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Searched refs:DR_REG_SLC_BASE (Results 1 – 6 of 6) sorted by relevance

/hal_espressif-latest/components/soc/esp32/include/soc/
Dslc_reg.h19 #define SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0)
213 #define SLC_0INT_RAW_REG (DR_REG_SLC_BASE + 0x4)
377 #define SLC_0INT_ST_REG (DR_REG_SLC_BASE + 0x8)
541 #define SLC_0INT_ENA_REG (DR_REG_SLC_BASE + 0xC)
705 #define SLC_0INT_CLR_REG (DR_REG_SLC_BASE + 0x10)
869 #define SLC_1INT_RAW_REG (DR_REG_SLC_BASE + 0x14)
1021 #define SLC_1INT_ST_REG (DR_REG_SLC_BASE + 0x18)
1173 #define SLC_1INT_ENA_REG (DR_REG_SLC_BASE + 0x1C)
1325 #define SLC_1INT_CLR_REG (DR_REG_SLC_BASE + 0x20)
1477 #define SLC_RX_STATUS_REG (DR_REG_SLC_BASE + 0x24)
[all …]
Dreg_base.h36 #define DR_REG_SLC_BASE 0x3ff58000 macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dslc_reg.h17 #define SDIO_SLCCONF0_REG (DR_REG_SLC_BASE + 0x0)
262 #define SDIO_SLC0INT_RAW_REG (DR_REG_SLC_BASE + 0x4)
470 #define SDIO_SLC0INT_ST_REG (DR_REG_SLC_BASE + 0x8)
678 #define SDIO_SLC0INT_ENA_REG (DR_REG_SLC_BASE + 0xc)
886 #define SDIO_SLC0INT_CLR_REG (DR_REG_SLC_BASE + 0x10)
1094 #define SDIO_SLC1INT_RAW_REG (DR_REG_SLC_BASE + 0x14)
1274 #define SDIO_SLC1INT_ST_REG (DR_REG_SLC_BASE + 0x18)
1454 #define SDIO_SLC1INT_ENA_REG (DR_REG_SLC_BASE + 0x1c)
1634 #define SDIO_SLC1INT_CLR_REG (DR_REG_SLC_BASE + 0x20)
1814 #define SDIO_SLCRX_STATUS_REG (DR_REG_SLC_BASE + 0x24)
[all …]
Dreg_base.h35 #define DR_REG_SLC_BASE 0x60017000 macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dreg_base.h29 #define DR_REG_SLC_BASE 0x60018000 macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dreg_base.h44 #define DR_REG_SLC_BASE 0x3f418000 macro