Searched refs:DR_REG_SENS_BASE (Results 1 – 6 of 6) sorted by relevance
22 #define SENS_SAR_READER1_CTRL_REG (DR_REG_SENS_BASE + 0x0000)54 #define SENS_SAR_READER1_STATUS_REG (DR_REG_SENS_BASE + 0x0004)62 #define SENS_SAR_MEAS1_CTRL1_REG (DR_REG_SENS_BASE + 0x0008)103 #define SENS_SAR_MEAS1_CTRL2_REG (DR_REG_SENS_BASE + 0x000c)141 #define SENS_SAR_MEAS1_MUX_REG (DR_REG_SENS_BASE + 0x0010)149 #define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x0014)157 #define SENS_SAR_AMP_CTRL1_REG (DR_REG_SENS_BASE + 0x0018)171 #define SENS_SAR_AMP_CTRL2_REG (DR_REG_SENS_BASE + 0x001c)221 #define SENS_SAR_AMP_CTRL3_REG (DR_REG_SENS_BASE + 0x0020)265 #define SENS_SAR_READER2_CTRL_REG (DR_REG_SENS_BASE + 0x0024)[all …]
33 #define DR_REG_SENS_BASE 0x3f408800 macro
23 #define SENS_SAR_READER1_CTRL_REG (DR_REG_SENS_BASE + 0x0)55 #define SENS_SAR_READER1_STATUS_REG (DR_REG_SENS_BASE + 0x4)63 #define SENS_SAR_MEAS1_CTRL1_REG (DR_REG_SENS_BASE + 0x8)89 #define SENS_SAR_MEAS1_CTRL2_REG (DR_REG_SENS_BASE + 0xC)127 #define SENS_SAR_MEAS1_MUX_REG (DR_REG_SENS_BASE + 0x10)135 #define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x14)143 #define SENS_SAR_AMP_CTRL1_REG (DR_REG_SENS_BASE + 0x18)157 #define SENS_SAR_AMP_CTRL2_REG (DR_REG_SENS_BASE + 0x1C)207 #define SENS_SAR_AMP_CTRL3_REG (DR_REG_SENS_BASE + 0x20)251 #define SENS_SAR_READER2_CTRL_REG (DR_REG_SENS_BASE + 0x24)[all …]
16 #define DR_REG_SENS_BASE 0x60008800 macro
19 #define SENS_SAR_READ_CTRL_REG (DR_REG_SENS_BASE + 0x0000)64 #define SENS_SAR_READ_STATUS1_REG (DR_REG_SENS_BASE + 0x0004)72 #define SENS_SAR_MEAS_WAIT1_REG (DR_REG_SENS_BASE + 0x0008)86 #define SENS_SAR_MEAS_WAIT2_REG (DR_REG_SENS_BASE + 0x000c)119 #define SENS_SAR_MEAS_CTRL_REG (DR_REG_SENS_BASE + 0x0010)163 #define SENS_SAR_READ_STATUS2_REG (DR_REG_SENS_BASE + 0x0014)171 #define SENS_ULP_CP_SLEEP_CYC0_REG (DR_REG_SENS_BASE + 0x0018)179 #define SENS_ULP_CP_SLEEP_CYC1_REG (DR_REG_SENS_BASE + 0x001c)187 #define SENS_ULP_CP_SLEEP_CYC2_REG (DR_REG_SENS_BASE + 0x0020)195 #define SENS_ULP_CP_SLEEP_CYC3_REG (DR_REG_SENS_BASE + 0x0024)[all …]
23 #define DR_REG_SENS_BASE 0x3ff48800 macro
