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Searched refs:DR_REG_PAU_BASE (Results 1 – 4 of 4) sorted by relevance

/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dpau_reg.h17 #define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
71 #define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
83 #define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
116 #define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc)
128 #define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10)
140 #define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14)
152 #define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18)
164 #define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c)
176 #define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20)
188 #define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24)
[all …]
Dreg_base.h50 #define DR_REG_PAU_BASE 0x60093000 macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dpau_reg.h17 #define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
71 #define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
83 #define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
116 #define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc)
128 #define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10)
140 #define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14)
152 #define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18)
164 #define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c)
176 #define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20)
188 #define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24)
[all …]
Dreg_base.h40 #define DR_REG_PAU_BASE 0x60093000 macro