Searched refs:DR_REG_MMU_TABLE (Results 1 – 9 of 9) sorted by relevance
178 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID; in mmu_ll_write_entry()194 return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4); in mmu_ll_read_entry()209 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; in mmu_ll_set_entry_invalid()238 return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & MMU_INVALID) ? false : true; in mmu_ll_check_entry_valid()254 bool target_code = (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_TYPE; in mmu_ll_get_entry_target()271 return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << 16; in mmu_ll_entry_id_to_paddr_base()291 if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) { in mmu_ll_find_entry_id_based_on_map_value()
196 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID; in mmu_ll_write_entry()212 return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4); in mmu_ll_read_entry()227 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; in mmu_ll_set_entry_invalid()256 return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & MMU_INVALID) ? false : true; in mmu_ll_check_entry_valid()271 if ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_ACCESS_FLASH) { in mmu_ll_get_entry_target()291 return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << 16; in mmu_ll_entry_id_to_paddr_base()311 if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) { in mmu_ll_find_entry_id_based_on_map_value()
178 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; in mmu_ll_write_entry()194 return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4); in mmu_ll_read_entry()209 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; in mmu_ll_set_entry_invalid()238 return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & MMU_INVALID) ? false : true; in mmu_ll_check_entry_valid()270 return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << 16; in mmu_ll_entry_id_to_paddr_base()290 if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) { in mmu_ll_find_entry_id_based_on_map_value()
211 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID; in mmu_ll_write_entry()227 return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4); in mmu_ll_read_entry()242 *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID; in mmu_ll_set_entry_invalid()271 return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & MMU_INVALID) ? false : true; in mmu_ll_check_entry_valid()317 return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << shift_code; in mmu_ll_entry_id_to_paddr_base()337 if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) { in mmu_ll_find_entry_id_based_on_map_value()
166 …instr_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START))[instr_mmu… in instruction_flash_page_info_init()169 instr_start_page = *((volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START)); in instruction_flash_page_info_init()219 …rodata_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START))[rodata_m… in rodata_flash_page_info_init()222 rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START); in rodata_flash_page_info_init()
10 #define DR_REG_MMU_TABLE 0x600c5000 macro
11 #define DR_REG_MMU_TABLE 0x61801000 macro
24 #define DR_REG_MMU_TABLE 0x600C5000 macro
