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Searched refs:DR_REG_LP_TIMER_BASE (Results 1 – 4 of 4) sorted by relevance

/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dlp_timer_reg.h17 #define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
29 #define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
48 #define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8)
60 #define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc)
79 #define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
112 #define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
124 #define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
136 #define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
148 #define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
160 #define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
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Dreg_base.h63 #define DR_REG_LP_TIMER_BASE 0x600B0C00 macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dlp_timer_reg.h17 #define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0)
29 #define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4)
48 #define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10)
81 #define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14)
93 #define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18)
105 #define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c)
117 #define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20)
129 #define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24)
141 #define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28)
160 #define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c)
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Dreg_base.h58 #define DR_REG_LP_TIMER_BASE 0x600B0C00 macro