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Searched refs:DR_REG_INTERRUPT_CORE0_BASE (Results 1 – 3 of 3) sorted by relevance

/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dinterrupt_core0_reg.h23 #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE macro
25 #define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
33 #define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
41 #define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
49 #define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
57 #define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x010)
65 #define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x014)
73 #define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x018)
81 #define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x01C)
89 #define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x020)
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/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dinterrupt_core0_reg.h23 #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE macro
25 #define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
33 #define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
41 #define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
49 #define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
57 #define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x010)
65 #define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x014)
73 #define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x018)
81 #define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x01C)
89 #define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x020)
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/hal_espressif-latest/tools/esptool_py/flasher_stub/include/
Dsoc_support.h319 #define DR_REG_INTERRUPT_CORE0_BASE 0x600c2000 macro
320 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068) /* USB-JTAG-S…
329 #define DR_REG_INTERRUPT_CORE0_BASE 0x600c2000 macro
330 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098) /* DWC-OTG */
331 #define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) /* USB-JTAG-S…