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Searched refs:DR_REG_INTERRUPT_BASE (Results 1 – 12 of 12) sorted by relevance

/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dinterrupt_reg.h22 #define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x000)
30 #define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x004)
38 #define DPORT_PRO_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x008)
46 #define DPORT_PRO_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x00C)
54 #define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x010)
62 #define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x014)
70 #define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x018)
78 #define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x01C)
86 #define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x020)
94 #define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x024)
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Dreg_base.h8 #define DR_REG_INTERRUPT_BASE 0x3f4c2000 macro
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dinterrupt_core0_reg.h16 #define INTERRUPT_CORE0_WIFI_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0)
28 #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4)
40 #define INTERRUPT_CORE0_WIFI_PWR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8)
52 #define INTERRUPT_CORE0_WIFI_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc)
64 #define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10)
76 #define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14)
88 #define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x18)
100 #define INTERRUPT_CORE0_LP_TIMER_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x1c)
112 #define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x20)
124 #define INTERRUPT_CORE0_BLE_TIMER_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x24)
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Dreg_base.h8 #define DR_REG_INTERRUPT_BASE 0x600c2000 macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dinterrupt_reg.h19 #define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dinterrupt_reg.h17 #define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dreg_base.h8 #define DR_REG_INTERRUPT_BASE 0x600c2000 macro
Dinterrupt_core0_reg.h23 #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dreg_base.h61 #define DR_REG_INTERRUPT_BASE 0x600C2000 macro
Dinterrupt_core0_reg.h23 #define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
Dinterrupt_core1_reg.h23 #define DR_REG_INTERRUPT_CORE1_BASE DR_REG_INTERRUPT_BASE
/hal_espressif-latest/components/riscv/
Dinterrupt.c67 REG_WRITE(DR_REG_INTERRUPT_BASE + 4 * intr_src, intr_num); in intr_matrix_route()