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Searched refs:DR_REG_HINF_BASE (Results 1 – 7 of 7) sorted by relevance

/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dhinf_reg.h18 #define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
32 #define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
130 #define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C)
156 #define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20)
164 #define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24)
172 #define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28)
180 #define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C)
188 #define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30)
196 #define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34)
204 #define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38)
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Dreg_base.h19 #define DR_REG_HINF_BASE 0x6000B000 macro
/hal_espressif-latest/components/soc/esp32/include/soc/
Dhinf_reg.h19 #define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
33 #define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
131 #define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C)
157 #define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20)
165 #define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24)
173 #define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28)
181 #define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C)
189 #define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30)
197 #define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34)
205 #define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38)
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Dreg_base.h26 #define DR_REG_HINF_BASE 0x3ff4B000 macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dhinf_reg.h17 #define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
36 #define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
153 #define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8)
193 #define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc)
205 #define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c)
329 #define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20)
341 #define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24)
353 #define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28)
365 #define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c)
377 #define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30)
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Dreg_base.h34 #define DR_REG_HINF_BASE 0x60016000 macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dreg_base.h36 #define DR_REG_HINF_BASE 0x3f40B000 macro