Searched refs:DR_REG_EXTMEM_BASE (Results 1 – 10 of 10) sorted by relevance
14 #define EXTMEM_L1_CACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4)28 #define EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20)36 #define EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x24)58 #define EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28)81 #define EXTMEM_L1_CACHE_FREEZE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x2C)104 #define EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x30)120 #define EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x34)136 #define EXTMEM_L1_CACHE_PRELOCK_CONF_REG (DR_REG_EXTMEM_BASE + 0x78)150 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x7C)160 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80)[all …]
80 #define DR_REG_EXTMEM_BASE 0x600C8000 macro
22 #define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000)30 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004)44 #define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008)66 #define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x00C)80 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x010)89 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014)98 #define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018)114 #define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x01C)136 #define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x020)145 #define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x024)[all …]
9 #define DR_REG_EXTMEM_BASE 0x600c4000 macro
23 #define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0)44 #define EXTMEM_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4)58 #define EXTMEM_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8)81 #define EXTMEM_DCACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0xC)95 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x10)104 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x14)113 #define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x18)129 #define EXTMEM_DCACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x1C)151 #define EXTMEM_DCACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x20)160 #define EXTMEM_DCACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x24)[all …]
62 #define DR_REG_EXTMEM_BASE 0x600C4000 macro
22 #define EXTMEM_PRO_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000)147 #define EXTMEM_PRO_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004)170 #define EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008)193 #define EXTMEM_PRO_DCACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x00C)202 #define EXTMEM_PRO_DCACHE_LOCK0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x010)211 #define EXTMEM_PRO_DCACHE_LOCK1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014)220 #define EXTMEM_PRO_DCACHE_LOCK1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018)229 #define EXTMEM_PRO_DCACHE_MEM_SYNC0_REG (DR_REG_EXTMEM_BASE + 0x01C)238 #define EXTMEM_PRO_DCACHE_MEM_SYNC1_REG (DR_REG_EXTMEM_BASE + 0x020)247 #define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x024)[all …]
10 #define DR_REG_EXTMEM_BASE 0x61800000 macro
17 #define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0)29 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4)48 #define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8)75 #define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28)95 #define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x2c)108 #define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x30)121 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x54)134 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x58)147 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x5c)160 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x60)[all …]
9 #define DR_REG_EXTMEM_BASE 0x600c4000 // CACHE_CONFIG macro
