Home
last modified time | relevance | path

Searched refs:DR_REG_APB_SARADC_BASE (Results 1 – 12 of 12) sorted by relevance

/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dapb_saradc_reg.h22 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000)
110 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004)
154 #define APB_SARADC_FSM_REG (DR_REG_APB_SARADC_BASE + 0x008)
168 #define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C)
188 #define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010)
196 #define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014)
204 #define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018)
212 #define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C)
220 #define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x020)
228 #define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x024)
[all …]
Dreg_base.h60 #define DR_REG_APB_SARADC_BASE 0x3f440000 macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dapb_saradc_reg.h23 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
111 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
155 #define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
169 #define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xC)
189 #define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
197 #define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
205 #define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
213 #define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1C)
221 #define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x20)
229 #define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x24)
[all …]
Dreg_base.h57 #define DR_REG_APB_SARADC_BASE 0x60040000 macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dapb_saradc_reg.h22 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000)
72 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004)
110 #define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x008)
124 #define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C)
144 #define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010)
152 #define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014)
160 #define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018)
168 #define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C)
176 #define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x020)
208 #define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x024)
[all …]
Dreg_base.h45 #define DR_REG_APB_SARADC_BASE 0x60040000 macro
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dapb_saradc_reg.h17 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
78 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
125 #define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
144 #define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc)
170 #define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
182 #define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
194 #define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
206 #define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
218 #define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
258 #define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
[all …]
Dreg_base.h36 #define DR_REG_APB_SARADC_BASE 0x60040000 macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dapb_saradc_reg.h17 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
85 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
132 #define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
151 #define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc)
177 #define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
189 #define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
201 #define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
213 #define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
225 #define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
265 #define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
[all …]
Dreg_base.h21 #define DR_REG_APB_SARADC_BASE 0x6000E000 macro
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dapb_saradc_reg.h17 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
85 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
132 #define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
151 #define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc)
177 #define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
189 #define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
201 #define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
213 #define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
225 #define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
265 #define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
[all …]
Dreg_base.h26 #define DR_REG_APB_SARADC_BASE 0x6000E000 macro