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Searched refs:DPORT_REG_GET_BIT (Results 1 – 19 of 19) sorted by relevance

/hal_espressif-latest/components/esp_psram/esp32/
Desp_psram_extram_cache.c36 if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE)==0) { in esp_psram_extram_writeback_cache()
41 if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE)==0) { in esp_psram_extram_writeback_cache()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dclk_gate_ll.h187 …return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false… in periph_ll_periph_enabled()
188DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; in periph_ll_periph_enabled()
Duart_ll.h74 return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 && in uart_ll_is_enabled()
75 DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0; in uart_ll_is_enabled()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dclk_gate_ll.h236 …return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false… in periph_ll_periph_enabled()
237DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; in periph_ll_periph_enabled()
Duart_ll.h75 return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 && in uart_ll_is_enabled()
76 DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0; in uart_ll_is_enabled()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dclk_gate_ll.h262 …return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false… in periph_ll_periph_enabled()
263 DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; in periph_ll_periph_enabled()
Duart_ll.h71 return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 && in uart_ll_is_enabled()
72 DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0; in uart_ll_is_enabled()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dclk_gate_ll.h251 …return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false… in periph_ll_periph_enabled()
252 DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; in periph_ll_periph_enabled()
Dcache_ll.h75 enabled = DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
77 enabled = DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dclk_gate_ll.h283 …return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false… in periph_ll_periph_enabled()
284DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; in periph_ll_periph_enabled()
Duart_ll.h77 return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 && in uart_ll_is_enabled()
78 DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0; in uart_ll_is_enabled()
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Ddport_access.h43 #define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Ddport_access.h40 #define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) macro
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Ddport_access.h42 #define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Ddport_access.h43 #define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) macro
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Ddport_access.h43 #define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Ddport_access.h41 #define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) macro
/hal_espressif-latest/components/esp_hw_support/
Dcpu.c114 …if (esp_cpu_dbgr_is_attached() && DPORT_REG_GET_BIT(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_… in esp_cpu_wait_for_intr()
/hal_espressif-latest/components/soc/esp32/include/soc/
Ddport_access.h134 #define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) macro