1 /* 2 * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_SYSTEM_REG_H_ 7 #define _SOC_SYSTEM_REG_H_ 8 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #include "soc.h" 14 #define DPORT_ROM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x000) 15 /* DPORT_ROM_FO : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ 16 /*description: */ 17 #define DPORT_ROM_FO 0x00000003 18 #define DPORT_ROM_FO_M ((DPORT_ROM_FO_V)<<(DPORT_ROM_FO_S)) 19 #define DPORT_ROM_FO_V 0x3 20 #define DPORT_ROM_FO_S 0 21 22 #define DPORT_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x004) 23 /* DPORT_ROM_FORCE_PU : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ 24 /*description: */ 25 #define DPORT_ROM_FORCE_PU 0x00000003 26 #define DPORT_ROM_FORCE_PU_M ((DPORT_ROM_FORCE_PU_V)<<(DPORT_ROM_FORCE_PU_S)) 27 #define DPORT_ROM_FORCE_PU_V 0x3 28 #define DPORT_ROM_FORCE_PU_S 2 29 /* DPORT_ROM_FORCE_PD : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 30 /*description: */ 31 #define DPORT_ROM_FORCE_PD 0x00000003 32 #define DPORT_ROM_FORCE_PD_M ((DPORT_ROM_FORCE_PD_V)<<(DPORT_ROM_FORCE_PD_S)) 33 #define DPORT_ROM_FORCE_PD_V 0x3 34 #define DPORT_ROM_FORCE_PD_S 0 35 36 #define DPORT_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x008) 37 /* DPORT_SRAM_FO : R/W ;bitpos:[21:0] ;default: ~22'b0 ; */ 38 /*description: */ 39 #define DPORT_SRAM_FO 0x003FFFFF 40 #define DPORT_SRAM_FO_M ((DPORT_SRAM_FO_V)<<(DPORT_SRAM_FO_S)) 41 #define DPORT_SRAM_FO_V 0x3FFFFF 42 #define DPORT_SRAM_FO_S 0 43 44 #define DPORT_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x00C) 45 /* DPORT_SRAM_FORCE_PD : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ 46 /*description: */ 47 #define DPORT_SRAM_FORCE_PD 0x003FFFFF 48 #define DPORT_SRAM_FORCE_PD_M ((DPORT_SRAM_FORCE_PD_V)<<(DPORT_SRAM_FORCE_PD_S)) 49 #define DPORT_SRAM_FORCE_PD_V 0x3FFFFF 50 #define DPORT_SRAM_FORCE_PD_S 0 51 52 #define DPORT_PERI_CLK_EN_REG DPORT_CPU_PERI_CLK_EN_REG 53 #define DPORT_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x010) 54 /* DPORT_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ 55 /*description: */ 56 #define DPORT_CLK_EN_DEDICATED_GPIO (BIT(7)) 57 #define DPORT_CLK_EN_DEDICATED_GPIO_M (BIT(7)) 58 #define DPORT_CLK_EN_DEDICATED_GPIO_V 0x1 59 #define DPORT_CLK_EN_DEDICATED_GPIO_S 7 60 /* DPORT_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ 61 /*description: */ 62 #define DPORT_CLK_EN_ASSIST_DEBUG (BIT(6)) 63 #define DPORT_CLK_EN_ASSIST_DEBUG_M (BIT(6)) 64 #define DPORT_CLK_EN_ASSIST_DEBUG_V 0x1 65 #define DPORT_CLK_EN_ASSIST_DEBUG_S 6 66 67 /* NB: Digital signature reset will hold AES & RSA in reset */ 68 #define DPORT_PERI_EN_ASSIST_DEBUG DPORT_CLK_EN_ASSIST_DEBUG 69 70 #define DPORT_PERI_RST_EN_REG DPORT_CPU_PERI_RST_EN_REG 71 #define DPORT_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x014) 72 /* DPORT_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ 73 /*description: */ 74 #define DPORT_RST_EN_DEDICATED_GPIO (BIT(7)) 75 #define DPORT_RST_EN_DEDICATED_GPIO_M (BIT(7)) 76 #define DPORT_RST_EN_DEDICATED_GPIO_V 0x1 77 #define DPORT_RST_EN_DEDICATED_GPIO_S 7 78 /* DPORT_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ 79 /*description: */ 80 #define DPORT_RST_EN_ASSIST_DEBUG (BIT(6)) 81 #define DPORT_RST_EN_ASSIST_DEBUG_M (BIT(6)) 82 #define DPORT_RST_EN_ASSIST_DEBUG_V 0x1 83 #define DPORT_RST_EN_ASSIST_DEBUG_S 6 84 85 #define DPORT_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x018) 86 /* DPORT_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ 87 /*description: */ 88 #define DPORT_CPU_WAITI_DELAY_NUM 0x0000000F 89 #define DPORT_CPU_WAITI_DELAY_NUM_M ((DPORT_CPU_WAITI_DELAY_NUM_V)<<(DPORT_CPU_WAITI_DELAY_NUM_S)) 90 #define DPORT_CPU_WAITI_DELAY_NUM_V 0xF 91 #define DPORT_CPU_WAITI_DELAY_NUM_S 4 92 /* DPORT_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ 93 /*description: */ 94 #define DPORT_CPU_WAIT_MODE_FORCE_ON (BIT(3)) 95 #define DPORT_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) 96 #define DPORT_CPU_WAIT_MODE_FORCE_ON_V 0x1 97 #define DPORT_CPU_WAIT_MODE_FORCE_ON_S 3 98 /* DPORT_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ 99 /*description: */ 100 #define DPORT_PLL_FREQ_SEL (BIT(2)) 101 #define DPORT_PLL_FREQ_SEL_M (BIT(2)) 102 #define DPORT_PLL_FREQ_SEL_V 0x1 103 #define DPORT_PLL_FREQ_SEL_S 2 104 /* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 105 /*description: */ 106 #define DPORT_CPUPERIOD_SEL 0x00000003 107 #define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) 108 #define DPORT_CPUPERIOD_SEL_V 0x3 109 #define DPORT_CPUPERIOD_SEL_S 0 110 111 #define DPORT_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x01C) 112 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 113 /*description: */ 114 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF 115 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S)) 116 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF 117 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0 118 119 #define DPORT_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x020) 120 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 121 /*description: */ 122 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF 123 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S)) 124 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF 125 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0 126 127 #define DPORT_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x024) 128 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 129 /*description: */ 130 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF 131 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S)) 132 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF 133 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0 134 135 #define DPORT_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x028) 136 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 137 /*description: */ 138 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF 139 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S)) 140 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF 141 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0 142 143 #define DPORT_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x02C) 144 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 145 /*description: */ 146 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF 147 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S)) 148 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF 149 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0 150 151 #define DPORT_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x030) 152 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 153 /*description: */ 154 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF 155 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S)) 156 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF 157 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0 158 159 #define DPORT_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x034) 160 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 161 /*description: */ 162 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF 163 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S)) 164 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF 165 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0 166 167 #define DPORT_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x038) 168 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 169 /*description: */ 170 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF 171 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S)) 172 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF 173 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0 174 175 #define DPORT_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x03C) 176 /* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ 177 /*description: */ 178 #define DPORT_LSLP_MEM_PD_MASK (BIT(0)) 179 #define DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) 180 #define DPORT_LSLP_MEM_PD_MASK_V 0x1 181 #define DPORT_LSLP_MEM_PD_MASK_S 0 182 183 #define DPORT_PERIP_CLK_EN_REG DPORT_PERIP_CLK_EN0_REG 184 #define DPORT_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x040) 185 /* DPORT_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ 186 /*description: */ 187 #define DPORT_ADC2_ARB_CLK_EN (BIT(30)) 188 #define DPORT_ADC2_ARB_CLK_EN_M (BIT(30)) 189 #define DPORT_ADC2_ARB_CLK_EN_V 0x1 190 #define DPORT_ADC2_ARB_CLK_EN_S 30 191 /* DPORT_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ 192 /*description: */ 193 #define DPORT_SYSTIMER_CLK_EN (BIT(29)) 194 #define DPORT_SYSTIMER_CLK_EN_M (BIT(29)) 195 #define DPORT_SYSTIMER_CLK_EN_V 0x1 196 #define DPORT_SYSTIMER_CLK_EN_S 29 197 /* DPORT_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ 198 /*description: */ 199 #define DPORT_APB_SARADC_CLK_EN (BIT(28)) 200 #define DPORT_APB_SARADC_CLK_EN_M (BIT(28)) 201 #define DPORT_APB_SARADC_CLK_EN_V 0x1 202 #define DPORT_APB_SARADC_CLK_EN_S 28 203 /* DPORT_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ 204 /*description: */ 205 #define DPORT_SPI3_DMA_CLK_EN (BIT(27)) 206 #define DPORT_SPI3_DMA_CLK_EN_M (BIT(27)) 207 #define DPORT_SPI3_DMA_CLK_EN_V 0x1 208 #define DPORT_SPI3_DMA_CLK_EN_S 27 209 /* DPORT_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ 210 /*description: */ 211 #define DPORT_PWM3_CLK_EN (BIT(26)) 212 #define DPORT_PWM3_CLK_EN_M (BIT(26)) 213 #define DPORT_PWM3_CLK_EN_V 0x1 214 #define DPORT_PWM3_CLK_EN_S 26 215 /* DPORT_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ 216 /*description: */ 217 #define DPORT_PWM2_CLK_EN (BIT(25)) 218 #define DPORT_PWM2_CLK_EN_M (BIT(25)) 219 #define DPORT_PWM2_CLK_EN_V 0x1 220 #define DPORT_PWM2_CLK_EN_S 25 221 /* DPORT_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ 222 /*description: */ 223 #define DPORT_UART_MEM_CLK_EN (BIT(24)) 224 #define DPORT_UART_MEM_CLK_EN_M (BIT(24)) 225 #define DPORT_UART_MEM_CLK_EN_V 0x1 226 #define DPORT_UART_MEM_CLK_EN_S 24 227 /* DPORT_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ 228 /*description: */ 229 #define DPORT_USB_CLK_EN (BIT(23)) 230 #define DPORT_USB_CLK_EN_M (BIT(23)) 231 #define DPORT_USB_CLK_EN_V 0x1 232 #define DPORT_USB_CLK_EN_S 23 233 /* DPORT_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ 234 /*description: */ 235 #define DPORT_SPI2_DMA_CLK_EN (BIT(22)) 236 #define DPORT_SPI2_DMA_CLK_EN_M (BIT(22)) 237 #define DPORT_SPI2_DMA_CLK_EN_V 0x1 238 #define DPORT_SPI2_DMA_CLK_EN_S 22 239 /* DPORT_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ 240 /*description: */ 241 #define DPORT_I2S1_CLK_EN (BIT(21)) 242 #define DPORT_I2S1_CLK_EN_M (BIT(21)) 243 #define DPORT_I2S1_CLK_EN_V 0x1 244 #define DPORT_I2S1_CLK_EN_S 21 245 /* DPORT_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 246 /*description: */ 247 #define DPORT_PWM1_CLK_EN (BIT(20)) 248 #define DPORT_PWM1_CLK_EN_M (BIT(20)) 249 #define DPORT_PWM1_CLK_EN_V 0x1 250 #define DPORT_PWM1_CLK_EN_S 20 251 /* DPORT_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ 252 /*description: */ 253 #define DPORT_TWAI_CLK_EN (BIT(19)) 254 #define DPORT_TWAI_CLK_EN_M (BIT(19)) 255 #define DPORT_TWAI_CLK_EN_V 0x1 256 #define DPORT_TWAI_CLK_EN_S 19 257 /* DPORT_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ 258 /*description: */ 259 #define DPORT_I2C_EXT1_CLK_EN (BIT(18)) 260 #define DPORT_I2C_EXT1_CLK_EN_M (BIT(18)) 261 #define DPORT_I2C_EXT1_CLK_EN_V 0x1 262 #define DPORT_I2C_EXT1_CLK_EN_S 18 263 /* DPORT_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ 264 /*description: */ 265 #define DPORT_PWM0_CLK_EN (BIT(17)) 266 #define DPORT_PWM0_CLK_EN_M (BIT(17)) 267 #define DPORT_PWM0_CLK_EN_V 0x1 268 #define DPORT_PWM0_CLK_EN_S 17 269 /* DPORT_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ 270 /*description: */ 271 #define DPORT_SPI3_CLK_EN (BIT(16)) 272 #define DPORT_SPI3_CLK_EN_M (BIT(16)) 273 #define DPORT_SPI3_CLK_EN_V 0x1 274 #define DPORT_SPI3_CLK_EN_S 16 275 /* DPORT_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ 276 /*description: */ 277 #define DPORT_TIMERGROUP1_CLK_EN (BIT(15)) 278 #define DPORT_TIMERGROUP1_CLK_EN_M (BIT(15)) 279 #define DPORT_TIMERGROUP1_CLK_EN_V 0x1 280 #define DPORT_TIMERGROUP1_CLK_EN_S 15 281 /* DPORT_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ 282 /*description: */ 283 #define DPORT_EFUSE_CLK_EN (BIT(14)) 284 #define DPORT_EFUSE_CLK_EN_M (BIT(14)) 285 #define DPORT_EFUSE_CLK_EN_V 0x1 286 #define DPORT_EFUSE_CLK_EN_S 14 287 /* DPORT_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ 288 /*description: */ 289 #define DPORT_TIMERGROUP_CLK_EN (BIT(13)) 290 #define DPORT_TIMERGROUP_CLK_EN_M (BIT(13)) 291 #define DPORT_TIMERGROUP_CLK_EN_V 0x1 292 #define DPORT_TIMERGROUP_CLK_EN_S 13 293 /* DPORT_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 294 /*description: */ 295 #define DPORT_UHCI1_CLK_EN (BIT(12)) 296 #define DPORT_UHCI1_CLK_EN_M (BIT(12)) 297 #define DPORT_UHCI1_CLK_EN_V 0x1 298 #define DPORT_UHCI1_CLK_EN_S 12 299 /* DPORT_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 300 /*description: */ 301 #define DPORT_LEDC_CLK_EN (BIT(11)) 302 #define DPORT_LEDC_CLK_EN_M (BIT(11)) 303 #define DPORT_LEDC_CLK_EN_V 0x1 304 #define DPORT_LEDC_CLK_EN_S 11 305 /* DPORT_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 306 /*description: */ 307 #define DPORT_PCNT_CLK_EN (BIT(10)) 308 #define DPORT_PCNT_CLK_EN_M (BIT(10)) 309 #define DPORT_PCNT_CLK_EN_V 0x1 310 #define DPORT_PCNT_CLK_EN_S 10 311 /* DPORT_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 312 /*description: */ 313 #define DPORT_RMT_CLK_EN (BIT(9)) 314 #define DPORT_RMT_CLK_EN_M (BIT(9)) 315 #define DPORT_RMT_CLK_EN_V 0x1 316 #define DPORT_RMT_CLK_EN_S 9 317 /* DPORT_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 318 /*description: */ 319 #define DPORT_UHCI0_CLK_EN (BIT(8)) 320 #define DPORT_UHCI0_CLK_EN_M (BIT(8)) 321 #define DPORT_UHCI0_CLK_EN_V 0x1 322 #define DPORT_UHCI0_CLK_EN_S 8 323 /* DPORT_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 324 /*description: */ 325 #define DPORT_I2C_EXT0_CLK_EN (BIT(7)) 326 #define DPORT_I2C_EXT0_CLK_EN_M (BIT(7)) 327 #define DPORT_I2C_EXT0_CLK_EN_V 0x1 328 #define DPORT_I2C_EXT0_CLK_EN_S 7 329 /* DPORT_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 330 /*description: */ 331 #define DPORT_SPI2_CLK_EN (BIT(6)) 332 #define DPORT_SPI2_CLK_EN_M (BIT(6)) 333 #define DPORT_SPI2_CLK_EN_V 0x1 334 #define DPORT_SPI2_CLK_EN_S 6 335 /* DPORT_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 336 /*description: */ 337 #define DPORT_UART1_CLK_EN (BIT(5)) 338 #define DPORT_UART1_CLK_EN_M (BIT(5)) 339 #define DPORT_UART1_CLK_EN_V 0x1 340 #define DPORT_UART1_CLK_EN_S 5 341 /* DPORT_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 342 /*description: */ 343 #define DPORT_I2S0_CLK_EN (BIT(4)) 344 #define DPORT_I2S0_CLK_EN_M (BIT(4)) 345 #define DPORT_I2S0_CLK_EN_V 0x1 346 #define DPORT_I2S0_CLK_EN_S 4 347 /* DPORT_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 348 /*description: */ 349 #define DPORT_WDG_CLK_EN (BIT(3)) 350 #define DPORT_WDG_CLK_EN_M (BIT(3)) 351 #define DPORT_WDG_CLK_EN_V 0x1 352 #define DPORT_WDG_CLK_EN_S 3 353 /* DPORT_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 354 /*description: */ 355 #define DPORT_UART_CLK_EN (BIT(2)) 356 #define DPORT_UART_CLK_EN_M (BIT(2)) 357 #define DPORT_UART_CLK_EN_V 0x1 358 #define DPORT_UART_CLK_EN_S 2 359 /* DPORT_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 360 /*description: */ 361 #define DPORT_SPI01_CLK_EN (BIT(1)) 362 #define DPORT_SPI01_CLK_EN_M (BIT(1)) 363 #define DPORT_SPI01_CLK_EN_V 0x1 364 #define DPORT_SPI01_CLK_EN_S 1 365 /* DPORT_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 366 /*description: */ 367 #define DPORT_TIMERS_CLK_EN (BIT(0)) 368 #define DPORT_TIMERS_CLK_EN_M (BIT(0)) 369 #define DPORT_TIMERS_CLK_EN_V 0x1 370 #define DPORT_TIMERS_CLK_EN_S 0 371 372 #define DPORT_CPU_PERIP_CLK_EN1_REG DPORT_PERIP_CLK_EN1_REG 373 #define DPORT_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x044) 374 /* DPORT_CRYPTO_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 375 /*description: */ 376 #define DPORT_CRYPTO_DMA_CLK_EN (BIT(6)) 377 #define DPORT_CRYPTO_DMA_CLK_EN_M (BIT(6)) 378 #define DPORT_CRYPTO_DMA_CLK_EN_V 0x1 379 #define DPORT_CRYPTO_DMA_CLK_EN_S 6 380 /* DPORT_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ 381 /*description: */ 382 #define DPORT_CRYPTO_HMAC_CLK_EN (BIT(5)) 383 #define DPORT_CRYPTO_HMAC_CLK_EN_M (BIT(5)) 384 #define DPORT_CRYPTO_HMAC_CLK_EN_V 0x1 385 #define DPORT_CRYPTO_HMAC_CLK_EN_S 5 386 /* DPORT_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 387 /*description: */ 388 #define DPORT_CRYPTO_DS_CLK_EN (BIT(4)) 389 #define DPORT_CRYPTO_DS_CLK_EN_M (BIT(4)) 390 #define DPORT_CRYPTO_DS_CLK_EN_V 0x1 391 #define DPORT_CRYPTO_DS_CLK_EN_S 4 392 /* DPORT_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 393 /*description: */ 394 #define DPORT_CRYPTO_RSA_CLK_EN (BIT(3)) 395 #define DPORT_CRYPTO_RSA_CLK_EN_M (BIT(3)) 396 #define DPORT_CRYPTO_RSA_CLK_EN_V 0x1 397 #define DPORT_CRYPTO_RSA_CLK_EN_S 3 398 /* DPORT_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 399 /*description: */ 400 #define DPORT_CRYPTO_SHA_CLK_EN (BIT(2)) 401 #define DPORT_CRYPTO_SHA_CLK_EN_M (BIT(2)) 402 #define DPORT_CRYPTO_SHA_CLK_EN_V 0x1 403 #define DPORT_CRYPTO_SHA_CLK_EN_S 2 404 /* DPORT_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 405 /*description: */ 406 #define DPORT_CRYPTO_AES_CLK_EN (BIT(1)) 407 #define DPORT_CRYPTO_AES_CLK_EN_M (BIT(1)) 408 #define DPORT_CRYPTO_AES_CLK_EN_V 0x1 409 #define DPORT_CRYPTO_AES_CLK_EN_S 1 410 411 #define DPORT_PERIP_RST_EN_REG DPORT_PERIP_RST_EN0_REG 412 #define DPORT_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x048) 413 /* DPORT_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ 414 /*description: */ 415 #define DPORT_ADC2_ARB_RST (BIT(30)) 416 #define DPORT_ADC2_ARB_RST_M (BIT(30)) 417 #define DPORT_ADC2_ARB_RST_V 0x1 418 #define DPORT_ADC2_ARB_RST_S 30 419 /* DPORT_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ 420 /*description: */ 421 #define DPORT_SYSTIMER_RST (BIT(29)) 422 #define DPORT_SYSTIMER_RST_M (BIT(29)) 423 #define DPORT_SYSTIMER_RST_V 0x1 424 #define DPORT_SYSTIMER_RST_S 29 425 /* DPORT_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ 426 /*description: */ 427 #define DPORT_APB_SARADC_RST (BIT(28)) 428 #define DPORT_APB_SARADC_RST_M (BIT(28)) 429 #define DPORT_APB_SARADC_RST_V 0x1 430 #define DPORT_APB_SARADC_RST_S 28 431 /* DPORT_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ 432 /*description: */ 433 #define DPORT_SPI3_DMA_RST (BIT(27)) 434 #define DPORT_SPI3_DMA_RST_M (BIT(27)) 435 #define DPORT_SPI3_DMA_RST_V 0x1 436 #define DPORT_SPI3_DMA_RST_S 27 437 /* DPORT_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ 438 /*description: */ 439 #define DPORT_PWM3_RST (BIT(26)) 440 #define DPORT_PWM3_RST_M (BIT(26)) 441 #define DPORT_PWM3_RST_V 0x1 442 #define DPORT_PWM3_RST_S 26 443 /* DPORT_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ 444 /*description: */ 445 #define DPORT_PWM2_RST (BIT(25)) 446 #define DPORT_PWM2_RST_M (BIT(25)) 447 #define DPORT_PWM2_RST_V 0x1 448 #define DPORT_PWM2_RST_S 25 449 /* DPORT_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ 450 /*description: */ 451 #define DPORT_UART_MEM_RST (BIT(24)) 452 #define DPORT_UART_MEM_RST_M (BIT(24)) 453 #define DPORT_UART_MEM_RST_V 0x1 454 #define DPORT_UART_MEM_RST_S 24 455 /* DPORT_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ 456 /*description: */ 457 #define DPORT_USB_RST (BIT(23)) 458 #define DPORT_USB_RST_M (BIT(23)) 459 #define DPORT_USB_RST_V 0x1 460 #define DPORT_USB_RST_S 23 461 /* DPORT_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ 462 /*description: */ 463 #define DPORT_SPI2_DMA_RST (BIT(22)) 464 #define DPORT_SPI2_DMA_RST_M (BIT(22)) 465 #define DPORT_SPI2_DMA_RST_V 0x1 466 #define DPORT_SPI2_DMA_RST_S 22 467 /* DPORT_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ 468 /*description: */ 469 #define DPORT_I2S1_RST (BIT(21)) 470 #define DPORT_I2S1_RST_M (BIT(21)) 471 #define DPORT_I2S1_RST_V 0x1 472 #define DPORT_I2S1_RST_S 21 473 /* DPORT_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ 474 /*description: */ 475 #define DPORT_PWM1_RST (BIT(20)) 476 #define DPORT_PWM1_RST_M (BIT(20)) 477 #define DPORT_PWM1_RST_V 0x1 478 #define DPORT_PWM1_RST_S 20 479 /* DPORT_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ 480 /*description: */ 481 #define DPORT_TWAI_RST (BIT(19)) 482 #define DPORT_TWAI_RST_M (BIT(19)) 483 #define DPORT_TWAI_RST_V 0x1 484 #define DPORT_TWAI_RST_S 19 485 /* DPORT_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ 486 /*description: */ 487 #define DPORT_I2C_EXT1_RST (BIT(18)) 488 #define DPORT_I2C_EXT1_RST_M (BIT(18)) 489 #define DPORT_I2C_EXT1_RST_V 0x1 490 #define DPORT_I2C_EXT1_RST_S 18 491 /* DPORT_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ 492 /*description: */ 493 #define DPORT_PWM0_RST (BIT(17)) 494 #define DPORT_PWM0_RST_M (BIT(17)) 495 #define DPORT_PWM0_RST_V 0x1 496 #define DPORT_PWM0_RST_S 17 497 /* DPORT_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ 498 /*description: */ 499 #define DPORT_SPI3_RST (BIT(16)) 500 #define DPORT_SPI3_RST_M (BIT(16)) 501 #define DPORT_SPI3_RST_V 0x1 502 #define DPORT_SPI3_RST_S 16 503 /* DPORT_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ 504 /*description: */ 505 #define DPORT_TIMERGROUP1_RST (BIT(15)) 506 #define DPORT_TIMERGROUP1_RST_M (BIT(15)) 507 #define DPORT_TIMERGROUP1_RST_V 0x1 508 #define DPORT_TIMERGROUP1_RST_S 15 509 /* DPORT_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ 510 /*description: */ 511 #define DPORT_EFUSE_RST (BIT(14)) 512 #define DPORT_EFUSE_RST_M (BIT(14)) 513 #define DPORT_EFUSE_RST_V 0x1 514 #define DPORT_EFUSE_RST_S 14 515 /* DPORT_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ 516 /*description: */ 517 #define DPORT_TIMERGROUP_RST (BIT(13)) 518 #define DPORT_TIMERGROUP_RST_M (BIT(13)) 519 #define DPORT_TIMERGROUP_RST_V 0x1 520 #define DPORT_TIMERGROUP_RST_S 13 521 /* DPORT_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ 522 /*description: */ 523 #define DPORT_UHCI1_RST (BIT(12)) 524 #define DPORT_UHCI1_RST_M (BIT(12)) 525 #define DPORT_UHCI1_RST_V 0x1 526 #define DPORT_UHCI1_RST_S 12 527 /* DPORT_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ 528 /*description: */ 529 #define DPORT_LEDC_RST (BIT(11)) 530 #define DPORT_LEDC_RST_M (BIT(11)) 531 #define DPORT_LEDC_RST_V 0x1 532 #define DPORT_LEDC_RST_S 11 533 /* DPORT_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ 534 /*description: */ 535 #define DPORT_PCNT_RST (BIT(10)) 536 #define DPORT_PCNT_RST_M (BIT(10)) 537 #define DPORT_PCNT_RST_V 0x1 538 #define DPORT_PCNT_RST_S 10 539 /* DPORT_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ 540 /*description: */ 541 #define DPORT_RMT_RST (BIT(9)) 542 #define DPORT_RMT_RST_M (BIT(9)) 543 #define DPORT_RMT_RST_V 0x1 544 #define DPORT_RMT_RST_S 9 545 /* DPORT_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ 546 /*description: */ 547 #define DPORT_UHCI0_RST (BIT(8)) 548 #define DPORT_UHCI0_RST_M (BIT(8)) 549 #define DPORT_UHCI0_RST_V 0x1 550 #define DPORT_UHCI0_RST_S 8 551 /* DPORT_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ 552 /*description: */ 553 #define DPORT_I2C_EXT0_RST (BIT(7)) 554 #define DPORT_I2C_EXT0_RST_M (BIT(7)) 555 #define DPORT_I2C_EXT0_RST_V 0x1 556 #define DPORT_I2C_EXT0_RST_S 7 557 /* DPORT_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ 558 /*description: */ 559 #define DPORT_SPI2_RST (BIT(6)) 560 #define DPORT_SPI2_RST_M (BIT(6)) 561 #define DPORT_SPI2_RST_V 0x1 562 #define DPORT_SPI2_RST_S 6 563 /* DPORT_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ 564 /*description: */ 565 #define DPORT_UART1_RST (BIT(5)) 566 #define DPORT_UART1_RST_M (BIT(5)) 567 #define DPORT_UART1_RST_V 0x1 568 #define DPORT_UART1_RST_S 5 569 /* DPORT_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 570 /*description: */ 571 #define DPORT_I2S0_RST (BIT(4)) 572 #define DPORT_I2S0_RST_M (BIT(4)) 573 #define DPORT_I2S0_RST_V 0x1 574 #define DPORT_I2S0_RST_S 4 575 /* DPORT_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 576 /*description: */ 577 #define DPORT_WDG_RST (BIT(3)) 578 #define DPORT_WDG_RST_M (BIT(3)) 579 #define DPORT_WDG_RST_V 0x1 580 #define DPORT_WDG_RST_S 3 581 /* DPORT_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ 582 /*description: */ 583 #define DPORT_UART_RST (BIT(2)) 584 #define DPORT_UART_RST_M (BIT(2)) 585 #define DPORT_UART_RST_V 0x1 586 #define DPORT_UART_RST_S 2 587 /* DPORT_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ 588 /*description: */ 589 #define DPORT_SPI01_RST (BIT(1)) 590 #define DPORT_SPI01_RST_M (BIT(1)) 591 #define DPORT_SPI01_RST_V 0x1 592 #define DPORT_SPI01_RST_S 1 593 /* DPORT_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ 594 /*description: */ 595 #define DPORT_TIMERS_RST (BIT(0)) 596 #define DPORT_TIMERS_RST_M (BIT(0)) 597 #define DPORT_TIMERS_RST_V 0x1 598 #define DPORT_TIMERS_RST_S 0 599 600 #define DPORT_CPU_PERIP_RST_EN1_REG DPORT_PERIP_RST_EN1_REG 601 #define DPORT_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x04C) 602 /* DPORT_CRYPTO_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ 603 /*description: */ 604 #define DPORT_CRYPTO_DMA_RST (BIT(6)) 605 #define DPORT_CRYPTO_DMA_RST_M (BIT(6)) 606 #define DPORT_CRYPTO_DMA_RST_V 0x1 607 #define DPORT_CRYPTO_DMA_RST_S 6 608 /* DPORT_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ 609 /*description: */ 610 #define DPORT_CRYPTO_HMAC_RST (BIT(5)) 611 #define DPORT_CRYPTO_HMAC_RST_M (BIT(5)) 612 #define DPORT_CRYPTO_HMAC_RST_V 0x1 613 #define DPORT_CRYPTO_HMAC_RST_S 5 614 /* DPORT_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ 615 /*description: */ 616 #define DPORT_CRYPTO_DS_RST (BIT(4)) 617 #define DPORT_CRYPTO_DS_RST_M (BIT(4)) 618 #define DPORT_CRYPTO_DS_RST_V 0x1 619 #define DPORT_CRYPTO_DS_RST_S 4 620 /* DPORT_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ 621 /*description: */ 622 #define DPORT_CRYPTO_RSA_RST (BIT(3)) 623 #define DPORT_CRYPTO_RSA_RST_M (BIT(3)) 624 #define DPORT_CRYPTO_RSA_RST_V 0x1 625 #define DPORT_CRYPTO_RSA_RST_S 3 626 /* DPORT_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ 627 /*description: */ 628 #define DPORT_CRYPTO_SHA_RST (BIT(2)) 629 #define DPORT_CRYPTO_SHA_RST_M (BIT(2)) 630 #define DPORT_CRYPTO_SHA_RST_V 0x1 631 #define DPORT_CRYPTO_SHA_RST_S 2 632 /* DPORT_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ 633 /*description: */ 634 #define DPORT_CRYPTO_AES_RST (BIT(1)) 635 #define DPORT_CRYPTO_AES_RST_M (BIT(1)) 636 #define DPORT_CRYPTO_AES_RST_V 0x1 637 #define DPORT_CRYPTO_AES_RST_S 1 638 639 #define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x050) 640 /* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ 641 /*description: */ 642 #define DPORT_BT_LPCK_DIV_NUM 0x00000FFF 643 #define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) 644 #define DPORT_BT_LPCK_DIV_NUM_V 0xFFF 645 #define DPORT_BT_LPCK_DIV_NUM_S 0 646 647 #define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x054) 648 /* DPORT_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ 649 /*description: */ 650 #define DPORT_LPCLK_RTC_EN (BIT(28)) 651 #define DPORT_LPCLK_RTC_EN_M (BIT(28)) 652 #define DPORT_LPCLK_RTC_EN_V 0x1 653 #define DPORT_LPCLK_RTC_EN_S 28 654 /* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ 655 /*description: */ 656 #define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) 657 #define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) 658 #define DPORT_LPCLK_SEL_XTAL32K_V 0x1 659 #define DPORT_LPCLK_SEL_XTAL32K_S 27 660 /* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ 661 /*description: */ 662 #define DPORT_LPCLK_SEL_XTAL (BIT(26)) 663 #define DPORT_LPCLK_SEL_XTAL_M (BIT(26)) 664 #define DPORT_LPCLK_SEL_XTAL_V 0x1 665 #define DPORT_LPCLK_SEL_XTAL_S 26 666 /* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ 667 /*description: */ 668 #define DPORT_LPCLK_SEL_8M (BIT(25)) 669 #define DPORT_LPCLK_SEL_8M_M (BIT(25)) 670 #define DPORT_LPCLK_SEL_8M_V 0x1 671 #define DPORT_LPCLK_SEL_8M_S 25 672 /* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ 673 /*description: */ 674 #define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) 675 #define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) 676 #define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 677 #define DPORT_LPCLK_SEL_RTC_SLOW_S 24 678 /* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ 679 /*description: */ 680 #define DPORT_BT_LPCK_DIV_A 0x00000FFF 681 #define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) 682 #define DPORT_BT_LPCK_DIV_A_V 0xFFF 683 #define DPORT_BT_LPCK_DIV_A_S 12 684 /* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ 685 /*description: */ 686 #define DPORT_BT_LPCK_DIV_B 0x00000FFF 687 #define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) 688 #define DPORT_BT_LPCK_DIV_B_V 0xFFF 689 #define DPORT_BT_LPCK_DIV_B_S 0 690 691 #define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x058) 692 /* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 693 /*description: */ 694 #define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) 695 #define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) 696 #define DPORT_CPU_INTR_FROM_CPU_0_V 0x1 697 #define DPORT_CPU_INTR_FROM_CPU_0_S 0 698 699 #define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x05C) 700 /* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 701 /*description: */ 702 #define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) 703 #define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) 704 #define DPORT_CPU_INTR_FROM_CPU_1_V 0x1 705 #define DPORT_CPU_INTR_FROM_CPU_1_S 0 706 707 #define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x060) 708 /* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 709 /*description: */ 710 #define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) 711 #define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) 712 #define DPORT_CPU_INTR_FROM_CPU_2_V 0x1 713 #define DPORT_CPU_INTR_FROM_CPU_2_S 0 714 715 #define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x064) 716 /* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 717 /*description: */ 718 #define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) 719 #define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) 720 #define DPORT_CPU_INTR_FROM_CPU_3_V 0x1 721 #define DPORT_CPU_INTR_FROM_CPU_3_S 0 722 723 #define DPORT_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x068) 724 /* DPORT_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ 725 /*description: */ 726 #define DPORT_RSA_MEM_FORCE_PD (BIT(2)) 727 #define DPORT_RSA_MEM_FORCE_PD_M (BIT(2)) 728 #define DPORT_RSA_MEM_FORCE_PD_V 0x1 729 #define DPORT_RSA_MEM_FORCE_PD_S 2 730 /* DPORT_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ 731 /*description: */ 732 #define DPORT_RSA_MEM_FORCE_PU (BIT(1)) 733 #define DPORT_RSA_MEM_FORCE_PU_M (BIT(1)) 734 #define DPORT_RSA_MEM_FORCE_PU_V 0x1 735 #define DPORT_RSA_MEM_FORCE_PU_S 1 736 /* DPORT_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ 737 /*description: */ 738 #define DPORT_RSA_MEM_PD (BIT(0)) 739 #define DPORT_RSA_MEM_PD_M (BIT(0)) 740 #define DPORT_RSA_MEM_PD_V 0x1 741 #define DPORT_RSA_MEM_PD_S 0 742 #define DPORT_RSA_PD DPORT_RSA_MEM_PD 743 744 #define DPORT_BUSTOEXTMEM_ENA_REG (DR_REG_SYSTEM_BASE + 0x06C) 745 /* DPORT_BUSTOEXTMEM_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 746 /*description: */ 747 #define DPORT_BUSTOEXTMEM_ENA (BIT(0)) 748 #define DPORT_BUSTOEXTMEM_ENA_M (BIT(0)) 749 #define DPORT_BUSTOEXTMEM_ENA_V 0x1 750 #define DPORT_BUSTOEXTMEM_ENA_S 0 751 752 #define DPORT_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x070) 753 /* DPORT_PRO_CACHE_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ 754 /*description: */ 755 #define DPORT_PRO_CACHE_RESET (BIT(2)) 756 #define DPORT_PRO_CACHE_RESET_M (BIT(2)) 757 #define DPORT_PRO_CACHE_RESET_V 0x1 758 #define DPORT_PRO_CACHE_RESET_S 2 759 /* DPORT_PRO_DCACHE_CLK_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ 760 /*description: */ 761 #define DPORT_PRO_DCACHE_CLK_ON (BIT(1)) 762 #define DPORT_PRO_DCACHE_CLK_ON_M (BIT(1)) 763 #define DPORT_PRO_DCACHE_CLK_ON_V 0x1 764 #define DPORT_PRO_DCACHE_CLK_ON_S 1 765 /* DPORT_PRO_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 766 /*description: */ 767 #define DPORT_PRO_ICACHE_CLK_ON (BIT(0)) 768 #define DPORT_PRO_ICACHE_CLK_ON_M (BIT(0)) 769 #define DPORT_PRO_ICACHE_CLK_ON_V 0x1 770 #define DPORT_PRO_ICACHE_CLK_ON_S 0 771 772 #define DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x074) 773 /* DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ 774 /*description: */ 775 #define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) 776 #define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) 777 #define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 778 #define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 779 /* DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ 780 /*description: */ 781 #define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) 782 #define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) 783 #define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 784 #define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 785 /* DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 786 /*description: */ 787 #define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) 788 #define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) 789 #define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 790 #define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 791 /* DPORT_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ 792 /*description: */ 793 #define DPORT_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) 794 #define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) 795 #define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 796 #define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_S 0 797 798 #define DPORT_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x078) 799 /* DPORT_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ 800 /*description: */ 801 #define DPORT_RTC_MEM_CRC_FINISH (BIT(31)) 802 #define DPORT_RTC_MEM_CRC_FINISH_M (BIT(31)) 803 #define DPORT_RTC_MEM_CRC_FINISH_V 0x1 804 #define DPORT_RTC_MEM_CRC_FINISH_S 31 805 /* DPORT_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ 806 /*description: */ 807 #define DPORT_RTC_MEM_CRC_LEN 0x000007FF 808 #define DPORT_RTC_MEM_CRC_LEN_M ((DPORT_RTC_MEM_CRC_LEN_V)<<(DPORT_RTC_MEM_CRC_LEN_S)) 809 #define DPORT_RTC_MEM_CRC_LEN_V 0x7FF 810 #define DPORT_RTC_MEM_CRC_LEN_S 20 811 /* DPORT_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ 812 /*description: */ 813 #define DPORT_RTC_MEM_CRC_ADDR 0x000007FF 814 #define DPORT_RTC_MEM_CRC_ADDR_M ((DPORT_RTC_MEM_CRC_ADDR_V)<<(DPORT_RTC_MEM_CRC_ADDR_S)) 815 #define DPORT_RTC_MEM_CRC_ADDR_V 0x7FF 816 #define DPORT_RTC_MEM_CRC_ADDR_S 9 817 /* DPORT_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ 818 /*description: */ 819 #define DPORT_RTC_MEM_CRC_START (BIT(8)) 820 #define DPORT_RTC_MEM_CRC_START_M (BIT(8)) 821 #define DPORT_RTC_MEM_CRC_START_V 0x1 822 #define DPORT_RTC_MEM_CRC_START_S 8 823 824 #define DPORT_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x07C) 825 /* DPORT_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 826 /*description: */ 827 #define DPORT_RTC_MEM_CRC_RES 0xFFFFFFFF 828 #define DPORT_RTC_MEM_CRC_RES_M ((DPORT_RTC_MEM_CRC_RES_V)<<(DPORT_RTC_MEM_CRC_RES_S)) 829 #define DPORT_RTC_MEM_CRC_RES_V 0xFFFFFFFF 830 #define DPORT_RTC_MEM_CRC_RES_S 0 831 832 #define DPORT_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x080) 833 /* DPORT_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ 834 /*description: */ 835 #define DPORT_REDUNDANT_ECO_RESULT (BIT(1)) 836 #define DPORT_REDUNDANT_ECO_RESULT_M (BIT(1)) 837 #define DPORT_REDUNDANT_ECO_RESULT_V 0x1 838 #define DPORT_REDUNDANT_ECO_RESULT_S 1 839 /* DPORT_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 840 /*description: */ 841 #define DPORT_REDUNDANT_ECO_DRIVE (BIT(0)) 842 #define DPORT_REDUNDANT_ECO_DRIVE_M (BIT(0)) 843 #define DPORT_REDUNDANT_ECO_DRIVE_V 0x1 844 #define DPORT_REDUNDANT_ECO_DRIVE_S 0 845 846 #define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x084) 847 /* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 848 /*description: */ 849 #define SYSTEM_CLK_EN (BIT(0)) 850 #define SYSTEM_CLK_EN_M (BIT(0)) 851 #define SYSTEM_CLK_EN_V 0x1 852 #define SYSTEM_CLK_EN_S 0 853 854 #define DPORT_SRAM_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x088) 855 /* DPORT_SRAM_FORCE_PU : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ 856 /*description: */ 857 #define DPORT_SRAM_FORCE_PU 0x003FFFFF 858 #define DPORT_SRAM_FORCE_PU_M ((DPORT_SRAM_FORCE_PU_V)<<(DPORT_SRAM_FORCE_PU_S)) 859 #define DPORT_SRAM_FORCE_PU_V 0x3FFFFF 860 #define DPORT_SRAM_FORCE_PU_S 0 861 862 #define DPORT_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x08C) 863 /* DPORT_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ 864 /*description: */ 865 #define DPORT_CLK_DIV_EN (BIT(19)) 866 #define DPORT_CLK_DIV_EN_M (BIT(19)) 867 #define DPORT_CLK_DIV_EN_V 0x1 868 #define DPORT_CLK_DIV_EN_S 19 869 /* DPORT_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ 870 /*description: */ 871 #define DPORT_CLK_XTAL_FREQ 0x0000007F 872 #define DPORT_CLK_XTAL_FREQ_M ((DPORT_CLK_XTAL_FREQ_V)<<(DPORT_CLK_XTAL_FREQ_S)) 873 #define DPORT_CLK_XTAL_FREQ_V 0x7F 874 #define DPORT_CLK_XTAL_FREQ_S 12 875 /* DPORT_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ 876 /*description: */ 877 #define DPORT_SOC_CLK_SEL 0x00000003 878 #define DPORT_SOC_CLK_SEL_M ((DPORT_SOC_CLK_SEL_V)<<(DPORT_SOC_CLK_SEL_S)) 879 #define DPORT_SOC_CLK_SEL_V 0x3 880 #define DPORT_SOC_CLK_SEL_S 10 881 /* DPORT_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ 882 /*description: */ 883 #define DPORT_PRE_DIV_CNT 0x000003FF 884 #define DPORT_PRE_DIV_CNT_M ((DPORT_PRE_DIV_CNT_V)<<(DPORT_PRE_DIV_CNT_S)) 885 #define DPORT_PRE_DIV_CNT_V 0x3FF 886 #define DPORT_PRE_DIV_CNT_S 0 887 888 #define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) 889 /* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1908020 ; */ 890 /*description: */ 891 #define SYSTEM_DATE 0x0FFFFFFF 892 #define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) 893 #define SYSTEM_DATE_V 0xFFFFFFF 894 #define SYSTEM_DATE_S 0 895 896 #ifdef __cplusplus 897 } 898 #endif 899 900 901 902 #endif /*_SOC_SYSTEM_REG_H_ */ 903
