1 /* 2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <stdbool.h> 12 #include <stddef.h> 13 #include "sdkconfig.h" 14 #include "hal/dac_types.h" 15 #if CONFIG_IDF_TARGET_ESP32S2 16 #include "hal/adc_types.h" 17 #endif 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 /** 24 * @brief The multiple of the amplitude of the cosine wave generator. The max amplitude is VDD3P3_RTC. 25 */ 26 typedef enum { 27 DAC_CW_SCALE_1 = 0x0, /*!< 1/1. Default. */ 28 DAC_CW_SCALE_2 = 0x1, /*!< 1/2. */ 29 DAC_CW_SCALE_4 = 0x2, /*!< 1/4. */ 30 DAC_CW_SCALE_8 = 0x3, /*!< 1/8. */ 31 } dac_cw_scale_t; 32 33 /** 34 * @brief Set the phase of the cosine wave generator output. 35 */ 36 typedef enum { 37 DAC_CW_PHASE_0 = 0x2, /*!< Phase shift +0° */ 38 DAC_CW_PHASE_180 = 0x3, /*!< Phase shift +180° */ 39 } dac_cw_phase_t; 40 41 #if CONFIG_IDF_TARGET_ESP32S2 42 /** 43 * @brief DAC digital controller (DMA mode) work mode. 44 */ 45 typedef enum { 46 DAC_CONV_NORMAL, /*!< The data in the DMA buffer is simultaneously output to the enable channel of the DAC. */ 47 DAC_CONV_ALTER, /*!< The data in the DMA buffer is alternately output to the enable channel of the DAC. */ 48 DAC_CONV_MAX 49 } dac_digi_convert_mode_t; 50 51 /** 52 * @brief DAC digital controller (DMA mode) configuration parameters. 53 */ 54 typedef struct { 55 dac_digi_convert_mode_t mode; /*!<DAC digital controller (DMA mode) work mode. See ``dac_digi_convert_mode_t``. */ 56 uint32_t interval; /*!<The number of interval clock cycles for the DAC digital controller to output voltage. 57 The unit is the divided clock. Range: 1 ~ 4095. 58 Expression: `dac_output_freq` = `controller_clk` / interval. Refer to ``adc_digi_clk_t``. 59 Note: The sampling rate of each channel is also related to the conversion mode (See ``dac_digi_convert_mode_t``) and pattern table settings. */ 60 adc_digi_clk_t dig_clk; /*!<DAC digital controller clock divider settings. Refer to ``adc_digi_clk_t``. 61 Note: The clocks of the DAC digital controller use the ADC digital controller clock divider. */ 62 } dac_digi_config_t; 63 #endif 64 65 /** 66 * @brief Config the cosine wave generator function in DAC module. 67 */ 68 typedef struct { 69 dac_channel_t en_ch; /*!< Enable the cosine wave generator of DAC channel. */ 70 dac_cw_scale_t scale; /*!< Set the amplitude of the cosine wave generator output. */ 71 dac_cw_phase_t phase; /*!< Set the phase of the cosine wave generator output. */ 72 uint32_t freq; /*!< Set frequency of cosine wave generator output. Range: 130(130Hz) ~ 55000(100KHz). */ 73 int8_t offset; /*!< Set the voltage value of the DC component of the cosine wave generator output. 74 Note: Unreasonable settings can cause waveform to be oversaturated. Range: -128 ~ 127. */ 75 } dac_cw_config_t; 76 77 #ifdef __cplusplus 78 } 79 #endif 80
