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Searched refs:APB_SARADC_APB_ADC_CLKM_CONF_REG (Results 1 – 13 of 13) sorted by relevance

/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32c2.c31 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_REG_CLK_SEL, 0x2); in bootloader_random_enable()
32 SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M); in bootloader_random_enable()
48 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_REG_CLKM_DIV_NUM, 15); in bootloader_random_enable()
64 CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M); in bootloader_random_disable()
Dbootloader_random_esp32c3.c31 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0x2); in bootloader_random_enable()
32 SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M); in bootloader_random_enable()
48 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLKM_DIV_NUM, 15); in bootloader_random_enable()
64 CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M); in bootloader_random_disable()
Dbootloader_random_esp32s3.c32 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); //APB clock in bootloader_random_enable()
34 SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); in bootloader_random_enable()
40 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLKM_DIV_NUM, 3); in bootloader_random_enable()
Dbootloader_random_esp32s2.c41 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); in bootloader_random_enable()
/hal_espressif-latest/zephyr/esp32c2/src/
Dsoc_random.c31 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_REG_CLK_SEL, 0x2); in soc_random_enable()
32 SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M); in soc_random_enable()
49 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_REG_CLKM_DIV_NUM, 15); in soc_random_enable()
65 CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M); in soc_random_disable()
/hal_espressif-latest/zephyr/esp32c3/src/
Dsoc_random.c31 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0x2); in soc_random_enable()
32 SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M); in soc_random_enable()
49 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLKM_DIV_NUM, 15); in soc_random_enable()
65 CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M); in soc_random_disable()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_random.c34 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); in soc_random_enable()
36 SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); in soc_random_enable()
44 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLKM_DIV_NUM, 3); in soc_random_enable()
/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_random.c36 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); in soc_random_enable()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dadc_ll.h705 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); in adc_ll_vref_output()
706 SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); in adc_ll_vref_output()
735 REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0); in adc_ll_vref_output()
736 CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN); in adc_ll_vref_output()
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dapb_saradc_reg.h538 #define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x05c) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dapb_saradc_reg.h525 #define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x054) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dapb_saradc_reg.h591 #define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x70) macro
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dapb_saradc_reg.h675 #define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54) macro