1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_APB_SARADC_REG_H_ 15 #define _SOC_APB_SARADC_REG_H_ 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 #include "soc.h" 22 #define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) 23 /* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */ 24 /*description: wait arbit signal stable after sar_done*/ 25 #define APB_SARADC_WAIT_ARB_CYCLE 0x00000003 26 #define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S)) 27 #define APB_SARADC_WAIT_ARB_CYCLE_V 0x3 28 #define APB_SARADC_WAIT_ARB_CYCLE_S 30 29 /* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ 30 /*description: force option to xpd sar blocks*/ 31 #define APB_SARADC_XPD_SAR_FORCE 0x00000003 32 #define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S)) 33 #define APB_SARADC_XPD_SAR_FORCE_V 0x3 34 #define APB_SARADC_XPD_SAR_FORCE_S 27 35 /* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ 36 /*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ 37 #define APB_SARADC_SAR_PATT_P_CLEAR (BIT(23)) 38 #define APB_SARADC_SAR_PATT_P_CLEAR_M (BIT(23)) 39 #define APB_SARADC_SAR_PATT_P_CLEAR_V 0x1 40 #define APB_SARADC_SAR_PATT_P_CLEAR_S 23 41 /* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */ 42 /*description: 0 ~ 15 means length 1 ~ 16*/ 43 #define APB_SARADC_SAR_PATT_LEN 0x00000007 44 #define APB_SARADC_SAR_PATT_LEN_M ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S)) 45 #define APB_SARADC_SAR_PATT_LEN_V 0x7 46 #define APB_SARADC_SAR_PATT_LEN_S 15 47 /* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ 48 /*description: SAR clock divider*/ 49 #define APB_SARADC_SAR_CLK_DIV 0x000000FF 50 #define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S)) 51 #define APB_SARADC_SAR_CLK_DIV_V 0xFF 52 #define APB_SARADC_SAR_CLK_DIV_S 7 53 /* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ 54 /*description: */ 55 #define APB_SARADC_SAR_CLK_GATED (BIT(6)) 56 #define APB_SARADC_SAR_CLK_GATED_M (BIT(6)) 57 #define APB_SARADC_SAR_CLK_GATED_V 0x1 58 #define APB_SARADC_SAR_CLK_GATED_S 6 59 /* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ 60 /*description: */ 61 #define APB_SARADC_START (BIT(1)) 62 #define APB_SARADC_START_M (BIT(1)) 63 #define APB_SARADC_START_V 0x1 64 #define APB_SARADC_START_S 1 65 /* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ 66 /*description: */ 67 #define APB_SARADC_START_FORCE (BIT(0)) 68 #define APB_SARADC_START_FORCE_M (BIT(0)) 69 #define APB_SARADC_START_FORCE_V 0x1 70 #define APB_SARADC_START_FORCE_S 0 71 72 #define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004) 73 /* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ 74 /*description: to enable saradc timer trigger*/ 75 #define APB_SARADC_TIMER_EN (BIT(24)) 76 #define APB_SARADC_TIMER_EN_M (BIT(24)) 77 #define APB_SARADC_TIMER_EN_V 0x1 78 #define APB_SARADC_TIMER_EN_S 24 79 /* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */ 80 /*description: to set saradc timer target*/ 81 #define APB_SARADC_TIMER_TARGET 0x00000FFF 82 #define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S)) 83 #define APB_SARADC_TIMER_TARGET_V 0xFFF 84 #define APB_SARADC_TIMER_TARGET_S 12 85 /* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ 86 /*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ 87 #define APB_SARADC_SAR2_INV (BIT(10)) 88 #define APB_SARADC_SAR2_INV_M (BIT(10)) 89 #define APB_SARADC_SAR2_INV_V 0x1 90 #define APB_SARADC_SAR2_INV_S 10 91 /* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ 92 /*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ 93 #define APB_SARADC_SAR1_INV (BIT(9)) 94 #define APB_SARADC_SAR1_INV_M (BIT(9)) 95 #define APB_SARADC_SAR1_INV_V 0x1 96 #define APB_SARADC_SAR1_INV_S 9 97 /* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ 98 /*description: max conversion number*/ 99 #define APB_SARADC_MAX_MEAS_NUM 0x000000FF 100 #define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S)) 101 #define APB_SARADC_MAX_MEAS_NUM_V 0xFF 102 #define APB_SARADC_MAX_MEAS_NUM_S 1 103 /* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ 104 /*description: */ 105 #define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) 106 #define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) 107 #define APB_SARADC_MEAS_NUM_LIMIT_V 0x1 108 #define APB_SARADC_MEAS_NUM_LIMIT_S 0 109 110 #define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x008) 111 /* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ 112 /*description: */ 113 #define APB_SARADC_FILTER_FACTOR0 0x00000007 114 #define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S)) 115 #define APB_SARADC_FILTER_FACTOR0_V 0x7 116 #define APB_SARADC_FILTER_FACTOR0_S 29 117 /* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ 118 /*description: */ 119 #define APB_SARADC_FILTER_FACTOR1 0x00000007 120 #define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S)) 121 #define APB_SARADC_FILTER_FACTOR1_V 0x7 122 #define APB_SARADC_FILTER_FACTOR1_S 26 123 124 #define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C) 125 /* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ 126 /*description: */ 127 #define APB_SARADC_STANDBY_WAIT 0x000000FF 128 #define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S)) 129 #define APB_SARADC_STANDBY_WAIT_V 0xFF 130 #define APB_SARADC_STANDBY_WAIT_S 16 131 /* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ 132 /*description: */ 133 #define APB_SARADC_RSTB_WAIT 0x000000FF 134 #define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S)) 135 #define APB_SARADC_RSTB_WAIT_V 0xFF 136 #define APB_SARADC_RSTB_WAIT_S 8 137 /* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ 138 /*description: */ 139 #define APB_SARADC_XPD_WAIT 0x000000FF 140 #define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S)) 141 #define APB_SARADC_XPD_WAIT_V 0xFF 142 #define APB_SARADC_XPD_WAIT_S 0 143 144 #define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010) 145 /* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ 146 /*description: */ 147 #define APB_SARADC_SAR1_STATUS 0xFFFFFFFF 148 #define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S)) 149 #define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF 150 #define APB_SARADC_SAR1_STATUS_S 0 151 152 #define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014) 153 /* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ 154 /*description: */ 155 #define APB_SARADC_SAR2_STATUS 0xFFFFFFFF 156 #define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S)) 157 #define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF 158 #define APB_SARADC_SAR2_STATUS_S 0 159 160 #define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018) 161 /* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ 162 /*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ 163 #define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFF 164 #define APB_SARADC_SAR_PATT_TAB1_M ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S)) 165 #define APB_SARADC_SAR_PATT_TAB1_V 0xFFFFFF 166 #define APB_SARADC_SAR_PATT_TAB1_S 0 167 168 #define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C) 169 /* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ 170 /*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ 171 #define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFF 172 #define APB_SARADC_SAR_PATT_TAB2_M ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S)) 173 #define APB_SARADC_SAR_PATT_TAB2_V 0xFFFFFF 174 #define APB_SARADC_SAR_PATT_TAB2_S 0 175 176 #define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x020) 177 /* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 178 /*description: */ 179 #define APB_SARADC1_ONETIME_SAMPLE (BIT(31)) 180 #define APB_SARADC1_ONETIME_SAMPLE_M (BIT(31)) 181 #define APB_SARADC1_ONETIME_SAMPLE_V 0x1 182 #define APB_SARADC1_ONETIME_SAMPLE_S 31 183 /* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 184 /*description: */ 185 #define APB_SARADC2_ONETIME_SAMPLE (BIT(30)) 186 #define APB_SARADC2_ONETIME_SAMPLE_M (BIT(30)) 187 #define APB_SARADC2_ONETIME_SAMPLE_V 0x1 188 #define APB_SARADC2_ONETIME_SAMPLE_S 30 189 /* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ 190 /*description: */ 191 #define APB_SARADC_ONETIME_START (BIT(29)) 192 #define APB_SARADC_ONETIME_START_M (BIT(29)) 193 #define APB_SARADC_ONETIME_START_V 0x1 194 #define APB_SARADC_ONETIME_START_S 29 195 /* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */ 196 /*description: */ 197 #define APB_SARADC_ONETIME_CHANNEL 0x0000000F 198 #define APB_SARADC_ONETIME_CHANNEL_M ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S)) 199 #define APB_SARADC_ONETIME_CHANNEL_V 0xF 200 #define APB_SARADC_ONETIME_CHANNEL_S 25 201 /* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ 202 /*description: */ 203 #define APB_SARADC_ONETIME_ATTEN 0x00000003 204 #define APB_SARADC_ONETIME_ATTEN_M ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S)) 205 #define APB_SARADC_ONETIME_ATTEN_V 0x3 206 #define APB_SARADC_ONETIME_ATTEN_S 23 207 208 #define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x024) 209 /* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ 210 /*description: adc2 arbiter uses fixed priority*/ 211 #define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) 212 #define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12)) 213 #define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1 214 #define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 215 /* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ 216 /*description: Set adc2 arbiter wifi priority*/ 217 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003 218 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)) 219 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3 220 #define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 221 /* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ 222 /*description: Set adc2 arbiter rtc priority*/ 223 #define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003 224 #define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S)) 225 #define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3 226 #define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 227 /* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ 228 /*description: Set adc2 arbiterapb priority*/ 229 #define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003 230 #define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S)) 231 #define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3 232 #define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 233 /* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ 234 /*description: adc2 arbiter force grant*/ 235 #define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) 236 #define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5)) 237 #define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1 238 #define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 239 /* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 240 /*description: adc2 arbiter force to enable wifi controller*/ 241 #define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) 242 #define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4)) 243 #define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1 244 #define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 245 /* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 246 /*description: adc2 arbiter force to enable rtc controller*/ 247 #define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) 248 #define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3)) 249 #define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1 250 #define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 251 /* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 252 /*description: adc2 arbiter force to enableapb controller*/ 253 #define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) 254 #define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2)) 255 #define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1 256 #define APB_SARADC_ADC_ARB_APB_FORCE_S 2 257 258 #define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x028) 259 /* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ 260 /*description: enable apb_adc1_filter*/ 261 #define APB_SARADC_FILTER_RESET (BIT(31)) 262 #define APB_SARADC_FILTER_RESET_M (BIT(31)) 263 #define APB_SARADC_FILTER_RESET_V 0x1 264 #define APB_SARADC_FILTER_RESET_S 31 265 /* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */ 266 /*description: apb_adc1_filter_factor*/ 267 #define APB_SARADC_FILTER_CHANNEL0 0x0000000F 268 #define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S)) 269 #define APB_SARADC_FILTER_CHANNEL0_V 0xF 270 #define APB_SARADC_FILTER_CHANNEL0_S 22 271 /* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */ 272 /*description: */ 273 #define APB_SARADC_FILTER_CHANNEL1 0x0000000F 274 #define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S)) 275 #define APB_SARADC_FILTER_CHANNEL1_V 0xF 276 #define APB_SARADC_FILTER_CHANNEL1_S 18 277 278 #define APB_SARADC_1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x02C) 279 /* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ 280 /*description: */ 281 #define APB_SARADC_ADC1_DATA 0x0001FFFF 282 #define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S)) 283 #define APB_SARADC_ADC1_DATA_V 0x1FFFF 284 #define APB_SARADC_ADC1_DATA_S 0 285 286 #define APB_SARADC_2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x030) 287 /* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ 288 /*description: */ 289 #define APB_SARADC_ADC2_DATA 0x0001FFFF 290 #define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S)) 291 #define APB_SARADC_ADC2_DATA_V 0x1FFFF 292 #define APB_SARADC_ADC2_DATA_S 0 293 294 #define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x034) 295 /* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ 296 /*description: saradc1's thres0 monitor thres*/ 297 #define APB_SARADC_THRES0_LOW 0x00001FFF 298 #define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S)) 299 #define APB_SARADC_THRES0_LOW_V 0x1FFF 300 #define APB_SARADC_THRES0_LOW_S 18 301 /* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ 302 /*description: saradc1's thres0 monitor thres*/ 303 #define APB_SARADC_THRES0_HIGH 0x00001FFF 304 #define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S)) 305 #define APB_SARADC_THRES0_HIGH_V 0x1FFF 306 #define APB_SARADC_THRES0_HIGH_S 5 307 /* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */ 308 /*description: */ 309 #define APB_SARADC_THRES0_CHANNEL 0x0000000F 310 #define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S)) 311 #define APB_SARADC_THRES0_CHANNEL_V 0xF 312 #define APB_SARADC_THRES0_CHANNEL_S 0 313 314 #define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038) 315 /* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ 316 /*description: saradc1's thres0 monitor thres*/ 317 #define APB_SARADC_THRES1_LOW 0x00001FFF 318 #define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S)) 319 #define APB_SARADC_THRES1_LOW_V 0x1FFF 320 #define APB_SARADC_THRES1_LOW_S 18 321 /* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ 322 /*description: saradc1's thres0 monitor thres*/ 323 #define APB_SARADC_THRES1_HIGH 0x00001FFF 324 #define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S)) 325 #define APB_SARADC_THRES1_HIGH_V 0x1FFF 326 #define APB_SARADC_THRES1_HIGH_S 5 327 /* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */ 328 /*description: */ 329 #define APB_SARADC_THRES1_CHANNEL 0x0000000F 330 #define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S)) 331 #define APB_SARADC_THRES1_CHANNEL_V 0xF 332 #define APB_SARADC_THRES1_CHANNEL_S 0 333 334 #define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x03C) 335 /* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 336 /*description: */ 337 #define APB_SARADC_THRES0_EN (BIT(31)) 338 #define APB_SARADC_THRES0_EN_M (BIT(31)) 339 #define APB_SARADC_THRES0_EN_V 0x1 340 #define APB_SARADC_THRES0_EN_S 31 341 /* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ 342 /*description: */ 343 #define APB_SARADC_THRES1_EN (BIT(30)) 344 #define APB_SARADC_THRES1_EN_M (BIT(30)) 345 #define APB_SARADC_THRES1_EN_V 0x1 346 #define APB_SARADC_THRES1_EN_S 30 347 /*description: */ 348 #define APB_SARADC_THRES_ALL_EN (BIT(27)) 349 #define APB_SARADC_THRES_ALL_EN_M (BIT(27)) 350 #define APB_SARADC_THRES_ALL_EN_V 0x1 351 #define APB_SARADC_THRES_ALL_EN_S 27 352 353 #define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x040) 354 /* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ 355 /*description: */ 356 #define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31)) 357 #define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31)) 358 #define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1 359 #define APB_SARADC_ADC1_DONE_INT_ENA_S 31 360 /* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ 361 /*description: */ 362 #define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30)) 363 #define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30)) 364 #define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1 365 #define APB_SARADC_ADC2_DONE_INT_ENA_S 30 366 /* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ 367 /*description: */ 368 #define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) 369 #define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29)) 370 #define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1 371 #define APB_SARADC_THRES0_HIGH_INT_ENA_S 29 372 /* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ 373 /*description: */ 374 #define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) 375 #define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28)) 376 #define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1 377 #define APB_SARADC_THRES1_HIGH_INT_ENA_S 28 378 /* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ 379 /*description: */ 380 #define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) 381 #define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27)) 382 #define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1 383 #define APB_SARADC_THRES0_LOW_INT_ENA_S 27 384 /* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ 385 /*description: */ 386 #define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) 387 #define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26)) 388 #define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1 389 #define APB_SARADC_THRES1_LOW_INT_ENA_S 26 390 391 #define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x044) 392 /* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ 393 /*description: */ 394 #define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31)) 395 #define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31)) 396 #define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1 397 #define APB_SARADC_ADC1_DONE_INT_RAW_S 31 398 /* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ 399 /*description: */ 400 #define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30)) 401 #define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30)) 402 #define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1 403 #define APB_SARADC_ADC2_DONE_INT_RAW_S 30 404 /* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ 405 /*description: */ 406 #define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) 407 #define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29)) 408 #define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1 409 #define APB_SARADC_THRES0_HIGH_INT_RAW_S 29 410 /* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ 411 /*description: */ 412 #define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) 413 #define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28)) 414 #define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1 415 #define APB_SARADC_THRES1_HIGH_INT_RAW_S 28 416 /* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ 417 /*description: */ 418 #define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) 419 #define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27)) 420 #define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1 421 #define APB_SARADC_THRES0_LOW_INT_RAW_S 27 422 /* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ 423 /*description: */ 424 #define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) 425 #define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26)) 426 #define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1 427 #define APB_SARADC_THRES1_LOW_INT_RAW_S 26 428 429 #define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x048) 430 /* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ 431 /*description: */ 432 #define APB_SARADC_ADC1_DONE_INT_ST (BIT(31)) 433 #define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31)) 434 #define APB_SARADC_ADC1_DONE_INT_ST_V 0x1 435 #define APB_SARADC_ADC1_DONE_INT_ST_S 31 436 /* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ 437 /*description: */ 438 #define APB_SARADC_ADC2_DONE_INT_ST (BIT(30)) 439 #define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30)) 440 #define APB_SARADC_ADC2_DONE_INT_ST_V 0x1 441 #define APB_SARADC_ADC2_DONE_INT_ST_S 30 442 /* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ 443 /*description: */ 444 #define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) 445 #define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29)) 446 #define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1 447 #define APB_SARADC_THRES0_HIGH_INT_ST_S 29 448 /* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ 449 /*description: */ 450 #define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) 451 #define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28)) 452 #define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1 453 #define APB_SARADC_THRES1_HIGH_INT_ST_S 28 454 /* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ 455 /*description: */ 456 #define APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) 457 #define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27)) 458 #define APB_SARADC_THRES0_LOW_INT_ST_V 0x1 459 #define APB_SARADC_THRES0_LOW_INT_ST_S 27 460 /* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ 461 /*description: */ 462 #define APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) 463 #define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26)) 464 #define APB_SARADC_THRES1_LOW_INT_ST_V 0x1 465 #define APB_SARADC_THRES1_LOW_INT_ST_S 26 466 467 #define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x04C) 468 /* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ 469 /*description: */ 470 #define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31)) 471 #define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31)) 472 #define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1 473 #define APB_SARADC_ADC1_DONE_INT_CLR_S 31 474 /* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ 475 /*description: */ 476 #define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30)) 477 #define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30)) 478 #define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1 479 #define APB_SARADC_ADC2_DONE_INT_CLR_S 30 480 /* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ 481 /*description: */ 482 #define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) 483 #define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29)) 484 #define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1 485 #define APB_SARADC_THRES0_HIGH_INT_CLR_S 29 486 /* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ 487 /*description: */ 488 #define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) 489 #define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28)) 490 #define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1 491 #define APB_SARADC_THRES1_HIGH_INT_CLR_S 28 492 /* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ 493 /*description: */ 494 #define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) 495 #define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27)) 496 #define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1 497 #define APB_SARADC_THRES0_LOW_INT_CLR_S 27 498 /* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ 499 /*description: */ 500 #define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) 501 #define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26)) 502 #define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1 503 #define APB_SARADC_THRES1_LOW_INT_CLR_S 26 504 505 #define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x050) 506 /* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */ 507 /*description: enable apb_adc use spi_dma*/ 508 #define APB_SARADC_APB_ADC_TRANS (BIT(31)) 509 #define APB_SARADC_APB_ADC_TRANS_M (BIT(31)) 510 #define APB_SARADC_APB_ADC_TRANS_V 0x1 511 #define APB_SARADC_APB_ADC_TRANS_S 31 512 /* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */ 513 /*description: reset_apb_adc_state*/ 514 #define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) 515 #define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30)) 516 #define APB_SARADC_APB_ADC_RESET_FSM_V 0x1 517 #define APB_SARADC_APB_ADC_RESET_FSM_S 30 518 /* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */ 519 /*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ 520 #define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF 521 #define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S)) 522 #define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF 523 #define APB_SARADC_APB_ADC_EOF_NUM_S 0 524 525 #define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x054) 526 /* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */ 527 /*description: Set this bit to enable clk_apll*/ 528 #define APB_SARADC_CLK_SEL 0x00000003 529 #define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S)) 530 #define APB_SARADC_CLK_SEL_V 0x3 531 #define APB_SARADC_CLK_SEL_S 21 532 /* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ 533 /*description: */ 534 #define APB_SARADC_CLK_EN (BIT(20)) 535 #define APB_SARADC_CLK_EN_M (BIT(20)) 536 #define APB_SARADC_CLK_EN_V 0x1 537 #define APB_SARADC_CLK_EN_S 20 538 /* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ 539 /*description: Fractional clock divider denominator value*/ 540 #define APB_SARADC_CLKM_DIV_A 0x0000003F 541 #define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S)) 542 #define APB_SARADC_CLKM_DIV_A_V 0x3F 543 #define APB_SARADC_CLKM_DIV_A_S 14 544 /* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ 545 /*description: Fractional clock divider numerator value*/ 546 #define APB_SARADC_CLKM_DIV_B 0x0000003F 547 #define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S)) 548 #define APB_SARADC_CLKM_DIV_B_V 0x3F 549 #define APB_SARADC_CLKM_DIV_B_S 8 550 /* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ 551 /*description: Integral I2S clock divider value*/ 552 #define APB_SARADC_CLKM_DIV_NUM 0x000000FF 553 #define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S)) 554 #define APB_SARADC_CLKM_DIV_NUM_V 0xFF 555 #define APB_SARADC_CLKM_DIV_NUM_S 0 556 557 #define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x058) 558 /* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */ 559 /*description: */ 560 #define APB_SARADC_TSENS_PU (BIT(22)) 561 #define APB_SARADC_TSENS_PU_M (BIT(22)) 562 #define APB_SARADC_TSENS_PU_V 0x1 563 #define APB_SARADC_TSENS_PU_S 22 564 /* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ 565 /*description: */ 566 #define APB_SARADC_TSENS_CLK_DIV 0x000000FF 567 #define APB_SARADC_TSENS_CLK_DIV_M ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S)) 568 #define APB_SARADC_TSENS_CLK_DIV_V 0xFF 569 #define APB_SARADC_TSENS_CLK_DIV_S 14 570 /* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ 571 /*description: */ 572 #define APB_SARADC_TSENS_IN_INV (BIT(13)) 573 #define APB_SARADC_TSENS_IN_INV_M (BIT(13)) 574 #define APB_SARADC_TSENS_IN_INV_V 0x1 575 #define APB_SARADC_TSENS_IN_INV_S 13 576 /* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ 577 /*description: */ 578 #define APB_SARADC_TSENS_OUT 0x000000FF 579 #define APB_SARADC_TSENS_OUT_M ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S)) 580 #define APB_SARADC_TSENS_OUT_V 0xFF 581 #define APB_SARADC_TSENS_OUT_S 0 582 583 #define APB_SARADC_APB_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x05C) 584 /* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */ 585 /*description: */ 586 #define APB_SARADC_TSENS_CLK_SEL (BIT(15)) 587 #define APB_SARADC_TSENS_CLK_SEL_M (BIT(15)) 588 #define APB_SARADC_TSENS_CLK_SEL_V 0x1 589 #define APB_SARADC_TSENS_CLK_SEL_S 15 590 /* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ 591 /*description: */ 592 #define APB_SARADC_TSENS_CLK_INV (BIT(14)) 593 #define APB_SARADC_TSENS_CLK_INV_M (BIT(14)) 594 #define APB_SARADC_TSENS_CLK_INV_V 0x1 595 #define APB_SARADC_TSENS_CLK_INV_S 14 596 /* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ 597 /*description: */ 598 #define APB_SARADC_TSENS_XPD_FORCE 0x00000003 599 #define APB_SARADC_TSENS_XPD_FORCE_M ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S)) 600 #define APB_SARADC_TSENS_XPD_FORCE_V 0x3 601 #define APB_SARADC_TSENS_XPD_FORCE_S 12 602 /* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ 603 /*description: */ 604 #define APB_SARADC_TSENS_XPD_WAIT 0x00000FFF 605 #define APB_SARADC_TSENS_XPD_WAIT_M ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S)) 606 #define APB_SARADC_TSENS_XPD_WAIT_V 0xFFF 607 #define APB_SARADC_TSENS_XPD_WAIT_S 0 608 609 #define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x060) 610 /* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */ 611 /*description: */ 612 #define APB_SARADC_CALI_CFG 0x0001FFFF 613 #define APB_SARADC_CALI_CFG_M ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S)) 614 #define APB_SARADC_CALI_CFG_V 0x1FFFF 615 #define APB_SARADC_CALI_CFG_S 0 616 617 #define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) 618 /* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02007171 ; */ 619 /*description: */ 620 #define APB_SARADC_DATE 0xFFFFFFFF 621 #define APB_SARADC_DATE_M ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S)) 622 #define APB_SARADC_DATE_V 0xFFFFFFFF 623 #define APB_SARADC_DATE_S 0 624 625 #ifdef __cplusplus 626 } 627 #endif 628 629 630 631 #endif /*_SOC_APB_SARADC_REG_H_ */ 632
