1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 // HAL for SPI Flash (non-IRAM part)
8 // The IRAM part is in spi_flash_hal_iram.c, spi_flash_hal_gpspi.c, spi_flash_hal_common.inc.
9
10 #include <zephyr/sys/util.h>
11 #include <stdlib.h>
12 #include <string.h>
13 #include <math.h>
14 #include "soc/soc_caps.h"
15 #include "hal/spi_flash_hal.h"
16 #include "hal/assert.h"
17 #include "hal/log.h"
18 #include "hal/spi_flash_types.h"
19
20 #define APB_CYCLE_NS (1000*1000*1000LL/APB_CLK_FREQ)
21
22 static const char *TAG = "flash_hal";
23
get_flash_clock_divider(const spi_flash_hal_config_t * cfg)24 static uint32_t get_flash_clock_divider(const spi_flash_hal_config_t *cfg)
25 {
26 int clk_source = cfg->clock_src_freq;
27 // On ESP32, ESP32-S2, ESP32-C3, we allow specific frequency 26.666MHz
28 // If user passes freq_mhz like 26 or 27, it's allowed to use integer divider 3.
29 // However on other chips or on other frequency, we only allow user pass frequency which
30 // can be integer divided. If no, the following strategy is round up the division and
31 // round down flash frequency to keep it safe.
32 int best_div = 0;
33 if (clk_source < cfg->freq_mhz) {
34 HAL_LOGE(TAG, "Target frequency %dMHz higher than supported.", cfg->freq_mhz);
35 abort();
36 }
37 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
38 if (cfg->freq_mhz == 26 || cfg->freq_mhz == 27) {
39 best_div = 3;
40 } else
41 #endif
42 {
43 best_div = (int)DIV_ROUND_UP((double)clk_source, (double)cfg->freq_mhz);
44 if ((cfg->clock_src_freq % cfg->freq_mhz) != 0) {
45 HAL_LOGW(TAG, "Flash clock frequency round down to %d", (int)((double)clk_source / (double)best_div));
46 }
47 }
48
49 return best_div;
50 }
51
spi_flash_cal_clock(const spi_flash_hal_config_t * cfg)52 static uint32_t spi_flash_cal_clock(const spi_flash_hal_config_t *cfg)
53 {
54 uint32_t div_parameter = spi_flash_ll_calculate_clock_reg(cfg->host_id, get_flash_clock_divider(cfg));
55 return div_parameter;
56 }
57
get_dummy_n(bool gpio_is_used,int input_delay_ns,int eff_clk)58 static inline int get_dummy_n(bool gpio_is_used, int input_delay_ns, int eff_clk)
59 {
60 const int apbclk_kHz = APB_CLK_FREQ / 1000;
61 //calculate how many apb clocks a period has
62 const int apbclk_n = APB_CLK_FREQ / eff_clk;
63 const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0;
64
65 //calculate how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off.
66 int apb_period_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000;
67 if (apb_period_n < 0) {
68 apb_period_n = 0;
69 }
70
71 return apb_period_n / apbclk_n;
72 }
73
74 #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
extra_dummy_under_timing_tuning(const spi_flash_hal_config_t * cfg)75 static inline int extra_dummy_under_timing_tuning(const spi_flash_hal_config_t *cfg)
76 {
77 bool main_flash = (cfg->host_id == SPI1_HOST && cfg->cs_num == 0);
78 int extra_dummy = 0;
79 if (main_flash) {
80 /**
81 * For Octal Flash, the dummy is `usr_dummy` + `extra_dummy`, they are in two different regs, we don't touch `extra_dummy` here, so set extra_dummy 0.
82 * Instead, for both Quad and Octal Flash, we use `usr_dummy` and set the whole dummy length (usr_dummy + extra_dummy) to this register.
83 */
84 extra_dummy = cfg->extra_dummy;
85 } else {
86 // TODO: for other flash chips, dummy get logic implement here. Currently, still calculate extra dummy by itself.
87 abort();
88 }
89
90 return extra_dummy;
91 }
92 #endif //SOC_SPI_MEM_SUPPORT_TIME_TUNING
93
spi_flash_hal_init(spi_flash_hal_context_t * data_out,const spi_flash_hal_config_t * cfg)94 esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_hal_config_t *cfg)
95 {
96 if (cfg->cs_num >= SOC_SPI_PERIPH_CS_NUM(cfg->host_id)) {
97 return ESP_ERR_INVALID_ARG;
98 }
99
100 *data_out = (spi_flash_hal_context_t) {
101 .inst = data_out->inst, // Keeps the function pointer table
102 .spi = spi_flash_ll_get_hw(cfg->host_id),
103 .cs_num = cfg->cs_num,
104 .cs_hold = cfg->cs_hold,
105 .cs_setup = cfg->cs_setup,
106 .base_io_mode = cfg->default_io_mode,
107 };
108 #if SOC_SPI_MEM_SUPPORT_TIME_TUNING
109 if (cfg->using_timing_tuning) {
110 data_out->extra_dummy = extra_dummy_under_timing_tuning(cfg);
111 data_out->clock_conf = cfg->clock_config;
112 } else
113 #endif // SOC_SPI_MEM_SUPPORT_TIME_TUNING
114 {
115 data_out->extra_dummy = get_dummy_n(!cfg->iomux, cfg->input_delay_ns, APB_CLK_FREQ/get_flash_clock_divider(cfg));
116 data_out->clock_conf = (spi_flash_ll_clock_reg_t)spi_flash_cal_clock(cfg);
117 }
118
119
120 if (cfg->auto_sus_en) {
121 data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND;
122 data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME;
123 }
124
125 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
126 if (cfg->octal_mode_en) {
127 data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_OCTAL_MODE;
128 }
129
130 if (cfg->default_io_mode == SPI_FLASH_OPI_DTR) {
131 data_out->slicer_flags |= SPI_FLASH_HOST_CONTEXT_SLICER_FLAG_DTR;
132 }
133 #endif
134
135 return ESP_OK;
136 }
137
spi_flash_hal_supports_direct_write(spi_flash_host_inst_t * host,const void * p)138 bool spi_flash_hal_supports_direct_write(spi_flash_host_inst_t *host, const void *p)
139 {
140 (void)p;
141 bool direct_write = (((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI1_HOST));
142 return direct_write;
143 }
144
145
spi_flash_hal_supports_direct_read(spi_flash_host_inst_t * host,const void * p)146 bool spi_flash_hal_supports_direct_read(spi_flash_host_inst_t *host, const void *p)
147 {
148 (void)p;
149 //currently the host doesn't support to read through dma, no word-aligned requirements
150 bool direct_read = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI1_HOST));
151 return direct_read;
152 }
153
