1 // Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_APB_CTRL_REG_H_ 15 #define _SOC_APB_CTRL_REG_H_ 16 17 18 #include "soc.h" 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 #define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) 24 /* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ 25 /*description: .*/ 26 #define APB_CTRL_RST_TICK_CNT (BIT(12)) 27 #define APB_CTRL_RST_TICK_CNT_M (BIT(12)) 28 #define APB_CTRL_RST_TICK_CNT_V 0x1 29 #define APB_CTRL_RST_TICK_CNT_S 12 30 /* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 31 /*description: .*/ 32 #define APB_CTRL_CLK_EN (BIT(11)) 33 #define APB_CTRL_CLK_EN_M (BIT(11)) 34 #define APB_CTRL_CLK_EN_V 0x1 35 #define APB_CTRL_CLK_EN_S 11 36 /* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 37 /*description: .*/ 38 #define APB_CTRL_CLK_320M_EN (BIT(10)) 39 #define APB_CTRL_CLK_320M_EN_M (BIT(10)) 40 #define APB_CTRL_CLK_320M_EN_V 0x1 41 #define APB_CTRL_CLK_320M_EN_S 10 42 /* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ 43 /*description: .*/ 44 #define APB_CTRL_PRE_DIV_CNT 0x000003FF 45 #define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S)) 46 #define APB_CTRL_PRE_DIV_CNT_V 0x3FF 47 #define APB_CTRL_PRE_DIV_CNT_S 0 48 49 #define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) 50 /* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ 51 /*description: .*/ 52 #define APB_CTRL_TICK_ENABLE (BIT(16)) 53 #define APB_CTRL_TICK_ENABLE_M (BIT(16)) 54 #define APB_CTRL_TICK_ENABLE_V 0x1 55 #define APB_CTRL_TICK_ENABLE_S 16 56 /* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ 57 /*description: .*/ 58 #define APB_CTRL_CK8M_TICK_NUM 0x000000FF 59 #define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S)) 60 #define APB_CTRL_CK8M_TICK_NUM_V 0xFF 61 #define APB_CTRL_CK8M_TICK_NUM_S 8 62 /* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ 63 /*description: .*/ 64 #define APB_CTRL_XTAL_TICK_NUM 0x000000FF 65 #define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S)) 66 #define APB_CTRL_XTAL_TICK_NUM_V 0xFF 67 #define APB_CTRL_XTAL_TICK_NUM_S 0 68 69 #define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x8) 70 /* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 71 /*description: .*/ 72 #define APB_CTRL_CLK_XTAL_OEN (BIT(10)) 73 #define APB_CTRL_CLK_XTAL_OEN_M (BIT(10)) 74 #define APB_CTRL_CLK_XTAL_OEN_V 0x1 75 #define APB_CTRL_CLK_XTAL_OEN_S 10 76 /* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 77 /*description: .*/ 78 #define APB_CTRL_CLK40X_BB_OEN (BIT(9)) 79 #define APB_CTRL_CLK40X_BB_OEN_M (BIT(9)) 80 #define APB_CTRL_CLK40X_BB_OEN_V 0x1 81 #define APB_CTRL_CLK40X_BB_OEN_S 9 82 /* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ 83 /*description: .*/ 84 #define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8)) 85 #define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8)) 86 #define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1 87 #define APB_CTRL_CLK_DAC_CPU_OEN_S 8 88 /* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ 89 /*description: .*/ 90 #define APB_CTRL_CLK_ADC_INF_OEN (BIT(7)) 91 #define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7)) 92 #define APB_CTRL_CLK_ADC_INF_OEN_V 0x1 93 #define APB_CTRL_CLK_ADC_INF_OEN_S 7 94 /* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 95 /*description: .*/ 96 #define APB_CTRL_CLK_320M_OEN (BIT(6)) 97 #define APB_CTRL_CLK_320M_OEN_M (BIT(6)) 98 #define APB_CTRL_CLK_320M_OEN_V 0x1 99 #define APB_CTRL_CLK_320M_OEN_S 6 100 /* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 101 /*description: .*/ 102 #define APB_CTRL_CLK160_OEN (BIT(5)) 103 #define APB_CTRL_CLK160_OEN_M (BIT(5)) 104 #define APB_CTRL_CLK160_OEN_V 0x1 105 #define APB_CTRL_CLK160_OEN_S 5 106 /* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ 107 /*description: .*/ 108 #define APB_CTRL_CLK80_OEN (BIT(4)) 109 #define APB_CTRL_CLK80_OEN_M (BIT(4)) 110 #define APB_CTRL_CLK80_OEN_V 0x1 111 #define APB_CTRL_CLK80_OEN_S 4 112 /* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 113 /*description: .*/ 114 #define APB_CTRL_CLK_BB_OEN (BIT(3)) 115 #define APB_CTRL_CLK_BB_OEN_M (BIT(3)) 116 #define APB_CTRL_CLK_BB_OEN_V 0x1 117 #define APB_CTRL_CLK_BB_OEN_S 3 118 /* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 119 /*description: .*/ 120 #define APB_CTRL_CLK44_OEN (BIT(2)) 121 #define APB_CTRL_CLK44_OEN_M (BIT(2)) 122 #define APB_CTRL_CLK44_OEN_V 0x1 123 #define APB_CTRL_CLK44_OEN_S 2 124 /* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 125 /*description: .*/ 126 #define APB_CTRL_CLK22_OEN (BIT(1)) 127 #define APB_CTRL_CLK22_OEN_M (BIT(1)) 128 #define APB_CTRL_CLK22_OEN_V 0x1 129 #define APB_CTRL_CLK22_OEN_S 1 130 /* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 131 /*description: .*/ 132 #define APB_CTRL_CLK20_OEN (BIT(0)) 133 #define APB_CTRL_CLK20_OEN_M (BIT(0)) 134 #define APB_CTRL_CLK20_OEN_V 0x1 135 #define APB_CTRL_CLK20_OEN_S 0 136 137 #define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0xC) 138 /* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 139 /*description: .*/ 140 #define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF 141 #define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S)) 142 #define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF 143 #define APB_CTRL_WIFI_BB_CFG_S 0 144 145 #define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x10) 146 /* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 147 /*description: .*/ 148 #define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF 149 #define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S)) 150 #define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF 151 #define APB_CTRL_WIFI_BB_CFG_2_S 0 152 153 #define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x14) 154 /* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 155 /*description: .*/ 156 #define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF 157 #define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S)) 158 #define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF 159 #define APB_CTRL_WIFI_CLK_EN_S 0 160 161 #define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x18) 162 /* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 163 /*description: .*/ 164 #define APB_CTRL_WIFI_RST 0xFFFFFFFF 165 #define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S)) 166 #define APB_CTRL_WIFI_RST_V 0xFFFFFFFF 167 #define APB_CTRL_WIFI_RST_S 0 168 169 #define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x1C) 170 /* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 171 /*description: .*/ 172 #define APB_CTRL_PERI_IO_SWAP 0x000000FF 173 #define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S)) 174 #define APB_CTRL_PERI_IO_SWAP_V 0xFF 175 #define APB_CTRL_PERI_IO_SWAP_S 0 176 177 #define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x20) 178 /* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 179 /*description: .*/ 180 #define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0)) 181 #define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0)) 182 #define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1 183 #define APB_CTRL_EXT_MEM_PMS_LOCK_S 0 184 185 #define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_APB_CTRL_BASE + 0x24) 186 /* APB_CTRL_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 187 /*description: Set 1 to bypass cache writeback request to external memory so that spi will not 188 check its attribute..*/ 189 #define APB_CTRL_WRITEBACK_BYPASS (BIT(0)) 190 #define APB_CTRL_WRITEBACK_BYPASS_M (BIT(0)) 191 #define APB_CTRL_WRITEBACK_BYPASS_V 0x1 192 #define APB_CTRL_WRITEBACK_BYPASS_S 0 193 194 #define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x28) 195 /* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 196 /*description: .*/ 197 #define APB_CTRL_FLASH_ACE0_ATTR 0x000001FF 198 #define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S)) 199 #define APB_CTRL_FLASH_ACE0_ATTR_V 0x1FF 200 #define APB_CTRL_FLASH_ACE0_ATTR_S 0 201 202 #define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x2C) 203 /* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 204 /*description: .*/ 205 #define APB_CTRL_FLASH_ACE1_ATTR 0x000001FF 206 #define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S)) 207 #define APB_CTRL_FLASH_ACE1_ATTR_V 0x1FF 208 #define APB_CTRL_FLASH_ACE1_ATTR_S 0 209 210 #define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x30) 211 /* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 212 /*description: .*/ 213 #define APB_CTRL_FLASH_ACE2_ATTR 0x000001FF 214 #define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S)) 215 #define APB_CTRL_FLASH_ACE2_ATTR_V 0x1FF 216 #define APB_CTRL_FLASH_ACE2_ATTR_S 0 217 218 #define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x34) 219 /* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 220 /*description: .*/ 221 #define APB_CTRL_FLASH_ACE3_ATTR 0x000001FF 222 #define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S)) 223 #define APB_CTRL_FLASH_ACE3_ATTR_V 0x1FF 224 #define APB_CTRL_FLASH_ACE3_ATTR_S 0 225 226 #define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x38) 227 /* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 228 /*description: .*/ 229 #define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF 230 #define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S)) 231 #define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF 232 #define APB_CTRL_FLASH_ACE0_ADDR_S_S 0 233 234 #define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x3C) 235 /* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ 236 /*description: .*/ 237 #define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF 238 #define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S)) 239 #define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF 240 #define APB_CTRL_FLASH_ACE1_ADDR_S_S 0 241 242 #define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x40) 243 /* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ 244 /*description: .*/ 245 #define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF 246 #define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S)) 247 #define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF 248 #define APB_CTRL_FLASH_ACE2_ADDR_S_S 0 249 250 #define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x44) 251 /* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ 252 /*description: .*/ 253 #define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF 254 #define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S)) 255 #define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF 256 #define APB_CTRL_FLASH_ACE3_ADDR_S_S 0 257 258 #define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x48) 259 /* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 260 /*description: .*/ 261 #define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF 262 #define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S)) 263 #define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF 264 #define APB_CTRL_FLASH_ACE0_SIZE_S 0 265 266 #define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x4C) 267 /* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 268 /*description: .*/ 269 #define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF 270 #define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S)) 271 #define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF 272 #define APB_CTRL_FLASH_ACE1_SIZE_S 0 273 274 #define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x50) 275 /* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 276 /*description: .*/ 277 #define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF 278 #define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S)) 279 #define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF 280 #define APB_CTRL_FLASH_ACE2_SIZE_S 0 281 282 #define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x54) 283 /* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 284 /*description: .*/ 285 #define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF 286 #define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S)) 287 #define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF 288 #define APB_CTRL_FLASH_ACE3_SIZE_S 0 289 290 #define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x58) 291 /* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 292 /*description: .*/ 293 #define APB_CTRL_SRAM_ACE0_ATTR 0x000001FF 294 #define APB_CTRL_SRAM_ACE0_ATTR_M ((APB_CTRL_SRAM_ACE0_ATTR_V)<<(APB_CTRL_SRAM_ACE0_ATTR_S)) 295 #define APB_CTRL_SRAM_ACE0_ATTR_V 0x1FF 296 #define APB_CTRL_SRAM_ACE0_ATTR_S 0 297 298 #define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x5C) 299 /* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 300 /*description: .*/ 301 #define APB_CTRL_SRAM_ACE1_ATTR 0x000001FF 302 #define APB_CTRL_SRAM_ACE1_ATTR_M ((APB_CTRL_SRAM_ACE1_ATTR_V)<<(APB_CTRL_SRAM_ACE1_ATTR_S)) 303 #define APB_CTRL_SRAM_ACE1_ATTR_V 0x1FF 304 #define APB_CTRL_SRAM_ACE1_ATTR_S 0 305 306 #define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x60) 307 /* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 308 /*description: .*/ 309 #define APB_CTRL_SRAM_ACE2_ATTR 0x000001FF 310 #define APB_CTRL_SRAM_ACE2_ATTR_M ((APB_CTRL_SRAM_ACE2_ATTR_V)<<(APB_CTRL_SRAM_ACE2_ATTR_S)) 311 #define APB_CTRL_SRAM_ACE2_ATTR_V 0x1FF 312 #define APB_CTRL_SRAM_ACE2_ATTR_S 0 313 314 #define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x64) 315 /* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 316 /*description: .*/ 317 #define APB_CTRL_SRAM_ACE3_ATTR 0x000001FF 318 #define APB_CTRL_SRAM_ACE3_ATTR_M ((APB_CTRL_SRAM_ACE3_ATTR_V)<<(APB_CTRL_SRAM_ACE3_ATTR_S)) 319 #define APB_CTRL_SRAM_ACE3_ATTR_V 0x1FF 320 #define APB_CTRL_SRAM_ACE3_ATTR_S 0 321 322 #define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x68) 323 /* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 324 /*description: .*/ 325 #define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF 326 #define APB_CTRL_SRAM_ACE0_ADDR_S_M ((APB_CTRL_SRAM_ACE0_ADDR_S_V)<<(APB_CTRL_SRAM_ACE0_ADDR_S_S)) 327 #define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF 328 #define APB_CTRL_SRAM_ACE0_ADDR_S_S 0 329 330 #define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x6C) 331 /* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ 332 /*description: .*/ 333 #define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF 334 #define APB_CTRL_SRAM_ACE1_ADDR_S_M ((APB_CTRL_SRAM_ACE1_ADDR_S_V)<<(APB_CTRL_SRAM_ACE1_ADDR_S_S)) 335 #define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF 336 #define APB_CTRL_SRAM_ACE1_ADDR_S_S 0 337 338 #define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x70) 339 /* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ 340 /*description: .*/ 341 #define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF 342 #define APB_CTRL_SRAM_ACE2_ADDR_S_M ((APB_CTRL_SRAM_ACE2_ADDR_S_V)<<(APB_CTRL_SRAM_ACE2_ADDR_S_S)) 343 #define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF 344 #define APB_CTRL_SRAM_ACE2_ADDR_S_S 0 345 346 #define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x74) 347 /* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ 348 /*description: .*/ 349 #define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF 350 #define APB_CTRL_SRAM_ACE3_ADDR_S_M ((APB_CTRL_SRAM_ACE3_ADDR_S_V)<<(APB_CTRL_SRAM_ACE3_ADDR_S_S)) 351 #define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF 352 #define APB_CTRL_SRAM_ACE3_ADDR_S_S 0 353 354 #define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x78) 355 /* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 356 /*description: .*/ 357 #define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF 358 #define APB_CTRL_SRAM_ACE0_SIZE_M ((APB_CTRL_SRAM_ACE0_SIZE_V)<<(APB_CTRL_SRAM_ACE0_SIZE_S)) 359 #define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF 360 #define APB_CTRL_SRAM_ACE0_SIZE_S 0 361 362 #define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x7C) 363 /* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 364 /*description: .*/ 365 #define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF 366 #define APB_CTRL_SRAM_ACE1_SIZE_M ((APB_CTRL_SRAM_ACE1_SIZE_V)<<(APB_CTRL_SRAM_ACE1_SIZE_S)) 367 #define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF 368 #define APB_CTRL_SRAM_ACE1_SIZE_S 0 369 370 #define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x80) 371 /* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 372 /*description: .*/ 373 #define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF 374 #define APB_CTRL_SRAM_ACE2_SIZE_M ((APB_CTRL_SRAM_ACE2_SIZE_V)<<(APB_CTRL_SRAM_ACE2_SIZE_S)) 375 #define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF 376 #define APB_CTRL_SRAM_ACE2_SIZE_S 0 377 378 #define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x84) 379 /* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 380 /*description: .*/ 381 #define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF 382 #define APB_CTRL_SRAM_ACE3_SIZE_M ((APB_CTRL_SRAM_ACE3_SIZE_V)<<(APB_CTRL_SRAM_ACE3_SIZE_S)) 383 #define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF 384 #define APB_CTRL_SRAM_ACE3_SIZE_S 0 385 386 #define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x88) 387 /* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ 388 /*description: .*/ 389 #define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F 390 #define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S)) 391 #define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F 392 #define APB_CTRL_SPI_MEM_REJECT_CDE_S 2 393 /* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 394 /*description: .*/ 395 #define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1)) 396 #define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1)) 397 #define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1 398 #define APB_CTRL_SPI_MEM_REJECT_CLR_S 1 399 /* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ 400 /*description: .*/ 401 #define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0)) 402 #define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0)) 403 #define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1 404 #define APB_CTRL_SPI_MEM_REJECT_INT_S 0 405 406 #define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x8C) 407 /* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 408 /*description: .*/ 409 #define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF 410 #define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S)) 411 #define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF 412 #define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0 413 414 #define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x90) 415 /* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 416 /*description: .*/ 417 #define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0)) 418 #define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0)) 419 #define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1 420 #define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0 421 422 #define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x94) 423 /* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 424 /*description: .*/ 425 #define APB_CTRL_REDCY_ANDOR (BIT(31)) 426 #define APB_CTRL_REDCY_ANDOR_M (BIT(31)) 427 #define APB_CTRL_REDCY_ANDOR_V 0x1 428 #define APB_CTRL_REDCY_ANDOR_S 31 429 /* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 430 /*description: .*/ 431 #define APB_CTRL_REDCY_SIG0 0x7FFFFFFF 432 #define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S)) 433 #define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF 434 #define APB_CTRL_REDCY_SIG0_S 0 435 436 #define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x98) 437 /* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 438 /*description: .*/ 439 #define APB_CTRL_REDCY_NANDOR (BIT(31)) 440 #define APB_CTRL_REDCY_NANDOR_M (BIT(31)) 441 #define APB_CTRL_REDCY_NANDOR_V 0x1 442 #define APB_CTRL_REDCY_NANDOR_S 31 443 /* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 444 /*description: .*/ 445 #define APB_CTRL_REDCY_SIG1 0x7FFFFFFF 446 #define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S)) 447 #define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF 448 #define APB_CTRL_REDCY_SIG1_S 0 449 450 #define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x9C) 451 /* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 452 /*description: .*/ 453 #define APB_CTRL_FREQ_MEM_FORCE_PD (BIT(7)) 454 #define APB_CTRL_FREQ_MEM_FORCE_PD_M (BIT(7)) 455 #define APB_CTRL_FREQ_MEM_FORCE_PD_V 0x1 456 #define APB_CTRL_FREQ_MEM_FORCE_PD_S 7 457 /* APB_CTRL_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */ 458 /*description: .*/ 459 #define APB_CTRL_FREQ_MEM_FORCE_PU (BIT(6)) 460 #define APB_CTRL_FREQ_MEM_FORCE_PU_M (BIT(6)) 461 #define APB_CTRL_FREQ_MEM_FORCE_PU_V 0x1 462 #define APB_CTRL_FREQ_MEM_FORCE_PU_S 6 463 /* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 464 /*description: .*/ 465 #define APB_CTRL_DC_MEM_FORCE_PD (BIT(5)) 466 #define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5)) 467 #define APB_CTRL_DC_MEM_FORCE_PD_V 0x1 468 #define APB_CTRL_DC_MEM_FORCE_PD_S 5 469 /* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 470 /*description: .*/ 471 #define APB_CTRL_DC_MEM_FORCE_PU (BIT(4)) 472 #define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4)) 473 #define APB_CTRL_DC_MEM_FORCE_PU_V 0x1 474 #define APB_CTRL_DC_MEM_FORCE_PU_S 4 475 /* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 476 /*description: .*/ 477 #define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3)) 478 #define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3)) 479 #define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1 480 #define APB_CTRL_PBUS_MEM_FORCE_PD_S 3 481 /* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 482 /*description: .*/ 483 #define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2)) 484 #define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2)) 485 #define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1 486 #define APB_CTRL_PBUS_MEM_FORCE_PU_S 2 487 /* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 488 /*description: .*/ 489 #define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1)) 490 #define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1)) 491 #define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1 492 #define APB_CTRL_AGC_MEM_FORCE_PD_S 1 493 /* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ 494 /*description: .*/ 495 #define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0)) 496 #define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0)) 497 #define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1 498 #define APB_CTRL_AGC_MEM_FORCE_PU_S 0 499 500 #define APB_CTRL_SPI_MEM_ECC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xA0) 501 /* APB_CTRL_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */ 502 /*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 503 1024 bytes. 3: 2048 bytes..*/ 504 #define APB_CTRL_SRAM_PAGE_SIZE 0x00000003 505 #define APB_CTRL_SRAM_PAGE_SIZE_M ((APB_CTRL_SRAM_PAGE_SIZE_V)<<(APB_CTRL_SRAM_PAGE_SIZE_S)) 506 #define APB_CTRL_SRAM_PAGE_SIZE_V 0x3 507 #define APB_CTRL_SRAM_PAGE_SIZE_S 20 508 /* APB_CTRL_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ 509 /*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by 510 tes. 3: 2048 bytes..*/ 511 #define APB_CTRL_FLASH_PAGE_SIZE 0x00000003 512 #define APB_CTRL_FLASH_PAGE_SIZE_M ((APB_CTRL_FLASH_PAGE_SIZE_V)<<(APB_CTRL_FLASH_PAGE_SIZE_S)) 513 #define APB_CTRL_FLASH_PAGE_SIZE_V 0x3 514 #define APB_CTRL_FLASH_PAGE_SIZE_S 18 515 516 #define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0xA8) 517 /* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */ 518 /*description: .*/ 519 #define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x000007FF 520 #define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S)) 521 #define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0x7FF 522 #define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 3 523 /* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ 524 /*description: .*/ 525 #define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000007 526 #define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S)) 527 #define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x7 528 #define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0 529 530 #define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_APB_CTRL_BASE + 0xAC) 531 /* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */ 532 /*description: .*/ 533 #define APB_CTRL_SRAM_POWER_DOWN 0x000007FF 534 #define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S)) 535 #define APB_CTRL_SRAM_POWER_DOWN_V 0x7FF 536 #define APB_CTRL_SRAM_POWER_DOWN_S 3 537 /* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ 538 /*description: .*/ 539 #define APB_CTRL_ROM_POWER_DOWN 0x00000007 540 #define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S)) 541 #define APB_CTRL_ROM_POWER_DOWN_V 0x7 542 #define APB_CTRL_ROM_POWER_DOWN_S 0 543 544 #define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0xB0) 545 /* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */ 546 /*description: .*/ 547 #define APB_CTRL_SRAM_POWER_UP 0x000007FF 548 #define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S)) 549 #define APB_CTRL_SRAM_POWER_UP_V 0x7FF 550 #define APB_CTRL_SRAM_POWER_UP_S 3 551 /* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ 552 /*description: .*/ 553 #define APB_CTRL_ROM_POWER_UP 0x00000007 554 #define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S)) 555 #define APB_CTRL_ROM_POWER_UP_V 0x7 556 #define APB_CTRL_ROM_POWER_UP_S 0 557 558 #define APB_CTRL_RETENTION_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xB4) 559 /* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ 560 /*description: .*/ 561 #define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27)) 562 #define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27)) 563 #define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1 564 #define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27 565 /* APB_CTRL_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ 566 /*description: .*/ 567 #define APB_CTRL_RETENTION_CPU_LINK_ADDR 0x07FFFFFF 568 #define APB_CTRL_RETENTION_CPU_LINK_ADDR_M ((APB_CTRL_RETENTION_CPU_LINK_ADDR_V)<<(APB_CTRL_RETENTION_CPU_LINK_ADDR_S)) 569 #define APB_CTRL_RETENTION_CPU_LINK_ADDR_V 0x7FFFFFF 570 #define APB_CTRL_RETENTION_CPU_LINK_ADDR_S 0 571 572 #define APB_CTRL_RETENTION_CTRL1_REG (DR_REG_APB_CTRL_BASE + 0xB8) 573 /* APB_CTRL_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ 574 /*description: .*/ 575 #define APB_CTRL_RETENTION_TAG_LINK_ADDR 0x07FFFFFF 576 #define APB_CTRL_RETENTION_TAG_LINK_ADDR_M ((APB_CTRL_RETENTION_TAG_LINK_ADDR_V)<<(APB_CTRL_RETENTION_TAG_LINK_ADDR_S)) 577 #define APB_CTRL_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF 578 #define APB_CTRL_RETENTION_TAG_LINK_ADDR_S 0 579 580 #define APB_CTRL_RETENTION_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0xBC) 581 /* APB_CTRL_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 582 /*description: .*/ 583 #define APB_CTRL_RET_ICACHE_ENABLE (BIT(31)) 584 #define APB_CTRL_RET_ICACHE_ENABLE_M (BIT(31)) 585 #define APB_CTRL_RET_ICACHE_ENABLE_V 0x1 586 #define APB_CTRL_RET_ICACHE_ENABLE_S 31 587 /* APB_CTRL_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */ 588 /*description: .*/ 589 #define APB_CTRL_RET_ICACHE_START_POINT 0x000000FF 590 #define APB_CTRL_RET_ICACHE_START_POINT_M ((APB_CTRL_RET_ICACHE_START_POINT_V)<<(APB_CTRL_RET_ICACHE_START_POINT_S)) 591 #define APB_CTRL_RET_ICACHE_START_POINT_V 0xFF 592 #define APB_CTRL_RET_ICACHE_START_POINT_S 22 593 /* APB_CTRL_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */ 594 /*description: .*/ 595 #define APB_CTRL_RET_ICACHE_VLD_SIZE 0x000000FF 596 #define APB_CTRL_RET_ICACHE_VLD_SIZE_M ((APB_CTRL_RET_ICACHE_VLD_SIZE_V)<<(APB_CTRL_RET_ICACHE_VLD_SIZE_S)) 597 #define APB_CTRL_RET_ICACHE_VLD_SIZE_V 0xFF 598 #define APB_CTRL_RET_ICACHE_VLD_SIZE_S 13 599 /* APB_CTRL_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */ 600 /*description: .*/ 601 #define APB_CTRL_RET_ICACHE_SIZE 0x000000FF 602 #define APB_CTRL_RET_ICACHE_SIZE_M ((APB_CTRL_RET_ICACHE_SIZE_V)<<(APB_CTRL_RET_ICACHE_SIZE_S)) 603 #define APB_CTRL_RET_ICACHE_SIZE_V 0xFF 604 #define APB_CTRL_RET_ICACHE_SIZE_S 4 605 606 #define APB_CTRL_RETENTION_CTRL3_REG (DR_REG_APB_CTRL_BASE + 0xC0) 607 /* APB_CTRL_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 608 /*description: .*/ 609 #define APB_CTRL_RET_DCACHE_ENABLE (BIT(31)) 610 #define APB_CTRL_RET_DCACHE_ENABLE_M (BIT(31)) 611 #define APB_CTRL_RET_DCACHE_ENABLE_V 0x1 612 #define APB_CTRL_RET_DCACHE_ENABLE_S 31 613 /* APB_CTRL_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */ 614 /*description: .*/ 615 #define APB_CTRL_RET_DCACHE_START_POINT 0x000001FF 616 #define APB_CTRL_RET_DCACHE_START_POINT_M ((APB_CTRL_RET_DCACHE_START_POINT_V)<<(APB_CTRL_RET_DCACHE_START_POINT_S)) 617 #define APB_CTRL_RET_DCACHE_START_POINT_V 0x1FF 618 #define APB_CTRL_RET_DCACHE_START_POINT_S 22 619 /* APB_CTRL_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */ 620 /*description: .*/ 621 #define APB_CTRL_RET_DCACHE_VLD_SIZE 0x000001FF 622 #define APB_CTRL_RET_DCACHE_VLD_SIZE_M ((APB_CTRL_RET_DCACHE_VLD_SIZE_V)<<(APB_CTRL_RET_DCACHE_VLD_SIZE_S)) 623 #define APB_CTRL_RET_DCACHE_VLD_SIZE_V 0x1FF 624 #define APB_CTRL_RET_DCACHE_VLD_SIZE_S 13 625 /* APB_CTRL_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */ 626 /*description: .*/ 627 #define APB_CTRL_RET_DCACHE_SIZE 0x000001FF 628 #define APB_CTRL_RET_DCACHE_SIZE_M ((APB_CTRL_RET_DCACHE_SIZE_V)<<(APB_CTRL_RET_DCACHE_SIZE_S)) 629 #define APB_CTRL_RET_DCACHE_SIZE_V 0x1FF 630 #define APB_CTRL_RET_DCACHE_SIZE_S 4 631 632 #define APB_CTRL_RETENTION_CTRL4_REG (DR_REG_APB_CTRL_BASE + 0xC4) 633 /* APB_CTRL_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */ 634 /*description: .*/ 635 #define APB_CTRL_RETENTION_INV_CFG 0xFFFFFFFF 636 #define APB_CTRL_RETENTION_INV_CFG_M ((APB_CTRL_RETENTION_INV_CFG_V)<<(APB_CTRL_RETENTION_INV_CFG_S)) 637 #define APB_CTRL_RETENTION_INV_CFG_V 0xFFFFFFFF 638 #define APB_CTRL_RETENTION_INV_CFG_S 0 639 640 #define APB_CTRL_RETENTION_CTRL5_REG (DR_REG_APB_CTRL_BASE + 0xC8) 641 /* APB_CTRL_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 642 /*description: .*/ 643 #define APB_CTRL_RETENTION_DISABLE (BIT(0)) 644 #define APB_CTRL_RETENTION_DISABLE_M (BIT(0)) 645 #define APB_CTRL_RETENTION_DISABLE_V 0x1 646 #define APB_CTRL_RETENTION_DISABLE_S 0 647 648 #define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC) 649 /* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */ 650 /*description: Version control.*/ 651 #define APB_CTRL_DATE 0xFFFFFFFF 652 #define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S)) 653 #define APB_CTRL_DATE_V 0xFFFFFFFF 654 #define APB_CTRL_DATE_S 0 655 656 657 #ifdef __cplusplus 658 } 659 #endif 660 661 662 663 #endif /*_SOC_APB_CTRL_REG_H_ */ 664
