1 /*
2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #pragma once
8
9 #include <stdbool.h>
10 #include "hal/adc_types.h"
11 #include "hal/misc.h"
12 #include "hal/assert.h"
13 #include "soc/adc_periph.h"
14 #include "soc/rtc_io_struct.h"
15 #include "soc/sens_struct.h"
16 #include "soc/sens_reg.h"
17 #include "soc/syscon_struct.h"
18 #include "soc/rtc_cntl_struct.h"
19 #include "soc/clk_tree_defs.h"
20
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24
25 #define ADC_LL_EVENT_ADC1_ONESHOT_DONE (1 << 0)
26 #define ADC_LL_EVENT_ADC2_ONESHOT_DONE (1 << 1)
27
28 /*---------------------------------------------------------------
29 Oneshot
30 ---------------------------------------------------------------*/
31 #define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
32 #define ADC_LL_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) (1)
33 #define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL (0)
34
35 /*---------------------------------------------------------------
36 DMA
37 ---------------------------------------------------------------*/
38 #define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (1)
39 #define ADC_LL_FSM_RSTB_WAIT_DEFAULT (8)
40 #define ADC_LL_FSM_START_WAIT_DEFAULT (ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT)
41 #define ADC_LL_FSM_STANDBY_WAIT_DEFAULT (100)
42 #define ADC_LL_SAMPLE_CYCLE_DEFAULT (2)
43 #define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT (16)
44
45 //On esp32, ADC can only be continuously triggered when `ADC_LL_DEFAULT_CONV_LIMIT_EN == 1`, `ADC_LL_DEFAULT_CONV_LIMIT_NUM != 0`
46 #define ADC_LL_DEFAULT_CONV_LIMIT_EN 1
47 #define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10
48
49 /*---------------------------------------------------------------
50 PWDET (Power Detect)
51 ---------------------------------------------------------------*/
52 #define ADC_LL_PWDET_CCT_DEFAULT (4)
53
54 typedef enum {
55 ADC_LL_CTRL_RTC = 0, ///< For ADC1 and ADC2. Select RTC controller.
56 ADC_LL_CTRL_ULP = 1, ///< For ADC1 and ADC2. Select ULP controller.
57 ADC_LL_CTRL_DIG = 2, ///< For ADC1 and ADC2. Select DIG controller.
58 ADC_LL_CTRL_PWDET = 3, ///< For ADC2. Select PWDET controller.
59 } adc_ll_controller_t;
60
61 /**
62 * @brief ADC digital controller (DMA mode) work mode.
63 *
64 * @note The conversion mode affects the sampling frequency:
65 * SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
66 * SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once.
67 * BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time.
68 * ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
69 */
70 typedef enum {
71 ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion
72 ADC_LL_DIGI_CONV_ONLY_ADC2 = 1, // Only use ADC2 for conversion
73 ADC_LL_DIGI_CONV_BOTH_UNIT = 2, // Use Both ADC1 and ADC2 for conversion simultaneously
74 ADC_LL_DIGI_CONV_ALTER_UNIT = 3 // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 .....
75 } adc_ll_digi_convert_mode_t;
76
77 //Need a unit test for bit_width
78 typedef struct {
79 union {
80 struct {
81 uint8_t atten: 2;
82 uint8_t bit_width: 2; //ADC resolution. 0: 9 bit; 1: 10 bit; 2: 11 bit; 3: 12 bit
83 uint8_t channel: 4;
84 };
85 uint8_t val;
86 };
87 } __attribute__((packed)) adc_ll_digi_pattern_table_t;
88
89 typedef enum {
90 ADC_HALL_CTRL_ULP = 0x0,/*!< Hall sensor controlled by ULP */
91 ADC_HALL_CTRL_RTC = 0x1 /*!< Hall sensor controlled by RTC */
92 } adc_ll_hall_controller_t ;
93
94 /*---------------------------------------------------------------
95 Digital controller setting
96 ---------------------------------------------------------------*/
97
98 /**
99 * Set adc fsm interval parameter for digital controller. These values are fixed for same platforms.
100 *
101 * @param rst_wait cycles between DIG ADC controller reset ADC sensor and start ADC sensor.
102 * @param start_wait Delay time after open xpd.
103 * @param standby_wait Delay time to close xpd.
104 */
adc_ll_digi_set_fsm_time(uint32_t rst_wait,uint32_t start_wait,uint32_t standby_wait)105 static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
106 {
107 // Internal FSM reset wait time
108 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, rstb_wait, rst_wait);
109 // Internal FSM start wait time
110 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, start_wait, start_wait);
111 // Internal FSM standby wait time
112 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, standby_wait, standby_wait);
113 }
114
115 /**
116 * Set adc sample cycle.
117 *
118 * @note Normally, please use default value.
119 * @param sample_cycle The number of ADC sampling cycles. Range: 1 ~ 7.
120 */
adc_ll_set_sample_cycle(uint32_t sample_cycle)121 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
122 {
123 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, sample_cycle, sample_cycle);
124 }
125
126 /**
127 * ADC module clock division factor setting. ADC clock divided from APB clock.
128 *
129 * @param div Division factor.
130 */
adc_ll_digi_set_clk_div(uint32_t div)131 static inline void adc_ll_digi_set_clk_div(uint32_t div)
132 {
133 /* ADC clock divided from APB clk, e.g. 80 / 2 = 40Mhz, */
134 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl, sar_clk_div, div);
135 }
136
137 /**
138 * Set adc max conversion number for digital controller.
139 * If the number of ADC conversion is equal to the maximum, the conversion is stopped.
140 *
141 * @param meas_num Max conversion number. Range: 0 ~ 255.
142 */
adc_ll_digi_set_convert_limit_num(uint32_t meas_num)143 static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
144 {
145 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl2, max_meas_num, meas_num);
146 }
147
148 /**
149 * Enable max conversion number detection for digital controller.
150 * If the number of ADC conversion is equal to the maximum, the conversion is stopped.
151 * @note On esp32, this should always be 1 to trigger the ADC continuously
152 *
153 * @param enable true: enable; false: disable
154 */
adc_ll_digi_convert_limit_enable(bool enable)155 static inline void adc_ll_digi_convert_limit_enable(bool enable)
156 {
157 SYSCON.saradc_ctrl2.meas_num_limit = enable;
158 }
159
160 /**
161 * Set adc conversion mode for digital controller.
162 *
163 * @note ESP32 only support ADC1 single mode.
164 * @note For `data_sar_sel` register:
165 * 1: [15] unit, [14:11] channel, [10:0] data, 11-bit-width at most. Only work under `ADC_LL_DIGI_CONV_BOTH_UNIT` or `ADC_LL_DIGI_CONV_ALTER_UNIT` mode.
166 * 0: [15:12] channel, [11:0] data, 12-bit-width at most. Only work under `ADC_LL_DIGI_CONV_ONLY_ADC1` or `ADC_LL_DIGI_CONV_ONLY_ADC2` mode
167 *
168 * @param mode Conversion mode select.
169 */
adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)170 static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
171 {
172 if (mode == ADC_LL_DIGI_CONV_ONLY_ADC1) {
173 SYSCON.saradc_ctrl.work_mode = 0;
174 SYSCON.saradc_ctrl.sar_sel = 0;
175 SYSCON.saradc_ctrl.data_sar_sel = 0;
176 } else if (mode == ADC_LL_DIGI_CONV_ONLY_ADC2) {
177 SYSCON.saradc_ctrl.work_mode = 0;
178 SYSCON.saradc_ctrl.sar_sel = 1;
179 SYSCON.saradc_ctrl.data_sar_sel = 0;
180 } else if (mode == ADC_LL_DIGI_CONV_BOTH_UNIT) {
181 SYSCON.saradc_ctrl.work_mode = 1;
182 SYSCON.saradc_ctrl.data_sar_sel = 1;
183 } else if (mode == ADC_LL_DIGI_CONV_ALTER_UNIT) {
184 SYSCON.saradc_ctrl.work_mode = 2;
185 SYSCON.saradc_ctrl.data_sar_sel = 1;
186 }
187 }
188
189 /**
190 * ADC module Digital output data invert or not.
191 *
192 * @prarm adc_n ADC unit.
193 */
adc_ll_digi_output_invert(adc_unit_t adc_n,bool inv_en)194 static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
195 {
196 if (adc_n == ADC_UNIT_1) {
197 SYSCON.saradc_ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
198 } else { // adc_n == ADC_UNIT_2
199 SYSCON.saradc_ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
200 }
201 }
202
203 /**
204 * Set I2S DMA data source for digital controller.
205 *
206 * @param src 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix
207 */
adc_ll_digi_set_data_source(bool src)208 static inline void adc_ll_digi_set_data_source(bool src)
209 {
210 SYSCON.saradc_ctrl.data_to_i2s = src;
211 }
212
213 /**
214 * Set pattern table length for digital controller.
215 * The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
216 * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
217 * pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself.
218 *
219 * @param adc_n ADC unit.
220 * @param patt_len Items range: 1 ~ 16.
221 */
adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n,uint32_t patt_len)222 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
223 {
224 if (adc_n == ADC_UNIT_1) {
225 SYSCON.saradc_ctrl.sar1_patt_len = patt_len - 1;
226 } else { // adc_n == ADC_UNIT_2
227 SYSCON.saradc_ctrl.sar2_patt_len = patt_len - 1;
228 }
229 }
230
231 /**
232 * Set pattern table lenth for digital controller.
233 * The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
234 * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
235 * pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself.
236 *
237 * @param adc_n ADC unit.
238 * @param pattern_index Items index. Range: 0 ~ 15.
239 * @param pattern Stored conversion rules, see ``adc_digi_pattern_table_t``.
240 */
adc_ll_digi_set_pattern_table(adc_unit_t adc_n,uint32_t pattern_index,adc_digi_pattern_config_t table)241 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
242 {
243 uint32_t tab;
244 uint8_t index = pattern_index / 4;
245 uint8_t offset = (pattern_index % 4) * 8;
246 adc_ll_digi_pattern_table_t pattern = {0};
247 uint8_t bit_width;
248
249 switch (table.bit_width) {
250 case 9:
251 bit_width = 0x0;
252 break;
253 case 10:
254 bit_width = 0x1;
255 break;
256 case 11:
257 bit_width = 0x2;
258 break;
259 case 12:
260 bit_width = 0x3;
261 break;
262 default:
263 bit_width = 0x3;
264 }
265 pattern.val = (table.atten & 0x3) | ((bit_width) << 2) | ((table.channel & 0xF) << 4);
266
267 if (table.unit == ADC_UNIT_1) {
268 tab = SYSCON.saradc_sar1_patt_tab[index]; // Read old register value
269 tab &= (~(0xFF000000 >> offset)); // clear old data
270 tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
271 SYSCON.saradc_sar1_patt_tab[index] = tab; // Write back
272 } else { // adc_n == ADC_UNIT_2
273 tab = SYSCON.saradc_sar2_patt_tab[index]; // Read old register value
274 tab &= (~(0xFF000000 >> offset)); // clear old data
275 tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
276 SYSCON.saradc_sar2_patt_tab[index] = tab; // Write back
277 }
278 }
279
280 /**
281 * Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
282 *
283 * @param adc_n ADC unit.
284 */
adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)285 static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
286 {
287 if (adc_n == ADC_UNIT_1) {
288 SYSCON.saradc_ctrl.sar1_patt_p_clear = 1;
289 SYSCON.saradc_ctrl.sar1_patt_p_clear = 0;
290 } else { // adc_n == ADC_UNIT_2
291 SYSCON.saradc_ctrl.sar2_patt_p_clear = 1;
292 SYSCON.saradc_ctrl.sar2_patt_p_clear = 0;
293 }
294 }
295
296 /**
297 * Disable clock for ADC digital controller.
298 * @note Not used for esp32
299 */
adc_ll_digi_controller_clk_disable(void)300 static inline void adc_ll_digi_controller_clk_disable(void)
301 {
302 //Leave here for compatibility
303 }
304
305 /*---------------------------------------------------------------
306 PWDET(Power detect) controller setting
307 ---------------------------------------------------------------*/
308 /**
309 * Set adc cct for PWDET controller.
310 *
311 * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
312 * @param cct Range: 0 ~ 7.
313 */
adc_ll_pwdet_set_cct(uint32_t cct)314 static inline void adc_ll_pwdet_set_cct(uint32_t cct)
315 {
316 /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
317 SENS.sar_start_force.sar2_pwdet_cct = cct;
318 }
319
320 /**
321 * Get adc cct for PWDET controller.
322 *
323 * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
324 * @return cct Range: 0 ~ 7.
325 */
adc_ll_pwdet_get_cct(void)326 static inline uint32_t adc_ll_pwdet_get_cct(void)
327 {
328 /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
329 return SENS.sar_start_force.sar2_pwdet_cct;
330 }
331
332 /*---------------------------------------------------------------
333 RTC controller setting
334 ---------------------------------------------------------------*/
335 /**
336 * ADC SAR clock division factor setting. ADC SAR clock divided from `RTC_FAST_CLK`.
337 *
338 * @param div Division factor.
339 */
adc_ll_set_sar_clk_div(adc_unit_t adc_n,uint32_t div)340 static inline void adc_ll_set_sar_clk_div(adc_unit_t adc_n, uint32_t div)
341 {
342 if (adc_n == ADC_UNIT_1) {
343 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div);
344 } else { // adc_n == ADC_UNIT_2
345 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div);
346 }
347 }
348
349 /**
350 * Set adc output data format for RTC controller.
351 *
352 * @param adc_n ADC unit.
353 * @param bits Output data bits width option
354 */
adc_oneshot_ll_set_output_bits(adc_unit_t adc_n,adc_bitwidth_t bits)355 static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits)
356 {
357 uint32_t reg_val = 0;
358 switch (bits) {
359 case ADC_BITWIDTH_9:
360 reg_val = 0;
361 break;
362 case ADC_BITWIDTH_10:
363 reg_val = 1;
364 break;
365 case ADC_BITWIDTH_11:
366 reg_val = 2;
367 break;
368 case ADC_BITWIDTH_12:
369 reg_val = 3;
370 break;
371 case ADC_BITWIDTH_DEFAULT:
372 reg_val = 3;
373 break;
374 default:
375 HAL_ASSERT(false);
376 }
377 if (adc_n == ADC_UNIT_1) {
378 SENS.sar_start_force.sar1_bit_width = reg_val;
379 SENS.sar_read_ctrl.sar1_sample_bit = reg_val;
380 } else { // adc_n == ADC_UNIT_2
381 SENS.sar_start_force.sar2_bit_width = reg_val;
382 SENS.sar_read_ctrl2.sar2_sample_bit = reg_val;
383 }
384 }
385
386 /**
387 * Enable adc channel to start convert.
388 *
389 * @note Only one channel can be selected in once measurement.
390 *
391 * @param adc_n ADC unit.
392 * @param channel ADC channel number for each ADCn.
393 */
adc_oneshot_ll_set_channel(adc_unit_t adc_n,int channel)394 static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, int channel)
395 {
396 if (adc_n == ADC_UNIT_1) {
397 SENS.sar_meas_start1.sar1_en_pad = (1 << channel); //only one channel is selected.
398 } else { // adc_n == ADC_UNIT_2
399 SENS.sar_meas_start2.sar2_en_pad = (1 << channel); //only one channel is selected.
400 }
401 }
402
403 /**
404 * Disable adc channel to start convert.
405 *
406 * @note Only one channel can be selected in once measurement.
407 *
408 * @param adc_n ADC unit.
409 */
adc_oneshot_ll_disable_channel(adc_unit_t adc_n)410 static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n)
411 {
412 if (adc_n == ADC_UNIT_1) {
413 SENS.sar_meas_start1.sar1_en_pad = 0; //only one channel is selected.
414 } else { // adc_n == ADC_UNIT_2
415 SENS.sar_meas_start2.sar2_en_pad = 0; //only one channel is selected.
416 }
417 }
418
419 /**
420 * Start conversion once by software for RTC controller.
421 *
422 * @note It may be block to wait conversion idle for ADC1.
423 *
424 * @param adc_n ADC unit.
425 */
adc_oneshot_ll_start(adc_unit_t adc_n)426 static inline void adc_oneshot_ll_start(adc_unit_t adc_n)
427 {
428 if (adc_n == ADC_UNIT_1) {
429 while (HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_slave_addr1, meas_status) != 0) {}
430 SENS.sar_meas_start1.meas1_start_sar = 0;
431 SENS.sar_meas_start1.meas1_start_sar = 1;
432 } else { // adc_n == ADC_UNIT_2
433 SENS.sar_meas_start2.meas2_start_sar = 0; //start force 0
434 SENS.sar_meas_start2.meas2_start_sar = 1; //start force 1
435 }
436 }
437
438 /**
439 * Clear the event for each ADCn for Oneshot mode
440 *
441 * @param event ADC event
442 */
adc_oneshot_ll_clear_event(uint32_t event)443 static inline void adc_oneshot_ll_clear_event(uint32_t event)
444 {
445 //For compatibility
446 }
447
448 /**
449 * Check the event for each ADCn for Oneshot mode
450 *
451 * @param event ADC event
452 *
453 * @return
454 * -true : The conversion process is finish.
455 * -false : The conversion process is not finish.
456 */
adc_oneshot_ll_get_event(uint32_t event)457 static inline bool adc_oneshot_ll_get_event(uint32_t event)
458 {
459 bool ret = true;
460 if (event == ADC_LL_EVENT_ADC1_ONESHOT_DONE) {
461 ret = (bool)SENS.sar_meas_start1.meas1_done_sar;
462 } else if (event == ADC_LL_EVENT_ADC2_ONESHOT_DONE) {
463 ret = (bool)SENS.sar_meas_start2.meas2_done_sar;
464 } else {
465 HAL_ASSERT(false);
466 }
467 return ret;
468 }
469
470 /**
471 * Get the converted value for each ADCn for RTC controller.
472 *
473 * @param adc_n ADC unit.
474 * @return
475 * - Converted value.
476 */
adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)477 static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
478 {
479 uint32_t ret_val = 0;
480 if (adc_n == ADC_UNIT_1) {
481 ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start1, meas1_data_sar);
482 } else { // adc_n == ADC_UNIT_2
483 ret_val = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_meas_start2, meas2_data_sar);
484 }
485 return ret_val;
486 }
487
488 /**
489 * ADC module RTC output data invert or not.
490 *
491 * @param adc_n ADC unit.
492 */
adc_oneshot_ll_output_invert(adc_unit_t adc_n,bool inv_en)493 static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en)
494 {
495 if (adc_n == ADC_UNIT_1) {
496 SENS.sar_read_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert
497 } else { // adc_n == ADC_UNIT_2
498 SENS.sar_read_ctrl2.sar2_data_inv = inv_en; // Enable / Disable ADC data invert
499 }
500 }
501
502 /**
503 * Analyze whether the obtained raw data is correct.
504 *
505 * @param adc_n ADC unit.
506 * @param raw ADC raw data input (convert value).
507 * @return
508 * - true: raw data is valid
509 */
adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n,uint32_t raw)510 static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw)
511 {
512 /* No arbiter, don't need check data */
513 return true;
514 }
515
516 /**
517 * Set the attenuation of a particular channel on ADCn.
518 */
adc_oneshot_ll_set_atten(adc_unit_t adc_n,adc_channel_t channel,adc_atten_t atten)519 static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
520 {
521 if (adc_n == ADC_UNIT_1) {
522 SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
523 } else { // adc_n == ADC_UNIT_2
524 SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
525 }
526 }
527
528 /**
529 * Get the attenuation of a particular channel on ADCn.
530 *
531 * @param adc_n ADC unit.
532 * @param channel ADCn channel number.
533 * @return atten The attenuation option.
534 */
535 __attribute__((always_inline))
adc_ll_get_atten(adc_unit_t adc_n,adc_channel_t channel)536 static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
537 {
538 if (adc_n == ADC_UNIT_1) {
539 return (adc_atten_t)((SENS.sar_atten1 >> (channel * 2)) & 0x3);
540 } else {
541 return (adc_atten_t)((SENS.sar_atten2 >> (channel * 2)) & 0x3);
542 }
543 }
544
545 /**
546 * Enable oneshot conversion trigger
547 *
548 * @param adc_n Not used, for compatibility
549 */
adc_oneshot_ll_enable(adc_unit_t adc_n)550 static inline void adc_oneshot_ll_enable(adc_unit_t adc_n)
551 {
552 (void)adc_n;
553 //For compatibility
554 }
555
556 /**
557 * Disable oneshot conversion trigger for all the ADC units
558 */
adc_oneshot_ll_disable_all_unit(void)559 static inline void adc_oneshot_ll_disable_all_unit(void)
560 {
561 //For compatibility
562 }
563
564 /*---------------------------------------------------------------
565 Common setting
566 ---------------------------------------------------------------*/
567 /**
568 * Set ADC module controller.
569 * There are five SAR ADC controllers:
570 * Two digital controller: Continuous conversion mode (DMA). High performance with multiple channel scan modes;
571 * Two RTC controller: Single conversion modes (Polling). For low power purpose working during deep sleep;
572 * the other is dedicated for Power detect (PWDET / PKDET), Only support ADC2.
573 *
574 * @param adc_n ADC unit.
575 * @param ctrl ADC controller.
576 */
577 __attribute__((always_inline))
adc_ll_set_controller(adc_unit_t adc_n,adc_ll_controller_t ctrl)578 static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
579 {
580 if (adc_n == ADC_UNIT_1) {
581 switch ( ctrl ) {
582 case ADC_LL_CTRL_RTC:
583 SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
584 SENS.sar_meas_start1.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
585 SENS.sar_meas_start1.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
586 SENS.sar_touch_ctrl1.xpd_hall_force = 1; // 1: SW control HALL power; 0: ULP FSM control HALL power.
587 SENS.sar_touch_ctrl1.hall_phase_force = 1; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
588 break;
589 case ADC_LL_CTRL_ULP:
590 SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
591 SENS.sar_meas_start1.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
592 SENS.sar_meas_start1.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
593 SENS.sar_touch_ctrl1.xpd_hall_force = 0; // 1: SW control HALL power; 0: ULP FSM control HALL power.
594 SENS.sar_touch_ctrl1.hall_phase_force = 0; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
595 break;
596 case ADC_LL_CTRL_DIG:
597 SENS.sar_read_ctrl.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
598 SENS.sar_meas_start1.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
599 SENS.sar_meas_start1.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
600 SENS.sar_touch_ctrl1.xpd_hall_force = 1; // 1: SW control HALL power; 0: ULP FSM control HALL power.
601 SENS.sar_touch_ctrl1.hall_phase_force = 1; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
602 break;
603 default:
604 break;
605 }
606 } else { // adc_n == ADC_UNIT_2
607 switch ( ctrl ) {
608 case ADC_LL_CTRL_RTC:
609 SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
610 SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
611 SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
612 SENS.sar_read_ctrl2.sar2_pwdet_force = 0; // 1: Select power detect control; 0: Select RTC control.
613 SYSCON.saradc_ctrl.sar2_mux = 1; // 1: Select digital control; 0: Select power detect control.
614 break;
615 case ADC_LL_CTRL_ULP:
616 SENS.sar_meas_start2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
617 SENS.sar_meas_start2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
618 SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
619 SENS.sar_read_ctrl2.sar2_pwdet_force = 0; // 1: Select power detect control; 0: Select RTC control.
620 SYSCON.saradc_ctrl.sar2_mux = 1; // 1: Select digital control; 0: Select power detect control.
621 break;
622 case ADC_LL_CTRL_DIG:
623 SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
624 SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
625 SENS.sar_read_ctrl2.sar2_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
626 SENS.sar_read_ctrl2.sar2_pwdet_force = 0; // 1: Select power detect control; 0: Select RTC control.
627 SYSCON.saradc_ctrl.sar2_mux = 1; // 1: Select digital control; 0: Select power detect control.
628 break;
629 case ADC_LL_CTRL_PWDET: // currently only used by Wi-Fi
630 SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
631 SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
632 SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
633 SENS.sar_read_ctrl2.sar2_pwdet_force = 1; // 1: Select power detect control; 0: Select RTC control.
634 SYSCON.saradc_ctrl.sar2_mux = 0; // 1: Select digital control; 0: Select power detect control.
635 break;
636 default:
637 break;
638 }
639 }
640 }
641
642 /**
643 * Close ADC AMP module if don't use it for power save.
644 */
adc_ll_amp_disable(void)645 static inline void adc_ll_amp_disable(void)
646 {
647 //channel is set in the convert function
648 SENS.sar_meas_wait2.force_xpd_amp = SENS_FORCE_XPD_AMP_PD;
649 //disable FSM, it's only used by the LNA.
650 SENS.sar_meas_ctrl.amp_rst_fb_fsm = 0;
651 SENS.sar_meas_ctrl.amp_short_ref_fsm = 0;
652 SENS.sar_meas_ctrl.amp_short_ref_gnd_fsm = 0;
653 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait1, 1);
654 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait2, 1);
655 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait2, sar_amp_wait3, 1);
656 }
657
658 /*---------------------------------------------------------------
659 Hall sensor setting
660 ---------------------------------------------------------------*/
661
662 /**
663 * Enable hall sensor.
664 */
adc_ll_hall_enable(void)665 static inline void adc_ll_hall_enable(void)
666 {
667 RTCIO.hall_sens.xpd_hall = 1;
668 }
669
670 /**
671 * Disable hall sensor.
672 */
adc_ll_hall_disable(void)673 static inline void adc_ll_hall_disable(void)
674 {
675 RTCIO.hall_sens.xpd_hall = 0;
676 }
677
678 /**
679 * Reverse phase of hall sensor.
680 */
adc_ll_hall_phase_enable(void)681 static inline void adc_ll_hall_phase_enable(void)
682 {
683 RTCIO.hall_sens.hall_phase = 1;
684 }
685
686 /**
687 * Don't reverse phase of hall sensor.
688 */
adc_ll_hall_phase_disable(void)689 static inline void adc_ll_hall_phase_disable(void)
690 {
691 RTCIO.hall_sens.hall_phase = 0;
692 }
693
694 /**
695 * Set hall sensor controller.
696 *
697 * @param hall_ctrl Hall controller.
698 */
adc_ll_set_hall_controller(adc_ll_hall_controller_t hall_ctrl)699 static inline void adc_ll_set_hall_controller(adc_ll_hall_controller_t hall_ctrl)
700 {
701 SENS.sar_touch_ctrl1.xpd_hall_force = hall_ctrl; // 1: SW control HALL power; 0: ULP FSM control HALL power.
702 SENS.sar_touch_ctrl1.hall_phase_force = hall_ctrl; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
703 }
704
705 /**
706 * Output ADC internal reference voltage to channels, only available for ADC2 on ESP32.
707 *
708 * This function routes the internal reference voltage of ADCn to one of
709 * ADC2's channels. This reference voltage can then be manually measured
710 * for calibration purposes.
711 *
712 * @param[in] adc ADC unit select
713 * @param[in] channel ADC2 channel number
714 * @param[in] en Enable/disable the reference voltage output
715 */
adc_ll_vref_output(adc_unit_t adc,adc_channel_t channel,bool en)716 static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
717 {
718 if (adc != ADC_UNIT_2) {
719 return;
720 }
721
722 if (en) {
723 RTCCNTL.bias_conf.dbg_atten = 0; //Check DBG effect outside sleep mode
724 //set dtest (MUX_SEL : 0 -> RTC; 1-> vdd_sar2)
725 RTCCNTL.test_mux.dtest_rtc = 1; //Config test mux to route v_ref to ADC2 Channels
726 //set ent
727 RTCCNTL.test_mux.ent_rtc = 1;
728 //set sar2_en_test
729 SENS.sar_start_force.sar2_en_test = 1;
730 //set sar2 en force
731 SENS.sar_meas_start2.sar2_en_pad_force = 1; //Pad bitmap controlled by SW
732 //set en_pad for channels 7,8,9 (bits 0x380)
733 SENS.sar_meas_start2.sar2_en_pad = 1 << channel;
734 } else {
735 RTCCNTL.test_mux.dtest_rtc = 0; //Config test mux to route v_ref to ADC2 Channels
736 //set ent
737 RTCCNTL.test_mux.ent_rtc = 0;
738 //set sar2_en_test
739 SENS.sar_start_force.sar2_en_test = 0;
740 //set sar2 en force
741 SENS.sar_meas_start2.sar2_en_pad_force = 0; //Pad bitmap controlled by SW
742 //set en_pad for channels 7,8,9 (bits 0x380)
743 SENS.sar_meas_start2.sar2_en_pad = 0;
744 }
745 }
746
747 #ifdef __cplusplus
748 }
749 #endif
750
