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Searched refs:divider (Results 1 – 25 of 48) sorted by relevance

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/hal_espressif-3.7.0/components/hal/esp32c6/include/hal/
Dclk_tree_ll.h384 static inline __attribute__((always_inline)) void clk_ll_cpu_set_hs_divider(uint32_t divider) in clk_ll_cpu_set_hs_divider() argument
393 HAL_ASSERT(divider == 3 || divider == 4 || divider == 6 || divider == 12); in clk_ll_cpu_set_hs_divider()
394 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_hs_div_num, (divider / 3) - 1); in clk_ll_cpu_set_hs_divider()
398 bool force_120m = (divider == 4) ? 1 : 0; in clk_ll_cpu_set_hs_divider()
407 static inline __attribute__((always_inline)) void clk_ll_cpu_set_ls_divider(uint32_t divider) in clk_ll_cpu_set_ls_divider() argument
415 HAL_ASSERT((divider > 0) && ((divider & (divider - 1)) == 0)); in clk_ll_cpu_set_ls_divider()
416 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_ls_div_num, divider - 1); in clk_ll_cpu_set_ls_divider()
452 static inline __attribute__((always_inline)) void clk_ll_ahb_set_hs_divider(uint32_t divider) in clk_ll_ahb_set_hs_divider() argument
460 HAL_ASSERT(divider == 12 || divider == 24 || divider == 48); in clk_ll_ahb_set_hs_divider()
461 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_hs_div_num, (divider / 3) - 1); in clk_ll_ahb_set_hs_divider()
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Dtimer_ll.h123 static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider) in timer_ll_set_clock_prescale() argument
125 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_clock_prescale()
126 if (divider >= 65536) { in timer_ll_set_clock_prescale()
127 divider = 0; in timer_ll_set_clock_prescale()
129 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); in timer_ll_set_clock_prescale()
/hal_espressif-3.7.0/components/esp_hw_support/port/esp32c6/
Drtc_clk.c198 uint32_t divider; // divider = freq of SOC_ROOT_CLK / freq of CPU_CLK in rtc_clk_cpu_freq_mhz_to_config() local
203 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
204 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
216 divider = 6; in rtc_clk_cpu_freq_mhz_to_config()
221 divider = 4; in rtc_clk_cpu_freq_mhz_to_config()
226 divider = 3; in rtc_clk_cpu_freq_mhz_to_config()
233 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
356 uint32_t divider; in rtc_clk_ahb_freq_get() local
360 divider = clk_ll_ahb_get_ls_divider(); in rtc_clk_ahb_freq_get()
364 divider = clk_ll_ahb_get_hs_divider(); in rtc_clk_ahb_freq_get()
[all …]
/hal_espressif-3.7.0/components/hal/esp32h2/include/hal/
Dclk_tree_ll.h400 static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider) in clk_ll_cpu_set_divider() argument
402 HAL_ASSERT(divider >= 1); in clk_ll_cpu_set_divider()
403 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, divider - 1); in clk_ll_cpu_set_divider()
421 static inline __attribute__((always_inline)) void clk_ll_ahb_set_divider(uint32_t divider) in clk_ll_ahb_set_divider() argument
423 HAL_ASSERT(divider >= 1); in clk_ll_ahb_set_divider()
424 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, divider - 1); in clk_ll_ahb_set_divider()
442 static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_t divider) in clk_ll_apb_set_divider() argument
446 HAL_ASSERT(divider == 1 || divider == 2 || divider == 4); in clk_ll_apb_set_divider()
447 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num, divider - 1); in clk_ll_apb_set_divider()
650 static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) in clk_ll_rc_fast_set_divider() argument
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Dtimer_ll.h123 static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider) in timer_ll_set_clock_prescale() argument
125 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_clock_prescale()
126 if (divider >= 65536) { in timer_ll_set_clock_prescale()
127 divider = 0; in timer_ll_set_clock_prescale()
129 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); in timer_ll_set_clock_prescale()
/hal_espressif-3.7.0/components/hal/esp32c6/
Dclk_tree_hal.c34 …uint32_t divider = (source == SOC_CPU_CLK_SRC_PLL) ? clk_ll_cpu_get_hs_divider() : clk_ll_cpu_get_… in clk_hal_cpu_get_freq_hz() local
35 return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider; in clk_hal_cpu_get_freq_hz()
41 …uint32_t divider = (source == SOC_CPU_CLK_SRC_PLL) ? clk_ll_ahb_get_hs_divider() : clk_ll_ahb_get_… in clk_hal_ahb_get_freq_hz() local
42 return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider; in clk_hal_ahb_get_freq_hz()
/hal_espressif-3.7.0/components/esp_hw_support/port/esp32h2/
Drtc_clk.c238 uint32_t divider; // divider = freq of SOC_ROOT_CLK / freq of CPU_CLK in rtc_clk_cpu_freq_mhz_to_config() local
243 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
244 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
256 divider = 1; in rtc_clk_cpu_freq_mhz_to_config()
261 divider = 1; in rtc_clk_cpu_freq_mhz_to_config()
266 divider = 2; in rtc_clk_cpu_freq_mhz_to_config()
273 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
404 uint32_t divider = clk_ll_ahb_get_divider(); in rtc_clk_ahb_freq_get() local
424 return soc_root_freq_mhz / divider; in rtc_clk_ahb_freq_get()
/hal_espressif-3.7.0/components/esp_hw_support/port/esp32c2/
Drtc_clk.c156 uint32_t divider; in rtc_clk_cpu_freq_mhz_to_config() local
161 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
162 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
174 divider = 6; in rtc_clk_cpu_freq_mhz_to_config()
179 divider = 4; in rtc_clk_cpu_freq_mhz_to_config()
186 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
/hal_espressif-3.7.0/components/hal/esp32/include/hal/
Dtimer_ll.h82 static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider) in timer_ll_set_clock_prescale() argument
84 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_clock_prescale()
85 if (divider >= 65536) { in timer_ll_set_clock_prescale()
86 divider = 0; in timer_ll_set_clock_prescale()
88 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); in timer_ll_set_clock_prescale()
/hal_espressif-3.7.0/components/esp_hw_support/port/esp32c3/
Drtc_clk.c179 uint32_t divider; in rtc_clk_cpu_freq_mhz_to_config() local
184 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
185 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
197 divider = 6; in rtc_clk_cpu_freq_mhz_to_config()
202 divider = 3; in rtc_clk_cpu_freq_mhz_to_config()
209 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
/hal_espressif-3.7.0/components/hal/esp32c3/include/hal/
Dtimer_ll.h81 static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider) in timer_ll_set_clock_prescale() argument
83 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_clock_prescale()
84 if (divider >= 65536) { in timer_ll_set_clock_prescale()
85 divider = 0; in timer_ll_set_clock_prescale()
87 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); in timer_ll_set_clock_prescale()
Dclk_tree_ll.h478 static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider) in clk_ll_cpu_set_divider() argument
480 HAL_ASSERT(divider > 0); in clk_ll_cpu_set_divider()
481 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, divider - 1); in clk_ll_cpu_set_divider()
581 static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) in clk_ll_rc_fast_set_divider() argument
583 HAL_ASSERT(divider > 0); in clk_ll_rc_fast_set_divider()
585 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, divider - 1); in clk_ll_rc_fast_set_divider()
604 static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) in clk_ll_rc_slow_set_divider() argument
606 HAL_ASSERT(divider > 0); in clk_ll_rc_slow_set_divider()
608 REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, divider - 1); in clk_ll_rc_slow_set_divider()
/hal_espressif-3.7.0/components/hal/esp32s2/include/hal/
Dtimer_ll.h86 static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider) in timer_ll_set_clock_prescale() argument
88 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_clock_prescale()
89 if (divider >= 65536) { in timer_ll_set_clock_prescale()
90 divider = 0; in timer_ll_set_clock_prescale()
92 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); in timer_ll_set_clock_prescale()
Dclk_tree_ll.h548 static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider) in clk_ll_cpu_set_divider() argument
550 HAL_ASSERT(divider > 0); in clk_ll_cpu_set_divider()
551 REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, divider - 1); in clk_ll_cpu_set_divider()
697 static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) in clk_ll_rc_fast_set_divider() argument
699 HAL_ASSERT(divider > 0); in clk_ll_rc_fast_set_divider()
701 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, divider - 1); in clk_ll_rc_fast_set_divider()
720 static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) in clk_ll_rc_slow_set_divider() argument
722 HAL_ASSERT(divider > 0); in clk_ll_rc_slow_set_divider()
724 REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, divider - 1); in clk_ll_rc_slow_set_divider()
/hal_espressif-3.7.0/components/hal/esp32s3/include/hal/
Dtimer_ll.h84 static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider) in timer_ll_set_clock_prescale() argument
86 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_clock_prescale()
87 if (divider >= 65536) { in timer_ll_set_clock_prescale()
88 divider = 0; in timer_ll_set_clock_prescale()
90 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tn_divider, divider); in timer_ll_set_clock_prescale()
Dclk_tree_ll.h485 static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider) in clk_ll_cpu_set_divider() argument
487 HAL_ASSERT(divider > 0); in clk_ll_cpu_set_divider()
488 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, divider - 1); in clk_ll_cpu_set_divider()
589 static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) in clk_ll_rc_fast_set_divider() argument
591 HAL_ASSERT(divider > 0); in clk_ll_rc_fast_set_divider()
593 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, divider - 1); in clk_ll_rc_fast_set_divider()
612 static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) in clk_ll_rc_slow_set_divider() argument
614 HAL_ASSERT(divider > 0); in clk_ll_rc_slow_set_divider()
616 REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, divider - 1); in clk_ll_rc_slow_set_divider()
/hal_espressif-3.7.0/components/hal/esp32c2/include/hal/
Dtimer_ll.h81 static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider) in timer_ll_set_clock_prescale() argument
83 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_clock_prescale()
84 if (divider >= 65536) { in timer_ll_set_clock_prescale()
85 divider = 0; in timer_ll_set_clock_prescale()
87 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); in timer_ll_set_clock_prescale()
Dclk_tree_ll.h370 static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider) in clk_ll_cpu_set_divider() argument
372 HAL_ASSERT(divider > 0); in clk_ll_cpu_set_divider()
373 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, divider - 1); in clk_ll_cpu_set_divider()
473 static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider) in clk_ll_rc_fast_set_divider() argument
475 HAL_ASSERT(divider > 0); in clk_ll_rc_fast_set_divider()
477 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, divider - 1); in clk_ll_rc_fast_set_divider()
496 static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider) in clk_ll_rc_slow_set_divider() argument
498 HAL_ASSERT(divider > 0); in clk_ll_rc_slow_set_divider()
500 REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, divider - 1); in clk_ll_rc_slow_set_divider()
/hal_espressif-3.7.0/components/esp_hw_support/port/esp32s3/
Drtc_clk.c233 uint32_t divider; in rtc_clk_cpu_freq_mhz_to_config() local
238 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
239 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
251 divider = 6; in rtc_clk_cpu_freq_mhz_to_config()
256 divider = 3; in rtc_clk_cpu_freq_mhz_to_config()
261 divider = 2; in rtc_clk_cpu_freq_mhz_to_config()
268 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
/hal_espressif-3.7.0/components/esp_hw_support/port/esp32s2/
Drtc_clk.c272 uint32_t divider; in rtc_clk_cpu_freq_mhz_to_config() local
277 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
278 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
290 divider = 6; in rtc_clk_cpu_freq_mhz_to_config()
295 divider = 3; in rtc_clk_cpu_freq_mhz_to_config()
300 divider = 2; in rtc_clk_cpu_freq_mhz_to_config()
307 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
/hal_espressif-3.7.0/components/hal/esp32/
Dclk_tree_hal.c41 uint32_t divider = clk_ll_cpu_get_divider_from_apll(); in clk_hal_cpu_get_freq_hz() local
42 if (divider == 0) { in clk_hal_cpu_get_freq_hz()
46 return apll_freq_hz / divider; in clk_hal_cpu_get_freq_hz()
/hal_espressif-3.7.0/components/hal/esp32s2/
Dclk_tree_hal.c48 uint32_t divider = clk_ll_cpu_get_divider_from_apll(); in clk_hal_cpu_get_freq_hz() local
49 if (divider == 0) { in clk_hal_cpu_get_freq_hz()
53 return apll_freq_hz / divider; in clk_hal_cpu_get_freq_hz()
/hal_espressif-3.7.0/components/esp_hw_support/port/esp32/
Drtc_clk.c418 uint32_t divider; in rtc_clk_cpu_freq_mhz_to_config() local
423 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
424 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
436 divider = 4; in rtc_clk_cpu_freq_mhz_to_config()
441 divider = 2; in rtc_clk_cpu_freq_mhz_to_config()
446 divider = 2; in rtc_clk_cpu_freq_mhz_to_config()
453 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
/hal_espressif-3.7.0/components/bt/esp_ble_mesh/mesh_common/include/
Dmesh_util.h97 #define ceiling_fraction(numerator, divider) \ argument
98 (((numerator) + ((divider) - 1)) / (divider))
/hal_espressif-3.7.0/components/driver/deprecated/
Dtimer_legacy.c49 uint32_t divider; member
78 uint32_t div = p_timer_obj[group_num][timer_num]->divider; in timer_get_counter_time_sec()
148 esp_err_t timer_set_divider(timer_group_t group_num, timer_idx_t timer_num, uint32_t divider) in timer_set_divider() argument
152 …ESP_RETURN_ON_FALSE(divider > 1 && divider < 65537, ESP_ERR_INVALID_ARG, TIMER_TAG, DIVIDER_RANGE… in timer_set_divider()
155 timer_ll_set_clock_prescale(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, divider); in timer_set_divider()
156 p_timer_obj[group_num][timer_num]->divider = divider; in timer_set_divider()
300 …ESP_RETURN_ON_FALSE(config->divider > 1 && config->divider < 65537, ESP_ERR_INVALID_ARG, TIMER_TAG… in timer_init()
321 timer_ll_set_clock_prescale(hal->dev, timer_num, config->divider); in timer_init()
333 p_timer_obj[group_num][timer_num]->divider = config->divider; in timer_init()
370 config->divider = p_timer_obj[group_num][timer_num]->divider; in timer_get_config()

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