1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 typedef volatile struct i2s_dev_s { 15 uint32_t fifo_wr; 16 uint32_t fifo_rd; 17 union { 18 struct { 19 uint32_t tx_reset: 1; 20 uint32_t rx_reset: 1; 21 uint32_t tx_fifo_reset: 1; 22 uint32_t rx_fifo_reset: 1; 23 uint32_t tx_start: 1; 24 uint32_t rx_start: 1; 25 uint32_t tx_slave_mod: 1; 26 uint32_t rx_slave_mod: 1; 27 uint32_t tx_right_first: 1; 28 uint32_t rx_right_first: 1; 29 uint32_t tx_msb_shift: 1; 30 uint32_t rx_msb_shift: 1; 31 uint32_t tx_short_sync: 1; 32 uint32_t rx_short_sync: 1; 33 uint32_t tx_mono: 1; 34 uint32_t rx_mono: 1; 35 uint32_t tx_msb_right: 1; 36 uint32_t rx_msb_right: 1; 37 uint32_t sig_loopback: 1; 38 uint32_t reserved19: 13; 39 }; 40 uint32_t val; 41 } conf; 42 union { 43 struct { 44 uint32_t rx_take_data: 1; 45 uint32_t tx_put_data: 1; 46 uint32_t rx_wfull: 1; 47 uint32_t rx_rempty: 1; 48 uint32_t tx_wfull: 1; 49 uint32_t tx_rempty: 1; 50 uint32_t rx_hung: 1; 51 uint32_t tx_hung: 1; 52 uint32_t in_done: 1; 53 uint32_t in_suc_eof: 1; 54 uint32_t in_err_eof: 1; 55 uint32_t out_done: 1; 56 uint32_t out_eof: 1; 57 uint32_t in_dscr_err: 1; 58 uint32_t out_dscr_err: 1; 59 uint32_t in_dscr_empty: 1; 60 uint32_t out_total_eof: 1; 61 uint32_t reserved17: 15; 62 }; 63 uint32_t val; 64 } int_raw; 65 union { 66 struct { 67 uint32_t rx_take_data: 1; 68 uint32_t tx_put_data: 1; 69 uint32_t rx_wfull: 1; 70 uint32_t rx_rempty: 1; 71 uint32_t tx_wfull: 1; 72 uint32_t tx_rempty: 1; 73 uint32_t rx_hung: 1; 74 uint32_t tx_hung: 1; 75 uint32_t in_done: 1; 76 uint32_t in_suc_eof: 1; 77 uint32_t in_err_eof: 1; 78 uint32_t out_done: 1; 79 uint32_t out_eof: 1; 80 uint32_t in_dscr_err: 1; 81 uint32_t out_dscr_err: 1; 82 uint32_t in_dscr_empty: 1; 83 uint32_t out_total_eof: 1; 84 uint32_t reserved17: 15; 85 }; 86 uint32_t val; 87 } int_st; 88 union { 89 struct { 90 uint32_t rx_take_data: 1; 91 uint32_t tx_put_data: 1; 92 uint32_t rx_wfull: 1; 93 uint32_t rx_rempty: 1; 94 uint32_t tx_wfull: 1; 95 uint32_t tx_rempty: 1; 96 uint32_t rx_hung: 1; 97 uint32_t tx_hung: 1; 98 uint32_t in_done: 1; 99 uint32_t in_suc_eof: 1; 100 uint32_t in_err_eof: 1; 101 uint32_t out_done: 1; 102 uint32_t out_eof: 1; 103 uint32_t in_dscr_err: 1; 104 uint32_t out_dscr_err: 1; 105 uint32_t in_dscr_empty: 1; 106 uint32_t out_total_eof: 1; 107 uint32_t reserved17: 15; 108 }; 109 uint32_t val; 110 } int_ena; 111 union { 112 struct { 113 uint32_t take_data: 1; 114 uint32_t put_data: 1; 115 uint32_t rx_wfull: 1; 116 uint32_t rx_rempty: 1; 117 uint32_t tx_wfull: 1; 118 uint32_t tx_rempty: 1; 119 uint32_t rx_hung: 1; 120 uint32_t tx_hung: 1; 121 uint32_t in_done: 1; 122 uint32_t in_suc_eof: 1; 123 uint32_t in_err_eof: 1; 124 uint32_t out_done: 1; 125 uint32_t out_eof: 1; 126 uint32_t in_dscr_err: 1; 127 uint32_t out_dscr_err: 1; 128 uint32_t in_dscr_empty: 1; 129 uint32_t out_total_eof: 1; 130 uint32_t reserved17: 15; 131 }; 132 uint32_t val; 133 } int_clr; 134 union { 135 struct { 136 uint32_t tx_bck_in_delay: 2; 137 uint32_t tx_ws_in_delay: 2; 138 uint32_t rx_bck_in_delay: 2; 139 uint32_t rx_ws_in_delay: 2; 140 uint32_t rx_sd_in_delay: 2; 141 uint32_t tx_bck_out_delay: 2; 142 uint32_t tx_ws_out_delay: 2; 143 uint32_t tx_sd_out_delay: 2; 144 uint32_t rx_ws_out_delay: 2; 145 uint32_t rx_bck_out_delay: 2; 146 uint32_t tx_dsync_sw: 1; 147 uint32_t rx_dsync_sw: 1; 148 uint32_t data_enable_delay: 2; 149 uint32_t tx_bck_in_inv: 1; 150 uint32_t reserved25: 7; 151 }; 152 uint32_t val; 153 } timing; 154 union { 155 struct { 156 uint32_t rx_data_num: 6; 157 uint32_t tx_data_num: 6; 158 uint32_t dscr_en: 1; 159 uint32_t tx_fifo_mod: 3; 160 uint32_t rx_fifo_mod: 3; 161 uint32_t tx_fifo_mod_force_en: 1; 162 uint32_t rx_fifo_mod_force_en: 1; 163 uint32_t reserved21: 11; 164 }; 165 uint32_t val; 166 } fifo_conf; 167 uint32_t rx_eof_num; 168 uint32_t conf_single_data; 169 union { 170 struct { 171 uint32_t tx_chan_mod: 3; 172 uint32_t rx_chan_mod: 2; 173 uint32_t reserved5: 27; 174 }; 175 uint32_t val; 176 } conf_chan; 177 union { 178 struct { 179 uint32_t addr: 20; 180 uint32_t reserved20: 8; 181 uint32_t stop: 1; 182 uint32_t start: 1; 183 uint32_t restart: 1; 184 uint32_t park: 1; 185 }; 186 uint32_t val; 187 } out_link; 188 union { 189 struct { 190 uint32_t addr: 20; 191 uint32_t reserved20: 8; 192 uint32_t stop: 1; 193 uint32_t start: 1; 194 uint32_t restart: 1; 195 uint32_t park: 1; 196 }; 197 uint32_t val; 198 } in_link; 199 uint32_t out_eof_des_addr; 200 uint32_t in_eof_des_addr; 201 uint32_t out_eof_bfr_des_addr; 202 union { 203 struct { 204 uint32_t mode: 3; 205 uint32_t reserved3: 1; 206 uint32_t addr: 2; 207 uint32_t reserved6: 26; 208 }; 209 uint32_t val; 210 } ahb_test; 211 uint32_t in_link_dscr; 212 uint32_t in_link_dscr_bf0; 213 uint32_t in_link_dscr_bf1; 214 uint32_t out_link_dscr; 215 uint32_t out_link_dscr_bf0; 216 uint32_t out_link_dscr_bf1; 217 union { 218 struct { 219 uint32_t in_rst: 1; 220 uint32_t out_rst: 1; 221 uint32_t ahbm_fifo_rst: 1; 222 uint32_t ahbm_rst: 1; 223 uint32_t out_loop_test: 1; 224 uint32_t in_loop_test: 1; 225 uint32_t out_auto_wrback: 1; 226 uint32_t out_no_restart_clr: 1; 227 uint32_t out_eof_mode: 1; 228 uint32_t outdscr_burst_en: 1; 229 uint32_t indscr_burst_en: 1; 230 uint32_t out_data_burst_en: 1; 231 uint32_t check_owner: 1; 232 uint32_t mem_trans_en: 1; 233 uint32_t reserved14: 18; 234 }; 235 uint32_t val; 236 } lc_conf; 237 union { 238 struct { 239 uint32_t wdata: 9; 240 uint32_t reserved9: 7; 241 uint32_t push: 1; 242 uint32_t reserved17: 15; 243 }; 244 uint32_t val; 245 } out_fifo_push; 246 union { 247 struct { 248 uint32_t rdata: 12; 249 uint32_t reserved12: 4; 250 uint32_t pop: 1; 251 uint32_t reserved17: 15; 252 }; 253 uint32_t val; 254 } in_fifo_pop; 255 uint32_t lc_state0; 256 uint32_t lc_state1; 257 union { 258 struct { 259 uint32_t fifo_timeout: 8; 260 uint32_t fifo_timeout_shift: 3; 261 uint32_t fifo_timeout_ena: 1; 262 uint32_t reserved12: 20; 263 }; 264 uint32_t val; 265 } lc_hung_conf; 266 uint32_t reserved_78; 267 uint32_t reserved_7c; 268 union { 269 struct { 270 uint32_t y_max:16; 271 uint32_t y_min:16; 272 }; 273 uint32_t val; 274 } cvsd_conf0; 275 union { 276 struct { 277 uint32_t sigma_max:16; 278 uint32_t sigma_min:16; 279 }; 280 uint32_t val; 281 } cvsd_conf1; 282 union { 283 struct { 284 uint32_t cvsd_k: 3; 285 uint32_t cvsd_j: 3; 286 uint32_t cvsd_beta: 10; 287 uint32_t cvsd_h: 3; 288 uint32_t reserved19:13; 289 }; 290 uint32_t val; 291 } cvsd_conf2; 292 union { 293 struct { 294 uint32_t good_pack_max: 6; 295 uint32_t n_err_seg: 3; 296 uint32_t shift_rate: 3; 297 uint32_t max_slide_sample: 8; 298 uint32_t pack_len_8k: 5; 299 uint32_t n_min_err: 3; 300 uint32_t reserved28: 4; 301 }; 302 uint32_t val; 303 } plc_conf0; 304 union { 305 struct { 306 uint32_t bad_cef_atten_para: 8; 307 uint32_t bad_cef_atten_para_shift: 4; 308 uint32_t bad_ola_win2_para_shift: 4; 309 uint32_t bad_ola_win2_para: 8; 310 uint32_t slide_win_len: 8; 311 }; 312 uint32_t val; 313 } plc_conf1; 314 union { 315 struct { 316 uint32_t cvsd_seg_mod: 2; 317 uint32_t min_period: 5; 318 uint32_t reserved7: 25; 319 }; 320 uint32_t val; 321 } plc_conf2; 322 union { 323 struct { 324 uint32_t en: 1; 325 uint32_t chan_mod: 1; 326 uint32_t cvsd_dec_pack_err: 1; 327 uint32_t cvsd_pack_len_8k: 5; 328 uint32_t cvsd_inf_en: 1; 329 uint32_t cvsd_dec_start: 1; 330 uint32_t cvsd_dec_reset: 1; 331 uint32_t plc_en: 1; 332 uint32_t plc2dma_en: 1; 333 uint32_t reserved13: 19; 334 }; 335 uint32_t val; 336 } esco_conf0; 337 union { 338 struct { 339 uint32_t with_en: 1; 340 uint32_t no_en: 1; 341 uint32_t cvsd_enc_start: 1; 342 uint32_t cvsd_enc_reset: 1; 343 uint32_t reserved4: 28; 344 }; 345 uint32_t val; 346 } sco_conf0; 347 union { 348 struct { 349 uint32_t tx_pcm_conf: 3; 350 uint32_t tx_pcm_bypass: 1; 351 uint32_t rx_pcm_conf: 3; 352 uint32_t rx_pcm_bypass: 1; 353 uint32_t tx_stop_en: 1; 354 uint32_t tx_zeros_rm_en: 1; 355 uint32_t reserved10: 22; 356 }; 357 uint32_t val; 358 } conf1; 359 union { 360 struct { 361 uint32_t fifo_force_pd: 1; 362 uint32_t fifo_force_pu: 1; 363 uint32_t plc_mem_force_pd: 1; 364 uint32_t plc_mem_force_pu: 1; 365 uint32_t reserved4: 28; 366 }; 367 uint32_t val; 368 } pd_conf; 369 union { 370 struct { 371 uint32_t camera_en: 1; 372 uint32_t lcd_tx_wrx2_en: 1; 373 uint32_t lcd_tx_sdx2_en: 1; 374 uint32_t data_enable_test_en: 1; 375 uint32_t data_enable: 1; 376 uint32_t lcd_en: 1; 377 uint32_t ext_adc_start_en: 1; 378 uint32_t inter_valid_en: 1; 379 uint32_t reserved8: 24; 380 }; 381 uint32_t val; 382 } conf2; 383 union { 384 struct { 385 uint32_t clkm_div_num: 8; 386 uint32_t clkm_div_b: 6; 387 uint32_t clkm_div_a: 6; 388 uint32_t clk_en: 1; 389 uint32_t clka_en: 1; 390 uint32_t reserved22: 10; 391 }; 392 uint32_t val; 393 } clkm_conf; 394 union { 395 struct { 396 uint32_t tx_bck_div_num: 6; 397 uint32_t rx_bck_div_num: 6; 398 uint32_t tx_bits_mod: 6; 399 uint32_t rx_bits_mod: 6; 400 uint32_t reserved24: 8; 401 }; 402 uint32_t val; 403 } sample_rate_conf; 404 union { 405 struct { 406 uint32_t tx_pdm_en: 1; 407 uint32_t rx_pdm_en: 1; 408 uint32_t pcm2pdm_conv_en: 1; 409 uint32_t pdm2pcm_conv_en: 1; 410 uint32_t tx_sinc_osr2: 4; 411 uint32_t tx_prescale: 8; 412 uint32_t tx_hp_in_shift: 2; 413 uint32_t tx_lp_in_shift: 2; 414 uint32_t tx_sinc_in_shift: 2; 415 uint32_t tx_sigmadelta_in_shift: 2; 416 uint32_t rx_sinc_dsr_16_en: 1; 417 uint32_t txhp_bypass: 1; 418 uint32_t reserved26: 6; 419 }; 420 uint32_t val; 421 } pdm_conf; 422 union { 423 struct { 424 uint32_t tx_pdm_fs: 10; 425 uint32_t tx_pdm_fp: 10; 426 uint32_t reserved20:12; 427 }; 428 uint32_t val; 429 } pdm_freq_conf; 430 union { 431 struct { 432 uint32_t tx_idle: 1; 433 uint32_t tx_fifo_reset_back: 1; 434 uint32_t rx_fifo_reset_back: 1; 435 uint32_t reserved3: 29; 436 }; 437 uint32_t val; 438 } state; 439 uint32_t reserved_c0; 440 uint32_t reserved_c4; 441 uint32_t reserved_c8; 442 uint32_t reserved_cc; 443 uint32_t reserved_d0; 444 uint32_t reserved_d4; 445 uint32_t reserved_d8; 446 uint32_t reserved_dc; 447 uint32_t reserved_e0; 448 uint32_t reserved_e4; 449 uint32_t reserved_e8; 450 uint32_t reserved_ec; 451 uint32_t reserved_f0; 452 uint32_t reserved_f4; 453 uint32_t reserved_f8; 454 uint32_t date; /**/ 455 } i2s_dev_t; 456 extern i2s_dev_t I2S0; 457 extern i2s_dev_t I2S1; 458 459 #ifdef __cplusplus 460 } 461 #endif 462
