1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #ifndef _SOC_RTC_IO_REG_H_
15 #define _SOC_RTC_IO_REG_H_
16 
17 
18 #include "soc.h"
19 #define RTC_GPIO_OUT_REG          (DR_REG_RTCIO_BASE + 0x0)
20 /* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */
21 /*description: GPIO0~17 output value*/
22 #define RTC_GPIO_OUT_DATA  0x0003FFFF
23 #define RTC_GPIO_OUT_DATA_M  ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S))
24 #define RTC_GPIO_OUT_DATA_V  0x3FFFF
25 #define RTC_GPIO_OUT_DATA_S  14
26 
27 #define RTC_GPIO_OUT_W1TS_REG          (DR_REG_RTCIO_BASE + 0x4)
28 /* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
29 /*description: GPIO0~17 output value write 1 to set*/
30 #define RTC_GPIO_OUT_DATA_W1TS  0x0003FFFF
31 #define RTC_GPIO_OUT_DATA_W1TS_M  ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S))
32 #define RTC_GPIO_OUT_DATA_W1TS_V  0x3FFFF
33 #define RTC_GPIO_OUT_DATA_W1TS_S  14
34 
35 #define RTC_GPIO_OUT_W1TC_REG          (DR_REG_RTCIO_BASE + 0x8)
36 /* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
37 /*description: GPIO0~17 output value write 1 to clear*/
38 #define RTC_GPIO_OUT_DATA_W1TC  0x0003FFFF
39 #define RTC_GPIO_OUT_DATA_W1TC_M  ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S))
40 #define RTC_GPIO_OUT_DATA_W1TC_V  0x3FFFF
41 #define RTC_GPIO_OUT_DATA_W1TC_S  14
42 
43 #define RTC_GPIO_ENABLE_REG          (DR_REG_RTCIO_BASE + 0xc)
44 /* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */
45 /*description: GPIO0~17 output enable*/
46 #define RTC_GPIO_ENABLE  0x0003FFFF
47 #define RTC_GPIO_ENABLE_M  ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S))
48 #define RTC_GPIO_ENABLE_V  0x3FFFF
49 #define RTC_GPIO_ENABLE_S  14
50 
51 #define RTC_GPIO_ENABLE_W1TS_REG          (DR_REG_RTCIO_BASE + 0x10)
52 /* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
53 /*description: GPIO0~17 output enable write 1 to set*/
54 #define RTC_GPIO_ENABLE_W1TS  0x0003FFFF
55 #define RTC_GPIO_ENABLE_W1TS_M  ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S))
56 #define RTC_GPIO_ENABLE_W1TS_V  0x3FFFF
57 #define RTC_GPIO_ENABLE_W1TS_S  14
58 
59 #define RTC_GPIO_ENABLE_W1TC_REG          (DR_REG_RTCIO_BASE + 0x14)
60 /* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
61 /*description: GPIO0~17 output enable write 1 to clear*/
62 #define RTC_GPIO_ENABLE_W1TC  0x0003FFFF
63 #define RTC_GPIO_ENABLE_W1TC_M  ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S))
64 #define RTC_GPIO_ENABLE_W1TC_V  0x3FFFF
65 #define RTC_GPIO_ENABLE_W1TC_S  14
66 
67 #define RTC_GPIO_STATUS_REG          (DR_REG_RTCIO_BASE + 0x18)
68 /* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */
69 /*description: GPIO0~17 interrupt status*/
70 #define RTC_GPIO_STATUS_INT  0x0003FFFF
71 #define RTC_GPIO_STATUS_INT_M  ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S))
72 #define RTC_GPIO_STATUS_INT_V  0x3FFFF
73 #define RTC_GPIO_STATUS_INT_S  14
74 
75 #define RTC_GPIO_STATUS_W1TS_REG          (DR_REG_RTCIO_BASE + 0x1c)
76 /* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
77 /*description: GPIO0~17 interrupt status write 1 to set*/
78 #define RTC_GPIO_STATUS_INT_W1TS  0x0003FFFF
79 #define RTC_GPIO_STATUS_INT_W1TS_M  ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S))
80 #define RTC_GPIO_STATUS_INT_W1TS_V  0x3FFFF
81 #define RTC_GPIO_STATUS_INT_W1TS_S  14
82 
83 #define RTC_GPIO_STATUS_W1TC_REG          (DR_REG_RTCIO_BASE + 0x20)
84 /* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
85 /*description: GPIO0~17 interrupt status write 1 to clear*/
86 #define RTC_GPIO_STATUS_INT_W1TC  0x0003FFFF
87 #define RTC_GPIO_STATUS_INT_W1TC_M  ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S))
88 #define RTC_GPIO_STATUS_INT_W1TC_V  0x3FFFF
89 #define RTC_GPIO_STATUS_INT_W1TC_S  14
90 
91 #define RTC_GPIO_IN_REG          (DR_REG_RTCIO_BASE + 0x24)
92 /* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default:  ; */
93 /*description: GPIO0~17 input value*/
94 #define RTC_GPIO_IN_NEXT  0x0003FFFF
95 #define RTC_GPIO_IN_NEXT_M  ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S))
96 #define RTC_GPIO_IN_NEXT_V  0x3FFFF
97 #define RTC_GPIO_IN_NEXT_S  14
98 
99 #define RTC_GPIO_PIN0_REG          (DR_REG_RTCIO_BASE + 0x28)
100 /* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
101 /*description: GPIO wake up enable  only available in light sleep*/
102 #define RTC_GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))
103 #define RTC_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
104 #define RTC_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
105 #define RTC_GPIO_PIN0_WAKEUP_ENABLE_S  10
106 /* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
107 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
108  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
109 #define RTC_GPIO_PIN0_INT_TYPE  0x00000007
110 #define RTC_GPIO_PIN0_INT_TYPE_M  ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S))
111 #define RTC_GPIO_PIN0_INT_TYPE_V  0x7
112 #define RTC_GPIO_PIN0_INT_TYPE_S  7
113 /* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
114 /*description: if set to 0: normal output  if set to 1: open drain*/
115 #define RTC_GPIO_PIN0_PAD_DRIVER  (BIT(2))
116 #define RTC_GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
117 #define RTC_GPIO_PIN0_PAD_DRIVER_V  0x1
118 #define RTC_GPIO_PIN0_PAD_DRIVER_S  2
119 
120 #define RTC_GPIO_PIN1_REG          (DR_REG_RTCIO_BASE + 0x2c)
121 /* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
122 /*description: GPIO wake up enable  only available in light sleep*/
123 #define RTC_GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))
124 #define RTC_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
125 #define RTC_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
126 #define RTC_GPIO_PIN1_WAKEUP_ENABLE_S  10
127 /* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
128 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
129  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
130 #define RTC_GPIO_PIN1_INT_TYPE  0x00000007
131 #define RTC_GPIO_PIN1_INT_TYPE_M  ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S))
132 #define RTC_GPIO_PIN1_INT_TYPE_V  0x7
133 #define RTC_GPIO_PIN1_INT_TYPE_S  7
134 /* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
135 /*description: if set to 0: normal output  if set to 1: open drain*/
136 #define RTC_GPIO_PIN1_PAD_DRIVER  (BIT(2))
137 #define RTC_GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
138 #define RTC_GPIO_PIN1_PAD_DRIVER_V  0x1
139 #define RTC_GPIO_PIN1_PAD_DRIVER_S  2
140 
141 #define RTC_GPIO_PIN2_REG          (DR_REG_RTCIO_BASE + 0x30)
142 /* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
143 /*description: GPIO wake up enable  only available in light sleep*/
144 #define RTC_GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))
145 #define RTC_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
146 #define RTC_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
147 #define RTC_GPIO_PIN2_WAKEUP_ENABLE_S  10
148 /* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
149 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
150  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
151 #define RTC_GPIO_PIN2_INT_TYPE  0x00000007
152 #define RTC_GPIO_PIN2_INT_TYPE_M  ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S))
153 #define RTC_GPIO_PIN2_INT_TYPE_V  0x7
154 #define RTC_GPIO_PIN2_INT_TYPE_S  7
155 /* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
156 /*description: if set to 0: normal output  if set to 1: open drain*/
157 #define RTC_GPIO_PIN2_PAD_DRIVER  (BIT(2))
158 #define RTC_GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
159 #define RTC_GPIO_PIN2_PAD_DRIVER_V  0x1
160 #define RTC_GPIO_PIN2_PAD_DRIVER_S  2
161 
162 #define RTC_GPIO_PIN3_REG          (DR_REG_RTCIO_BASE + 0x34)
163 /* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
164 /*description: GPIO wake up enable  only available in light sleep*/
165 #define RTC_GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))
166 #define RTC_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
167 #define RTC_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
168 #define RTC_GPIO_PIN3_WAKEUP_ENABLE_S  10
169 /* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
170 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
171  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
172 #define RTC_GPIO_PIN3_INT_TYPE  0x00000007
173 #define RTC_GPIO_PIN3_INT_TYPE_M  ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S))
174 #define RTC_GPIO_PIN3_INT_TYPE_V  0x7
175 #define RTC_GPIO_PIN3_INT_TYPE_S  7
176 /* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
177 /*description: if set to 0: normal output  if set to 1: open drain*/
178 #define RTC_GPIO_PIN3_PAD_DRIVER  (BIT(2))
179 #define RTC_GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
180 #define RTC_GPIO_PIN3_PAD_DRIVER_V  0x1
181 #define RTC_GPIO_PIN3_PAD_DRIVER_S  2
182 
183 #define RTC_GPIO_PIN4_REG          (DR_REG_RTCIO_BASE + 0x38)
184 /* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
185 /*description: GPIO wake up enable  only available in light sleep*/
186 #define RTC_GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))
187 #define RTC_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
188 #define RTC_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
189 #define RTC_GPIO_PIN4_WAKEUP_ENABLE_S  10
190 /* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
191 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
192  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
193 #define RTC_GPIO_PIN4_INT_TYPE  0x00000007
194 #define RTC_GPIO_PIN4_INT_TYPE_M  ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S))
195 #define RTC_GPIO_PIN4_INT_TYPE_V  0x7
196 #define RTC_GPIO_PIN4_INT_TYPE_S  7
197 /* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
198 /*description: if set to 0: normal output  if set to 1: open drain*/
199 #define RTC_GPIO_PIN4_PAD_DRIVER  (BIT(2))
200 #define RTC_GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
201 #define RTC_GPIO_PIN4_PAD_DRIVER_V  0x1
202 #define RTC_GPIO_PIN4_PAD_DRIVER_S  2
203 
204 #define RTC_GPIO_PIN5_REG          (DR_REG_RTCIO_BASE + 0x3c)
205 /* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
206 /*description: GPIO wake up enable  only available in light sleep*/
207 #define RTC_GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))
208 #define RTC_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
209 #define RTC_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
210 #define RTC_GPIO_PIN5_WAKEUP_ENABLE_S  10
211 /* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
212 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
213  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
214 #define RTC_GPIO_PIN5_INT_TYPE  0x00000007
215 #define RTC_GPIO_PIN5_INT_TYPE_M  ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S))
216 #define RTC_GPIO_PIN5_INT_TYPE_V  0x7
217 #define RTC_GPIO_PIN5_INT_TYPE_S  7
218 /* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
219 /*description: if set to 0: normal output  if set to 1: open drain*/
220 #define RTC_GPIO_PIN5_PAD_DRIVER  (BIT(2))
221 #define RTC_GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
222 #define RTC_GPIO_PIN5_PAD_DRIVER_V  0x1
223 #define RTC_GPIO_PIN5_PAD_DRIVER_S  2
224 
225 #define RTC_GPIO_PIN6_REG          (DR_REG_RTCIO_BASE + 0x40)
226 /* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
227 /*description: GPIO wake up enable  only available in light sleep*/
228 #define RTC_GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))
229 #define RTC_GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
230 #define RTC_GPIO_PIN6_WAKEUP_ENABLE_V  0x1
231 #define RTC_GPIO_PIN6_WAKEUP_ENABLE_S  10
232 /* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
233 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
234  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
235 #define RTC_GPIO_PIN6_INT_TYPE  0x00000007
236 #define RTC_GPIO_PIN6_INT_TYPE_M  ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S))
237 #define RTC_GPIO_PIN6_INT_TYPE_V  0x7
238 #define RTC_GPIO_PIN6_INT_TYPE_S  7
239 /* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
240 /*description: if set to 0: normal output  if set to 1: open drain*/
241 #define RTC_GPIO_PIN6_PAD_DRIVER  (BIT(2))
242 #define RTC_GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
243 #define RTC_GPIO_PIN6_PAD_DRIVER_V  0x1
244 #define RTC_GPIO_PIN6_PAD_DRIVER_S  2
245 
246 #define RTC_GPIO_PIN7_REG          (DR_REG_RTCIO_BASE + 0x44)
247 /* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
248 /*description: GPIO wake up enable  only available in light sleep*/
249 #define RTC_GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))
250 #define RTC_GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
251 #define RTC_GPIO_PIN7_WAKEUP_ENABLE_V  0x1
252 #define RTC_GPIO_PIN7_WAKEUP_ENABLE_S  10
253 /* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
254 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
255  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
256 #define RTC_GPIO_PIN7_INT_TYPE  0x00000007
257 #define RTC_GPIO_PIN7_INT_TYPE_M  ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S))
258 #define RTC_GPIO_PIN7_INT_TYPE_V  0x7
259 #define RTC_GPIO_PIN7_INT_TYPE_S  7
260 /* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
261 /*description: if set to 0: normal output  if set to 1: open drain*/
262 #define RTC_GPIO_PIN7_PAD_DRIVER  (BIT(2))
263 #define RTC_GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
264 #define RTC_GPIO_PIN7_PAD_DRIVER_V  0x1
265 #define RTC_GPIO_PIN7_PAD_DRIVER_S  2
266 
267 #define RTC_GPIO_PIN8_REG          (DR_REG_RTCIO_BASE + 0x48)
268 /* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
269 /*description: GPIO wake up enable  only available in light sleep*/
270 #define RTC_GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))
271 #define RTC_GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
272 #define RTC_GPIO_PIN8_WAKEUP_ENABLE_V  0x1
273 #define RTC_GPIO_PIN8_WAKEUP_ENABLE_S  10
274 /* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
275 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
276  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
277 #define RTC_GPIO_PIN8_INT_TYPE  0x00000007
278 #define RTC_GPIO_PIN8_INT_TYPE_M  ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S))
279 #define RTC_GPIO_PIN8_INT_TYPE_V  0x7
280 #define RTC_GPIO_PIN8_INT_TYPE_S  7
281 /* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
282 /*description: if set to 0: normal output  if set to 1: open drain*/
283 #define RTC_GPIO_PIN8_PAD_DRIVER  (BIT(2))
284 #define RTC_GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
285 #define RTC_GPIO_PIN8_PAD_DRIVER_V  0x1
286 #define RTC_GPIO_PIN8_PAD_DRIVER_S  2
287 
288 #define RTC_GPIO_PIN9_REG          (DR_REG_RTCIO_BASE + 0x4c)
289 /* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
290 /*description: GPIO wake up enable  only available in light sleep*/
291 #define RTC_GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))
292 #define RTC_GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
293 #define RTC_GPIO_PIN9_WAKEUP_ENABLE_V  0x1
294 #define RTC_GPIO_PIN9_WAKEUP_ENABLE_S  10
295 /* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
296 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
297  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
298 #define RTC_GPIO_PIN9_INT_TYPE  0x00000007
299 #define RTC_GPIO_PIN9_INT_TYPE_M  ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S))
300 #define RTC_GPIO_PIN9_INT_TYPE_V  0x7
301 #define RTC_GPIO_PIN9_INT_TYPE_S  7
302 /* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
303 /*description: if set to 0: normal output  if set to 1: open drain*/
304 #define RTC_GPIO_PIN9_PAD_DRIVER  (BIT(2))
305 #define RTC_GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
306 #define RTC_GPIO_PIN9_PAD_DRIVER_V  0x1
307 #define RTC_GPIO_PIN9_PAD_DRIVER_S  2
308 
309 #define RTC_GPIO_PIN10_REG          (DR_REG_RTCIO_BASE + 0x50)
310 /* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
311 /*description: GPIO wake up enable  only available in light sleep*/
312 #define RTC_GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))
313 #define RTC_GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
314 #define RTC_GPIO_PIN10_WAKEUP_ENABLE_V  0x1
315 #define RTC_GPIO_PIN10_WAKEUP_ENABLE_S  10
316 /* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
317 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
318  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
319 #define RTC_GPIO_PIN10_INT_TYPE  0x00000007
320 #define RTC_GPIO_PIN10_INT_TYPE_M  ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S))
321 #define RTC_GPIO_PIN10_INT_TYPE_V  0x7
322 #define RTC_GPIO_PIN10_INT_TYPE_S  7
323 /* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
324 /*description: if set to 0: normal output  if set to 1: open drain*/
325 #define RTC_GPIO_PIN10_PAD_DRIVER  (BIT(2))
326 #define RTC_GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
327 #define RTC_GPIO_PIN10_PAD_DRIVER_V  0x1
328 #define RTC_GPIO_PIN10_PAD_DRIVER_S  2
329 
330 #define RTC_GPIO_PIN11_REG          (DR_REG_RTCIO_BASE + 0x54)
331 /* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
332 /*description: GPIO wake up enable  only available in light sleep*/
333 #define RTC_GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))
334 #define RTC_GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
335 #define RTC_GPIO_PIN11_WAKEUP_ENABLE_V  0x1
336 #define RTC_GPIO_PIN11_WAKEUP_ENABLE_S  10
337 /* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
338 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
339  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
340 #define RTC_GPIO_PIN11_INT_TYPE  0x00000007
341 #define RTC_GPIO_PIN11_INT_TYPE_M  ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S))
342 #define RTC_GPIO_PIN11_INT_TYPE_V  0x7
343 #define RTC_GPIO_PIN11_INT_TYPE_S  7
344 /* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
345 /*description: if set to 0: normal output  if set to 1: open drain*/
346 #define RTC_GPIO_PIN11_PAD_DRIVER  (BIT(2))
347 #define RTC_GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
348 #define RTC_GPIO_PIN11_PAD_DRIVER_V  0x1
349 #define RTC_GPIO_PIN11_PAD_DRIVER_S  2
350 
351 #define RTC_GPIO_PIN12_REG          (DR_REG_RTCIO_BASE + 0x58)
352 /* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
353 /*description: GPIO wake up enable  only available in light sleep*/
354 #define RTC_GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))
355 #define RTC_GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
356 #define RTC_GPIO_PIN12_WAKEUP_ENABLE_V  0x1
357 #define RTC_GPIO_PIN12_WAKEUP_ENABLE_S  10
358 /* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
359 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
360  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
361 #define RTC_GPIO_PIN12_INT_TYPE  0x00000007
362 #define RTC_GPIO_PIN12_INT_TYPE_M  ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S))
363 #define RTC_GPIO_PIN12_INT_TYPE_V  0x7
364 #define RTC_GPIO_PIN12_INT_TYPE_S  7
365 /* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
366 /*description: if set to 0: normal output  if set to 1: open drain*/
367 #define RTC_GPIO_PIN12_PAD_DRIVER  (BIT(2))
368 #define RTC_GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
369 #define RTC_GPIO_PIN12_PAD_DRIVER_V  0x1
370 #define RTC_GPIO_PIN12_PAD_DRIVER_S  2
371 
372 #define RTC_GPIO_PIN13_REG          (DR_REG_RTCIO_BASE + 0x5c)
373 /* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
374 /*description: GPIO wake up enable  only available in light sleep*/
375 #define RTC_GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))
376 #define RTC_GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
377 #define RTC_GPIO_PIN13_WAKEUP_ENABLE_V  0x1
378 #define RTC_GPIO_PIN13_WAKEUP_ENABLE_S  10
379 /* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
380 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
381  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
382 #define RTC_GPIO_PIN13_INT_TYPE  0x00000007
383 #define RTC_GPIO_PIN13_INT_TYPE_M  ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S))
384 #define RTC_GPIO_PIN13_INT_TYPE_V  0x7
385 #define RTC_GPIO_PIN13_INT_TYPE_S  7
386 /* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
387 /*description: if set to 0: normal output  if set to 1: open drain*/
388 #define RTC_GPIO_PIN13_PAD_DRIVER  (BIT(2))
389 #define RTC_GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
390 #define RTC_GPIO_PIN13_PAD_DRIVER_V  0x1
391 #define RTC_GPIO_PIN13_PAD_DRIVER_S  2
392 
393 #define RTC_GPIO_PIN14_REG          (DR_REG_RTCIO_BASE + 0x60)
394 /* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
395 /*description: GPIO wake up enable  only available in light sleep*/
396 #define RTC_GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))
397 #define RTC_GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
398 #define RTC_GPIO_PIN14_WAKEUP_ENABLE_V  0x1
399 #define RTC_GPIO_PIN14_WAKEUP_ENABLE_S  10
400 /* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
401 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
402  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
403 #define RTC_GPIO_PIN14_INT_TYPE  0x00000007
404 #define RTC_GPIO_PIN14_INT_TYPE_M  ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S))
405 #define RTC_GPIO_PIN14_INT_TYPE_V  0x7
406 #define RTC_GPIO_PIN14_INT_TYPE_S  7
407 /* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
408 /*description: if set to 0: normal output  if set to 1: open drain*/
409 #define RTC_GPIO_PIN14_PAD_DRIVER  (BIT(2))
410 #define RTC_GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
411 #define RTC_GPIO_PIN14_PAD_DRIVER_V  0x1
412 #define RTC_GPIO_PIN14_PAD_DRIVER_S  2
413 
414 #define RTC_GPIO_PIN15_REG          (DR_REG_RTCIO_BASE + 0x64)
415 /* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
416 /*description: GPIO wake up enable  only available in light sleep*/
417 #define RTC_GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))
418 #define RTC_GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
419 #define RTC_GPIO_PIN15_WAKEUP_ENABLE_V  0x1
420 #define RTC_GPIO_PIN15_WAKEUP_ENABLE_S  10
421 /* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
422 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
423  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
424 #define RTC_GPIO_PIN15_INT_TYPE  0x00000007
425 #define RTC_GPIO_PIN15_INT_TYPE_M  ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S))
426 #define RTC_GPIO_PIN15_INT_TYPE_V  0x7
427 #define RTC_GPIO_PIN15_INT_TYPE_S  7
428 /* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
429 /*description: if set to 0: normal output  if set to 1: open drain*/
430 #define RTC_GPIO_PIN15_PAD_DRIVER  (BIT(2))
431 #define RTC_GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
432 #define RTC_GPIO_PIN15_PAD_DRIVER_V  0x1
433 #define RTC_GPIO_PIN15_PAD_DRIVER_S  2
434 
435 #define RTC_GPIO_PIN16_REG          (DR_REG_RTCIO_BASE + 0x68)
436 /* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
437 /*description: GPIO wake up enable  only available in light sleep*/
438 #define RTC_GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))
439 #define RTC_GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
440 #define RTC_GPIO_PIN16_WAKEUP_ENABLE_V  0x1
441 #define RTC_GPIO_PIN16_WAKEUP_ENABLE_S  10
442 /* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
443 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
444  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
445 #define RTC_GPIO_PIN16_INT_TYPE  0x00000007
446 #define RTC_GPIO_PIN16_INT_TYPE_M  ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S))
447 #define RTC_GPIO_PIN16_INT_TYPE_V  0x7
448 #define RTC_GPIO_PIN16_INT_TYPE_S  7
449 /* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
450 /*description: if set to 0: normal output  if set to 1: open drain*/
451 #define RTC_GPIO_PIN16_PAD_DRIVER  (BIT(2))
452 #define RTC_GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
453 #define RTC_GPIO_PIN16_PAD_DRIVER_V  0x1
454 #define RTC_GPIO_PIN16_PAD_DRIVER_S  2
455 
456 #define RTC_GPIO_PIN17_REG          (DR_REG_RTCIO_BASE + 0x6c)
457 /* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
458 /*description: GPIO wake up enable  only available in light sleep*/
459 #define RTC_GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))
460 #define RTC_GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
461 #define RTC_GPIO_PIN17_WAKEUP_ENABLE_V  0x1
462 #define RTC_GPIO_PIN17_WAKEUP_ENABLE_S  10
463 /* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
464 /*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
465  trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
466 #define RTC_GPIO_PIN17_INT_TYPE  0x00000007
467 #define RTC_GPIO_PIN17_INT_TYPE_M  ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S))
468 #define RTC_GPIO_PIN17_INT_TYPE_V  0x7
469 #define RTC_GPIO_PIN17_INT_TYPE_S  7
470 /* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
471 /*description: if set to 0: normal output  if set to 1: open drain*/
472 #define RTC_GPIO_PIN17_PAD_DRIVER  (BIT(2))
473 #define RTC_GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
474 #define RTC_GPIO_PIN17_PAD_DRIVER_V  0x1
475 #define RTC_GPIO_PIN17_PAD_DRIVER_S  2
476 
477 #define RTC_IO_RTC_DEBUG_SEL_REG          (DR_REG_RTCIO_BASE + 0x70)
478 /* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */
479 /*description: */
480 #define RTC_IO_DEBUG_12M_NO_GATING  (BIT(25))
481 #define RTC_IO_DEBUG_12M_NO_GATING_M  (BIT(25))
482 #define RTC_IO_DEBUG_12M_NO_GATING_V  0x1
483 #define RTC_IO_DEBUG_12M_NO_GATING_S  25
484 /* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */
485 /*description: */
486 #define RTC_IO_DEBUG_SEL4  0x0000001F
487 #define RTC_IO_DEBUG_SEL4_M  ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S))
488 #define RTC_IO_DEBUG_SEL4_V  0x1F
489 #define RTC_IO_DEBUG_SEL4_S  20
490 /* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */
491 /*description: */
492 #define RTC_IO_DEBUG_SEL3  0x0000001F
493 #define RTC_IO_DEBUG_SEL3_M  ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S))
494 #define RTC_IO_DEBUG_SEL3_V  0x1F
495 #define RTC_IO_DEBUG_SEL3_S  15
496 /* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */
497 /*description: */
498 #define RTC_IO_DEBUG_SEL2  0x0000001F
499 #define RTC_IO_DEBUG_SEL2_M  ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S))
500 #define RTC_IO_DEBUG_SEL2_V  0x1F
501 #define RTC_IO_DEBUG_SEL2_S  10
502 /* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */
503 /*description: */
504 #define RTC_IO_DEBUG_SEL1  0x0000001F
505 #define RTC_IO_DEBUG_SEL1_M  ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S))
506 #define RTC_IO_DEBUG_SEL1_V  0x1F
507 #define RTC_IO_DEBUG_SEL1_S  5
508 /* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
509 /*description: */
510 #define RTC_IO_DEBUG_SEL0  0x0000001F
511 #define RTC_IO_DEBUG_SEL0_M  ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S))
512 #define RTC_IO_DEBUG_SEL0_V  0x1F
513 #define RTC_IO_DEBUG_SEL0_S  0
514 #define RTC_IO_DEBUG_SEL0_8M       1
515 #define RTC_IO_DEBUG_SEL0_32K_XTAL 4
516 #define RTC_IO_DEBUG_SEL0_150K_OSC 5
517 
518 #define RTC_IO_DIG_PAD_HOLD_REG          (DR_REG_RTCIO_BASE + 0x74)
519 /* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */
520 /*description: select the digital pad hold value.*/
521 #define RTC_IO_DIG_PAD_HOLD  0xFFFFFFFF
522 #define RTC_IO_DIG_PAD_HOLD_M  ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S))
523 #define RTC_IO_DIG_PAD_HOLD_V  0xFFFFFFFF
524 #define RTC_IO_DIG_PAD_HOLD_S  0
525 
526 #define RTC_IO_HALL_SENS_REG          (DR_REG_RTCIO_BASE + 0x78)
527 /* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */
528 /*description: Power on hall sensor and connect to VP and VN*/
529 #define RTC_IO_XPD_HALL  (BIT(31))
530 #define RTC_IO_XPD_HALL_M  (BIT(31))
531 #define RTC_IO_XPD_HALL_V  0x1
532 #define RTC_IO_XPD_HALL_S  31
533 /* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */
534 /*description: Reverse phase of hall sensor*/
535 #define RTC_IO_HALL_PHASE  (BIT(30))
536 #define RTC_IO_HALL_PHASE_M  (BIT(30))
537 #define RTC_IO_HALL_PHASE_V  0x1
538 #define RTC_IO_HALL_PHASE_S  30
539 
540 #define RTC_IO_SENSOR_PADS_REG          (DR_REG_RTCIO_BASE + 0x7c)
541 /* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
542 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
543 #define RTC_IO_SENSE1_HOLD  (BIT(31))
544 #define RTC_IO_SENSE1_HOLD_M  (BIT(31))
545 #define RTC_IO_SENSE1_HOLD_V  0x1
546 #define RTC_IO_SENSE1_HOLD_S  31
547 /* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */
548 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
549 #define RTC_IO_SENSE2_HOLD  (BIT(30))
550 #define RTC_IO_SENSE2_HOLD_M  (BIT(30))
551 #define RTC_IO_SENSE2_HOLD_V  0x1
552 #define RTC_IO_SENSE2_HOLD_S  30
553 /* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
554 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
555 #define RTC_IO_SENSE3_HOLD  (BIT(29))
556 #define RTC_IO_SENSE3_HOLD_M  (BIT(29))
557 #define RTC_IO_SENSE3_HOLD_V  0x1
558 #define RTC_IO_SENSE3_HOLD_S  29
559 /* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */
560 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
561 #define RTC_IO_SENSE4_HOLD  (BIT(28))
562 #define RTC_IO_SENSE4_HOLD_M  (BIT(28))
563 #define RTC_IO_SENSE4_HOLD_V  0x1
564 #define RTC_IO_SENSE4_HOLD_S  28
565 /* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */
566 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
567 #define RTC_IO_SENSE1_MUX_SEL  (BIT(27))
568 #define RTC_IO_SENSE1_MUX_SEL_M  (BIT(27))
569 #define RTC_IO_SENSE1_MUX_SEL_V  0x1
570 #define RTC_IO_SENSE1_MUX_SEL_S  27
571 /* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */
572 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
573 #define RTC_IO_SENSE2_MUX_SEL  (BIT(26))
574 #define RTC_IO_SENSE2_MUX_SEL_M  (BIT(26))
575 #define RTC_IO_SENSE2_MUX_SEL_V  0x1
576 #define RTC_IO_SENSE2_MUX_SEL_S  26
577 /* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */
578 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
579 #define RTC_IO_SENSE3_MUX_SEL  (BIT(25))
580 #define RTC_IO_SENSE3_MUX_SEL_M  (BIT(25))
581 #define RTC_IO_SENSE3_MUX_SEL_V  0x1
582 #define RTC_IO_SENSE3_MUX_SEL_S  25
583 /* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */
584 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
585 #define RTC_IO_SENSE4_MUX_SEL  (BIT(24))
586 #define RTC_IO_SENSE4_MUX_SEL_M  (BIT(24))
587 #define RTC_IO_SENSE4_MUX_SEL_V  0x1
588 #define RTC_IO_SENSE4_MUX_SEL_S  24
589 /* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
590 /*description: the functional selection signal of the pad*/
591 #define RTC_IO_SENSE1_FUN_SEL  0x00000003
592 #define RTC_IO_SENSE1_FUN_SEL_M  ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S))
593 #define RTC_IO_SENSE1_FUN_SEL_V  0x3
594 #define RTC_IO_SENSE1_FUN_SEL_S  22
595 /* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */
596 /*description: the sleep status selection signal of the pad*/
597 #define RTC_IO_SENSE1_SLP_SEL  (BIT(21))
598 #define RTC_IO_SENSE1_SLP_SEL_M  (BIT(21))
599 #define RTC_IO_SENSE1_SLP_SEL_V  0x1
600 #define RTC_IO_SENSE1_SLP_SEL_S  21
601 /* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */
602 /*description: the input enable of the pad in sleep status*/
603 #define RTC_IO_SENSE1_SLP_IE  (BIT(20))
604 #define RTC_IO_SENSE1_SLP_IE_M  (BIT(20))
605 #define RTC_IO_SENSE1_SLP_IE_V  0x1
606 #define RTC_IO_SENSE1_SLP_IE_S  20
607 /* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */
608 /*description: the input enable of the pad*/
609 #define RTC_IO_SENSE1_FUN_IE  (BIT(19))
610 #define RTC_IO_SENSE1_FUN_IE_M  (BIT(19))
611 #define RTC_IO_SENSE1_FUN_IE_V  0x1
612 #define RTC_IO_SENSE1_FUN_IE_S  19
613 /* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
614 /*description: the functional selection signal of the pad*/
615 #define RTC_IO_SENSE2_FUN_SEL  0x00000003
616 #define RTC_IO_SENSE2_FUN_SEL_M  ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S))
617 #define RTC_IO_SENSE2_FUN_SEL_V  0x3
618 #define RTC_IO_SENSE2_FUN_SEL_S  17
619 /* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
620 /*description: the sleep status selection signal of the pad*/
621 #define RTC_IO_SENSE2_SLP_SEL  (BIT(16))
622 #define RTC_IO_SENSE2_SLP_SEL_M  (BIT(16))
623 #define RTC_IO_SENSE2_SLP_SEL_V  0x1
624 #define RTC_IO_SENSE2_SLP_SEL_S  16
625 /* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
626 /*description: the input enable of the pad in sleep status*/
627 #define RTC_IO_SENSE2_SLP_IE  (BIT(15))
628 #define RTC_IO_SENSE2_SLP_IE_M  (BIT(15))
629 #define RTC_IO_SENSE2_SLP_IE_V  0x1
630 #define RTC_IO_SENSE2_SLP_IE_S  15
631 /* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */
632 /*description: the input enable of the pad*/
633 #define RTC_IO_SENSE2_FUN_IE  (BIT(14))
634 #define RTC_IO_SENSE2_FUN_IE_M  (BIT(14))
635 #define RTC_IO_SENSE2_FUN_IE_V  0x1
636 #define RTC_IO_SENSE2_FUN_IE_S  14
637 /* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
638 /*description: the functional selection signal of the pad*/
639 #define RTC_IO_SENSE3_FUN_SEL  0x00000003
640 #define RTC_IO_SENSE3_FUN_SEL_M  ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S))
641 #define RTC_IO_SENSE3_FUN_SEL_V  0x3
642 #define RTC_IO_SENSE3_FUN_SEL_S  12
643 /* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
644 /*description: the sleep status selection signal of the pad*/
645 #define RTC_IO_SENSE3_SLP_SEL  (BIT(11))
646 #define RTC_IO_SENSE3_SLP_SEL_M  (BIT(11))
647 #define RTC_IO_SENSE3_SLP_SEL_V  0x1
648 #define RTC_IO_SENSE3_SLP_SEL_S  11
649 /* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */
650 /*description: the input enable of the pad in sleep status*/
651 #define RTC_IO_SENSE3_SLP_IE  (BIT(10))
652 #define RTC_IO_SENSE3_SLP_IE_M  (BIT(10))
653 #define RTC_IO_SENSE3_SLP_IE_V  0x1
654 #define RTC_IO_SENSE3_SLP_IE_S  10
655 /* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */
656 /*description: the input enable of the pad*/
657 #define RTC_IO_SENSE3_FUN_IE  (BIT(9))
658 #define RTC_IO_SENSE3_FUN_IE_M  (BIT(9))
659 #define RTC_IO_SENSE3_FUN_IE_V  0x1
660 #define RTC_IO_SENSE3_FUN_IE_S  9
661 /* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */
662 /*description: the functional selection signal of the pad*/
663 #define RTC_IO_SENSE4_FUN_SEL  0x00000003
664 #define RTC_IO_SENSE4_FUN_SEL_M  ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S))
665 #define RTC_IO_SENSE4_FUN_SEL_V  0x3
666 #define RTC_IO_SENSE4_FUN_SEL_S  7
667 /* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */
668 /*description: the sleep status selection signal of the pad*/
669 #define RTC_IO_SENSE4_SLP_SEL  (BIT(6))
670 #define RTC_IO_SENSE4_SLP_SEL_M  (BIT(6))
671 #define RTC_IO_SENSE4_SLP_SEL_V  0x1
672 #define RTC_IO_SENSE4_SLP_SEL_S  6
673 /* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
674 /*description: the input enable of the pad in sleep status*/
675 #define RTC_IO_SENSE4_SLP_IE  (BIT(5))
676 #define RTC_IO_SENSE4_SLP_IE_M  (BIT(5))
677 #define RTC_IO_SENSE4_SLP_IE_V  0x1
678 #define RTC_IO_SENSE4_SLP_IE_S  5
679 /* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */
680 /*description: the input enable of the pad*/
681 #define RTC_IO_SENSE4_FUN_IE  (BIT(4))
682 #define RTC_IO_SENSE4_FUN_IE_M  (BIT(4))
683 #define RTC_IO_SENSE4_FUN_IE_V  0x1
684 #define RTC_IO_SENSE4_FUN_IE_S  4
685 
686 #define RTC_IO_ADC_PAD_REG          (DR_REG_RTCIO_BASE + 0x80)
687 /* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
688 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
689 #define RTC_IO_ADC1_HOLD  (BIT(31))
690 #define RTC_IO_ADC1_HOLD_M  (BIT(31))
691 #define RTC_IO_ADC1_HOLD_V  0x1
692 #define RTC_IO_ADC1_HOLD_S  31
693 /* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */
694 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
695 #define RTC_IO_ADC2_HOLD  (BIT(30))
696 #define RTC_IO_ADC2_HOLD_M  (BIT(30))
697 #define RTC_IO_ADC2_HOLD_V  0x1
698 #define RTC_IO_ADC2_HOLD_S  30
699 /* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */
700 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
701 #define RTC_IO_ADC1_MUX_SEL  (BIT(29))
702 #define RTC_IO_ADC1_MUX_SEL_M  (BIT(29))
703 #define RTC_IO_ADC1_MUX_SEL_V  0x1
704 #define RTC_IO_ADC1_MUX_SEL_S  29
705 /* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */
706 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
707 #define RTC_IO_ADC2_MUX_SEL  (BIT(28))
708 #define RTC_IO_ADC2_MUX_SEL_M  (BIT(28))
709 #define RTC_IO_ADC2_MUX_SEL_V  0x1
710 #define RTC_IO_ADC2_MUX_SEL_S  28
711 /* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
712 /*description: the functional selection signal of the pad*/
713 #define RTC_IO_ADC1_FUN_SEL  0x00000003
714 #define RTC_IO_ADC1_FUN_SEL_M  ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S))
715 #define RTC_IO_ADC1_FUN_SEL_V  0x3
716 #define RTC_IO_ADC1_FUN_SEL_S  26
717 /* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */
718 /*description: the sleep status selection signal of the pad*/
719 #define RTC_IO_ADC1_SLP_SEL  (BIT(25))
720 #define RTC_IO_ADC1_SLP_SEL_M  (BIT(25))
721 #define RTC_IO_ADC1_SLP_SEL_V  0x1
722 #define RTC_IO_ADC1_SLP_SEL_S  25
723 /* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */
724 /*description: the input enable of the pad in sleep status*/
725 #define RTC_IO_ADC1_SLP_IE  (BIT(24))
726 #define RTC_IO_ADC1_SLP_IE_M  (BIT(24))
727 #define RTC_IO_ADC1_SLP_IE_V  0x1
728 #define RTC_IO_ADC1_SLP_IE_S  24
729 /* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */
730 /*description: the input enable of the pad*/
731 #define RTC_IO_ADC1_FUN_IE  (BIT(23))
732 #define RTC_IO_ADC1_FUN_IE_M  (BIT(23))
733 #define RTC_IO_ADC1_FUN_IE_V  0x1
734 #define RTC_IO_ADC1_FUN_IE_S  23
735 /* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */
736 /*description: the functional selection signal of the pad*/
737 #define RTC_IO_ADC2_FUN_SEL  0x00000003
738 #define RTC_IO_ADC2_FUN_SEL_M  ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S))
739 #define RTC_IO_ADC2_FUN_SEL_V  0x3
740 #define RTC_IO_ADC2_FUN_SEL_S  21
741 /* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */
742 /*description: the sleep status selection signal of the pad*/
743 #define RTC_IO_ADC2_SLP_SEL  (BIT(20))
744 #define RTC_IO_ADC2_SLP_SEL_M  (BIT(20))
745 #define RTC_IO_ADC2_SLP_SEL_V  0x1
746 #define RTC_IO_ADC2_SLP_SEL_S  20
747 /* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */
748 /*description: the input enable of the pad in sleep status*/
749 #define RTC_IO_ADC2_SLP_IE  (BIT(19))
750 #define RTC_IO_ADC2_SLP_IE_M  (BIT(19))
751 #define RTC_IO_ADC2_SLP_IE_V  0x1
752 #define RTC_IO_ADC2_SLP_IE_S  19
753 /* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */
754 /*description: the input enable of the pad*/
755 #define RTC_IO_ADC2_FUN_IE  (BIT(18))
756 #define RTC_IO_ADC2_FUN_IE_M  (BIT(18))
757 #define RTC_IO_ADC2_FUN_IE_V  0x1
758 #define RTC_IO_ADC2_FUN_IE_S  18
759 
760 #define RTC_IO_PAD_DAC1_REG          (DR_REG_RTCIO_BASE + 0x84)
761 /* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
762 /*description: the driver strength of the pad*/
763 #define RTC_IO_PDAC1_DRV  0x00000003
764 #define RTC_IO_PDAC1_DRV_M  ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S))
765 #define RTC_IO_PDAC1_DRV_V  0x3
766 #define RTC_IO_PDAC1_DRV_S  30
767 /* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
768 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
769 #define RTC_IO_PDAC1_HOLD  (BIT(29))
770 #define RTC_IO_PDAC1_HOLD_M  (BIT(29))
771 #define RTC_IO_PDAC1_HOLD_V  0x1
772 #define RTC_IO_PDAC1_HOLD_S  29
773 /* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
774 /*description: the pull down enable of the pad*/
775 #define RTC_IO_PDAC1_RDE  (BIT(28))
776 #define RTC_IO_PDAC1_RDE_M  (BIT(28))
777 #define RTC_IO_PDAC1_RDE_V  0x1
778 #define RTC_IO_PDAC1_RDE_S  28
779 /* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
780 /*description: the pull up enable of the pad*/
781 #define RTC_IO_PDAC1_RUE  (BIT(27))
782 #define RTC_IO_PDAC1_RUE_M  (BIT(27))
783 #define RTC_IO_PDAC1_RUE_V  0x1
784 #define RTC_IO_PDAC1_RUE_S  27
785 /* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
786 /*description: PAD DAC1 control code.*/
787 #define RTC_IO_PDAC1_DAC  0x000000FF
788 #define RTC_IO_PDAC1_DAC_M  ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S))
789 #define RTC_IO_PDAC1_DAC_V  0xFF
790 #define RTC_IO_PDAC1_DAC_S  19
791 /* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
792 /*description: Power on DAC1. Usually  we need to tristate PDAC1 if we power
793  on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
794 #define RTC_IO_PDAC1_XPD_DAC  (BIT(18))
795 #define RTC_IO_PDAC1_XPD_DAC_M  (BIT(18))
796 #define RTC_IO_PDAC1_XPD_DAC_V  0x1
797 #define RTC_IO_PDAC1_XPD_DAC_S  18
798 /* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
799 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
800 #define RTC_IO_PDAC1_MUX_SEL  (BIT(17))
801 #define RTC_IO_PDAC1_MUX_SEL_M  (BIT(17))
802 #define RTC_IO_PDAC1_MUX_SEL_V  0x1
803 #define RTC_IO_PDAC1_MUX_SEL_S  17
804 /* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
805 /*description: the functional selection signal of the pad*/
806 #define RTC_IO_PDAC1_FUN_SEL  0x00000003
807 #define RTC_IO_PDAC1_FUN_SEL_M  ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S))
808 #define RTC_IO_PDAC1_FUN_SEL_V  0x3
809 #define RTC_IO_PDAC1_FUN_SEL_S  15
810 /* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
811 /*description: the sleep status selection signal of the pad*/
812 #define RTC_IO_PDAC1_SLP_SEL  (BIT(14))
813 #define RTC_IO_PDAC1_SLP_SEL_M  (BIT(14))
814 #define RTC_IO_PDAC1_SLP_SEL_V  0x1
815 #define RTC_IO_PDAC1_SLP_SEL_S  14
816 /* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
817 /*description: the input enable of the pad in sleep status*/
818 #define RTC_IO_PDAC1_SLP_IE  (BIT(13))
819 #define RTC_IO_PDAC1_SLP_IE_M  (BIT(13))
820 #define RTC_IO_PDAC1_SLP_IE_V  0x1
821 #define RTC_IO_PDAC1_SLP_IE_S  13
822 /* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
823 /*description: the output enable of the pad in sleep status*/
824 #define RTC_IO_PDAC1_SLP_OE  (BIT(12))
825 #define RTC_IO_PDAC1_SLP_OE_M  (BIT(12))
826 #define RTC_IO_PDAC1_SLP_OE_V  0x1
827 #define RTC_IO_PDAC1_SLP_OE_S  12
828 /* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
829 /*description: the input enable of the pad*/
830 #define RTC_IO_PDAC1_FUN_IE  (BIT(11))
831 #define RTC_IO_PDAC1_FUN_IE_M  (BIT(11))
832 #define RTC_IO_PDAC1_FUN_IE_V  0x1
833 #define RTC_IO_PDAC1_FUN_IE_S  11
834 /* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
835 /*description: Power on DAC1. Usually  we need to tristate PDAC1 if we power
836  on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
837 #define RTC_IO_PDAC1_DAC_XPD_FORCE  (BIT(10))
838 #define RTC_IO_PDAC1_DAC_XPD_FORCE_M  (BIT(10))
839 #define RTC_IO_PDAC1_DAC_XPD_FORCE_V  0x1
840 #define RTC_IO_PDAC1_DAC_XPD_FORCE_S  10
841 
842 #define RTC_IO_PAD_DAC2_REG          (DR_REG_RTCIO_BASE + 0x88)
843 /* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
844 /*description: the driver strength of the pad*/
845 #define RTC_IO_PDAC2_DRV  0x00000003
846 #define RTC_IO_PDAC2_DRV_M  ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S))
847 #define RTC_IO_PDAC2_DRV_V  0x3
848 #define RTC_IO_PDAC2_DRV_S  30
849 /* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
850 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
851 #define RTC_IO_PDAC2_HOLD  (BIT(29))
852 #define RTC_IO_PDAC2_HOLD_M  (BIT(29))
853 #define RTC_IO_PDAC2_HOLD_V  0x1
854 #define RTC_IO_PDAC2_HOLD_S  29
855 /* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
856 /*description: the pull down enable of the pad*/
857 #define RTC_IO_PDAC2_RDE  (BIT(28))
858 #define RTC_IO_PDAC2_RDE_M  (BIT(28))
859 #define RTC_IO_PDAC2_RDE_V  0x1
860 #define RTC_IO_PDAC2_RDE_S  28
861 /* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
862 /*description: the pull up enable of the pad*/
863 #define RTC_IO_PDAC2_RUE  (BIT(27))
864 #define RTC_IO_PDAC2_RUE_M  (BIT(27))
865 #define RTC_IO_PDAC2_RUE_V  0x1
866 #define RTC_IO_PDAC2_RUE_S  27
867 /* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
868 /*description: PAD DAC2 control code.*/
869 #define RTC_IO_PDAC2_DAC  0x000000FF
870 #define RTC_IO_PDAC2_DAC_M  ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S))
871 #define RTC_IO_PDAC2_DAC_V  0xFF
872 #define RTC_IO_PDAC2_DAC_S  19
873 /* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
874 /*description: Power on DAC2. Usually  we need to tristate PDAC1 if we power
875  on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
876 #define RTC_IO_PDAC2_XPD_DAC  (BIT(18))
877 #define RTC_IO_PDAC2_XPD_DAC_M  (BIT(18))
878 #define RTC_IO_PDAC2_XPD_DAC_V  0x1
879 #define RTC_IO_PDAC2_XPD_DAC_S  18
880 /* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
881 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
882 #define RTC_IO_PDAC2_MUX_SEL  (BIT(17))
883 #define RTC_IO_PDAC2_MUX_SEL_M  (BIT(17))
884 #define RTC_IO_PDAC2_MUX_SEL_V  0x1
885 #define RTC_IO_PDAC2_MUX_SEL_S  17
886 /* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
887 /*description: the functional selection signal of the pad*/
888 #define RTC_IO_PDAC2_FUN_SEL  0x00000003
889 #define RTC_IO_PDAC2_FUN_SEL_M  ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S))
890 #define RTC_IO_PDAC2_FUN_SEL_V  0x3
891 #define RTC_IO_PDAC2_FUN_SEL_S  15
892 /* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
893 /*description: the sleep status selection signal of the pad*/
894 #define RTC_IO_PDAC2_SLP_SEL  (BIT(14))
895 #define RTC_IO_PDAC2_SLP_SEL_M  (BIT(14))
896 #define RTC_IO_PDAC2_SLP_SEL_V  0x1
897 #define RTC_IO_PDAC2_SLP_SEL_S  14
898 /* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
899 /*description: the input enable of the pad in sleep status*/
900 #define RTC_IO_PDAC2_SLP_IE  (BIT(13))
901 #define RTC_IO_PDAC2_SLP_IE_M  (BIT(13))
902 #define RTC_IO_PDAC2_SLP_IE_V  0x1
903 #define RTC_IO_PDAC2_SLP_IE_S  13
904 /* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
905 /*description: the output enable of the pad in sleep status*/
906 #define RTC_IO_PDAC2_SLP_OE  (BIT(12))
907 #define RTC_IO_PDAC2_SLP_OE_M  (BIT(12))
908 #define RTC_IO_PDAC2_SLP_OE_V  0x1
909 #define RTC_IO_PDAC2_SLP_OE_S  12
910 /* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
911 /*description: the input enable of the pad*/
912 #define RTC_IO_PDAC2_FUN_IE  (BIT(11))
913 #define RTC_IO_PDAC2_FUN_IE_M  (BIT(11))
914 #define RTC_IO_PDAC2_FUN_IE_V  0x1
915 #define RTC_IO_PDAC2_FUN_IE_S  11
916 /* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
917 /*description: Power on DAC2. Usually  we need to tristate PDAC2 if we power
918  on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
919 #define RTC_IO_PDAC2_DAC_XPD_FORCE  (BIT(10))
920 #define RTC_IO_PDAC2_DAC_XPD_FORCE_M  (BIT(10))
921 #define RTC_IO_PDAC2_DAC_XPD_FORCE_V  0x1
922 #define RTC_IO_PDAC2_DAC_XPD_FORCE_S  10
923 
924 #define RTC_IO_XTAL_32K_PAD_REG          (DR_REG_RTCIO_BASE + 0x8c)
925 /* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
926 /*description: the driver strength of the pad*/
927 #define RTC_IO_X32N_DRV  0x00000003
928 #define RTC_IO_X32N_DRV_M  ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S))
929 #define RTC_IO_X32N_DRV_V  0x3
930 #define RTC_IO_X32N_DRV_S  30
931 /* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
932 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
933 #define RTC_IO_X32N_HOLD  (BIT(29))
934 #define RTC_IO_X32N_HOLD_M  (BIT(29))
935 #define RTC_IO_X32N_HOLD_V  0x1
936 #define RTC_IO_X32N_HOLD_S  29
937 /* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
938 /*description: the pull down enable of the pad*/
939 #define RTC_IO_X32N_RDE  (BIT(28))
940 #define RTC_IO_X32N_RDE_M  (BIT(28))
941 #define RTC_IO_X32N_RDE_V  0x1
942 #define RTC_IO_X32N_RDE_S  28
943 /* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
944 /*description: the pull up enable of the pad*/
945 #define RTC_IO_X32N_RUE  (BIT(27))
946 #define RTC_IO_X32N_RUE_M  (BIT(27))
947 #define RTC_IO_X32N_RUE_V  0x1
948 #define RTC_IO_X32N_RUE_S  27
949 /* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */
950 /*description: the driver strength of the pad*/
951 #define RTC_IO_X32P_DRV  0x00000003
952 #define RTC_IO_X32P_DRV_M  ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S))
953 #define RTC_IO_X32P_DRV_V  0x3
954 #define RTC_IO_X32P_DRV_S  25
955 /* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */
956 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
957 #define RTC_IO_X32P_HOLD  (BIT(24))
958 #define RTC_IO_X32P_HOLD_M  (BIT(24))
959 #define RTC_IO_X32P_HOLD_V  0x1
960 #define RTC_IO_X32P_HOLD_S  24
961 /* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */
962 /*description: the pull down enable of the pad*/
963 #define RTC_IO_X32P_RDE  (BIT(23))
964 #define RTC_IO_X32P_RDE_M  (BIT(23))
965 #define RTC_IO_X32P_RDE_V  0x1
966 #define RTC_IO_X32P_RDE_S  23
967 /* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */
968 /*description: the pull up enable of the pad*/
969 #define RTC_IO_X32P_RUE  (BIT(22))
970 #define RTC_IO_X32P_RUE_M  (BIT(22))
971 #define RTC_IO_X32P_RUE_V  0x1
972 #define RTC_IO_X32P_RUE_S  22
973 /* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */
974 /*description: 32K XTAL bias current DAC.*/
975 #define RTC_IO_DAC_XTAL_32K  0x00000003
976 #define RTC_IO_DAC_XTAL_32K_M  ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S))
977 #define RTC_IO_DAC_XTAL_32K_V  0x3
978 #define RTC_IO_DAC_XTAL_32K_S  20
979 /* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */
980 /*description: Power up 32kHz crystal oscillator*/
981 #define RTC_IO_XPD_XTAL_32K  (BIT(19))
982 #define RTC_IO_XPD_XTAL_32K_M  (BIT(19))
983 #define RTC_IO_XPD_XTAL_32K_V  0x1
984 #define RTC_IO_XPD_XTAL_32K_S  19
985 /* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */
986 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
987 #define RTC_IO_X32N_MUX_SEL  (BIT(18))
988 #define RTC_IO_X32N_MUX_SEL_M  (BIT(18))
989 #define RTC_IO_X32N_MUX_SEL_V  0x1
990 #define RTC_IO_X32N_MUX_SEL_S  18
991 /* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
992 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
993 #define RTC_IO_X32P_MUX_SEL  (BIT(17))
994 #define RTC_IO_X32P_MUX_SEL_M  (BIT(17))
995 #define RTC_IO_X32P_MUX_SEL_V  0x1
996 #define RTC_IO_X32P_MUX_SEL_S  17
997 /* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
998 /*description: the functional selection signal of the pad*/
999 #define RTC_IO_X32N_FUN_SEL  0x00000003
1000 #define RTC_IO_X32N_FUN_SEL_M  ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S))
1001 #define RTC_IO_X32N_FUN_SEL_V  0x3
1002 #define RTC_IO_X32N_FUN_SEL_S  15
1003 /* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
1004 /*description: the sleep status selection signal of the pad*/
1005 #define RTC_IO_X32N_SLP_SEL  (BIT(14))
1006 #define RTC_IO_X32N_SLP_SEL_M  (BIT(14))
1007 #define RTC_IO_X32N_SLP_SEL_V  0x1
1008 #define RTC_IO_X32N_SLP_SEL_S  14
1009 /* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
1010 /*description: the input enable of the pad in sleep status*/
1011 #define RTC_IO_X32N_SLP_IE  (BIT(13))
1012 #define RTC_IO_X32N_SLP_IE_M  (BIT(13))
1013 #define RTC_IO_X32N_SLP_IE_V  0x1
1014 #define RTC_IO_X32N_SLP_IE_S  13
1015 /* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
1016 /*description: the output enable of the pad in sleep status*/
1017 #define RTC_IO_X32N_SLP_OE  (BIT(12))
1018 #define RTC_IO_X32N_SLP_OE_M  (BIT(12))
1019 #define RTC_IO_X32N_SLP_OE_V  0x1
1020 #define RTC_IO_X32N_SLP_OE_S  12
1021 /* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
1022 /*description: the input enable of the pad*/
1023 #define RTC_IO_X32N_FUN_IE  (BIT(11))
1024 #define RTC_IO_X32N_FUN_IE_M  (BIT(11))
1025 #define RTC_IO_X32N_FUN_IE_V  0x1
1026 #define RTC_IO_X32N_FUN_IE_S  11
1027 /* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */
1028 /*description: the functional selection signal of the pad*/
1029 #define RTC_IO_X32P_FUN_SEL  0x00000003
1030 #define RTC_IO_X32P_FUN_SEL_M  ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S))
1031 #define RTC_IO_X32P_FUN_SEL_V  0x3
1032 #define RTC_IO_X32P_FUN_SEL_S  9
1033 /* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */
1034 /*description: the sleep status selection signal of the pad*/
1035 #define RTC_IO_X32P_SLP_SEL  (BIT(8))
1036 #define RTC_IO_X32P_SLP_SEL_M  (BIT(8))
1037 #define RTC_IO_X32P_SLP_SEL_V  0x1
1038 #define RTC_IO_X32P_SLP_SEL_S  8
1039 /* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */
1040 /*description: the input enable of the pad in sleep status*/
1041 #define RTC_IO_X32P_SLP_IE  (BIT(7))
1042 #define RTC_IO_X32P_SLP_IE_M  (BIT(7))
1043 #define RTC_IO_X32P_SLP_IE_V  0x1
1044 #define RTC_IO_X32P_SLP_IE_S  7
1045 /* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */
1046 /*description: the output enable of the pad in sleep status*/
1047 #define RTC_IO_X32P_SLP_OE  (BIT(6))
1048 #define RTC_IO_X32P_SLP_OE_M  (BIT(6))
1049 #define RTC_IO_X32P_SLP_OE_V  0x1
1050 #define RTC_IO_X32P_SLP_OE_S  6
1051 /* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
1052 /*description: the input enable of the pad*/
1053 #define RTC_IO_X32P_FUN_IE  (BIT(5))
1054 #define RTC_IO_X32P_FUN_IE_M  (BIT(5))
1055 #define RTC_IO_X32P_FUN_IE_V  0x1
1056 #define RTC_IO_X32P_FUN_IE_S  5
1057 /* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */
1058 /*description: 32K XTAL resistor bias control.*/
1059 #define RTC_IO_DRES_XTAL_32K  0x00000003
1060 #define RTC_IO_DRES_XTAL_32K_M  ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S))
1061 #define RTC_IO_DRES_XTAL_32K_V  0x3
1062 #define RTC_IO_DRES_XTAL_32K_S  3
1063 /* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */
1064 /*description: 32K XTAL self-bias reference control.*/
1065 #define RTC_IO_DBIAS_XTAL_32K  0x00000003
1066 #define RTC_IO_DBIAS_XTAL_32K_M  ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S))
1067 #define RTC_IO_DBIAS_XTAL_32K_V  0x3
1068 #define RTC_IO_DBIAS_XTAL_32K_S  1
1069 
1070 #define RTC_IO_TOUCH_CFG_REG          (DR_REG_RTCIO_BASE + 0x90)
1071 /* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */
1072 /*description: touch sensor bias power on.*/
1073 #define RTC_IO_TOUCH_XPD_BIAS  (BIT(31))
1074 #define RTC_IO_TOUCH_XPD_BIAS_M  (BIT(31))
1075 #define RTC_IO_TOUCH_XPD_BIAS_V  0x1
1076 #define RTC_IO_TOUCH_XPD_BIAS_S  31
1077 /* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */
1078 /*description: touch sensor saw wave top voltage.*/
1079 #define RTC_IO_TOUCH_DREFH  0x00000003
1080 #define RTC_IO_TOUCH_DREFH_M  ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S))
1081 #define RTC_IO_TOUCH_DREFH_V  0x3
1082 #define RTC_IO_TOUCH_DREFH_S  29
1083 /* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */
1084 /*description: touch sensor saw wave bottom voltage.*/
1085 #define RTC_IO_TOUCH_DREFL  0x00000003
1086 #define RTC_IO_TOUCH_DREFL_M  ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S))
1087 #define RTC_IO_TOUCH_DREFL_V  0x3
1088 #define RTC_IO_TOUCH_DREFL_S  27
1089 /* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */
1090 /*description: touch sensor saw wave voltage range.*/
1091 #define RTC_IO_TOUCH_DRANGE  0x00000003
1092 #define RTC_IO_TOUCH_DRANGE_M  ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S))
1093 #define RTC_IO_TOUCH_DRANGE_V  0x3
1094 #define RTC_IO_TOUCH_DRANGE_S  25
1095 /* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */
1096 /*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When
1097  BIAS_SLEEP  this setting is available*/
1098 #define RTC_IO_TOUCH_DCUR  0x00000003
1099 #define RTC_IO_TOUCH_DCUR_M  ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S))
1100 #define RTC_IO_TOUCH_DCUR_V  0x3
1101 #define RTC_IO_TOUCH_DCUR_S  23
1102 
1103 #define RTC_IO_TOUCH_PAD0_REG          (DR_REG_RTCIO_BASE + 0x94)
1104 /* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
1105 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
1106 #define RTC_IO_TOUCH_PAD0_HOLD  (BIT(31))
1107 #define RTC_IO_TOUCH_PAD0_HOLD_M  (BIT(31))
1108 #define RTC_IO_TOUCH_PAD0_HOLD_V  0x1
1109 #define RTC_IO_TOUCH_PAD0_HOLD_S  31
1110 /* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
1111 /*description: the driver strength of the pad*/
1112 #define RTC_IO_TOUCH_PAD0_DRV  0x00000003
1113 #define RTC_IO_TOUCH_PAD0_DRV_M  ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S))
1114 #define RTC_IO_TOUCH_PAD0_DRV_V  0x3
1115 #define RTC_IO_TOUCH_PAD0_DRV_S  29
1116 /* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
1117 /*description: the pull down enable of the pad*/
1118 #define RTC_IO_TOUCH_PAD0_RDE  (BIT(28))
1119 #define RTC_IO_TOUCH_PAD0_RDE_M  (BIT(28))
1120 #define RTC_IO_TOUCH_PAD0_RDE_V  0x1
1121 #define RTC_IO_TOUCH_PAD0_RDE_S  28
1122 /* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
1123 /*description: the pull up enable of the pad*/
1124 #define RTC_IO_TOUCH_PAD0_RUE  (BIT(27))
1125 #define RTC_IO_TOUCH_PAD0_RUE_M  (BIT(27))
1126 #define RTC_IO_TOUCH_PAD0_RUE_V  0x1
1127 #define RTC_IO_TOUCH_PAD0_RUE_S  27
1128 /* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
1129 /*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
1130 #define RTC_IO_TOUCH_PAD0_DAC  0x00000007
1131 #define RTC_IO_TOUCH_PAD0_DAC_M  ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S))
1132 #define RTC_IO_TOUCH_PAD0_DAC_V  0x7
1133 #define RTC_IO_TOUCH_PAD0_DAC_S  23
1134 /* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
1135 /*description: start touch sensor.*/
1136 #define RTC_IO_TOUCH_PAD0_START  (BIT(22))
1137 #define RTC_IO_TOUCH_PAD0_START_M  (BIT(22))
1138 #define RTC_IO_TOUCH_PAD0_START_V  0x1
1139 #define RTC_IO_TOUCH_PAD0_START_S  22
1140 /* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
1141 /*description: default touch sensor tie option. 0: tie low  1: tie high.*/
1142 #define RTC_IO_TOUCH_PAD0_TIE_OPT  (BIT(21))
1143 #define RTC_IO_TOUCH_PAD0_TIE_OPT_M  (BIT(21))
1144 #define RTC_IO_TOUCH_PAD0_TIE_OPT_V  0x1
1145 #define RTC_IO_TOUCH_PAD0_TIE_OPT_S  21
1146 /* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
1147 /*description: touch sensor power on.*/
1148 #define RTC_IO_TOUCH_PAD0_XPD  (BIT(20))
1149 #define RTC_IO_TOUCH_PAD0_XPD_M  (BIT(20))
1150 #define RTC_IO_TOUCH_PAD0_XPD_V  0x1
1151 #define RTC_IO_TOUCH_PAD0_XPD_S  20
1152 /* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
1153 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
1154 #define RTC_IO_TOUCH_PAD0_MUX_SEL  (BIT(19))
1155 #define RTC_IO_TOUCH_PAD0_MUX_SEL_M  (BIT(19))
1156 #define RTC_IO_TOUCH_PAD0_MUX_SEL_V  0x1
1157 #define RTC_IO_TOUCH_PAD0_MUX_SEL_S  19
1158 /* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
1159 /*description: the functional selection signal of the pad*/
1160 #define RTC_IO_TOUCH_PAD0_FUN_SEL  0x00000003
1161 #define RTC_IO_TOUCH_PAD0_FUN_SEL_M  ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S))
1162 #define RTC_IO_TOUCH_PAD0_FUN_SEL_V  0x3
1163 #define RTC_IO_TOUCH_PAD0_FUN_SEL_S  17
1164 /* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
1165 /*description: the sleep status selection signal of the pad*/
1166 #define RTC_IO_TOUCH_PAD0_SLP_SEL  (BIT(16))
1167 #define RTC_IO_TOUCH_PAD0_SLP_SEL_M  (BIT(16))
1168 #define RTC_IO_TOUCH_PAD0_SLP_SEL_V  0x1
1169 #define RTC_IO_TOUCH_PAD0_SLP_SEL_S  16
1170 /* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
1171 /*description: the input enable of the pad in sleep status*/
1172 #define RTC_IO_TOUCH_PAD0_SLP_IE  (BIT(15))
1173 #define RTC_IO_TOUCH_PAD0_SLP_IE_M  (BIT(15))
1174 #define RTC_IO_TOUCH_PAD0_SLP_IE_V  0x1
1175 #define RTC_IO_TOUCH_PAD0_SLP_IE_S  15
1176 /* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
1177 /*description: the output enable of the pad in sleep status*/
1178 #define RTC_IO_TOUCH_PAD0_SLP_OE  (BIT(14))
1179 #define RTC_IO_TOUCH_PAD0_SLP_OE_M  (BIT(14))
1180 #define RTC_IO_TOUCH_PAD0_SLP_OE_V  0x1
1181 #define RTC_IO_TOUCH_PAD0_SLP_OE_S  14
1182 /* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
1183 /*description: the input enable of the pad*/
1184 #define RTC_IO_TOUCH_PAD0_FUN_IE  (BIT(13))
1185 #define RTC_IO_TOUCH_PAD0_FUN_IE_M  (BIT(13))
1186 #define RTC_IO_TOUCH_PAD0_FUN_IE_V  0x1
1187 #define RTC_IO_TOUCH_PAD0_FUN_IE_S  13
1188 /* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
1189 /*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/
1190 #define RTC_IO_TOUCH_PAD0_TO_GPIO  (BIT(12))
1191 #define RTC_IO_TOUCH_PAD0_TO_GPIO_M  (BIT(12))
1192 #define RTC_IO_TOUCH_PAD0_TO_GPIO_V  0x1
1193 #define RTC_IO_TOUCH_PAD0_TO_GPIO_S  12
1194 
1195 #define RTC_IO_TOUCH_PAD1_REG          (DR_REG_RTCIO_BASE + 0x98)
1196 /* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
1197 /*description: */
1198 #define RTC_IO_TOUCH_PAD1_HOLD  (BIT(31))
1199 #define RTC_IO_TOUCH_PAD1_HOLD_M  (BIT(31))
1200 #define RTC_IO_TOUCH_PAD1_HOLD_V  0x1
1201 #define RTC_IO_TOUCH_PAD1_HOLD_S  31
1202 /* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
1203 /*description: the driver strength of the pad*/
1204 #define RTC_IO_TOUCH_PAD1_DRV  0x00000003
1205 #define RTC_IO_TOUCH_PAD1_DRV_M  ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S))
1206 #define RTC_IO_TOUCH_PAD1_DRV_V  0x3
1207 #define RTC_IO_TOUCH_PAD1_DRV_S  29
1208 /* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
1209 /*description: the pull down enable of the pad*/
1210 #define RTC_IO_TOUCH_PAD1_RDE  (BIT(28))
1211 #define RTC_IO_TOUCH_PAD1_RDE_M  (BIT(28))
1212 #define RTC_IO_TOUCH_PAD1_RDE_V  0x1
1213 #define RTC_IO_TOUCH_PAD1_RDE_S  28
1214 /* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
1215 /*description: the pull up enable of the pad*/
1216 #define RTC_IO_TOUCH_PAD1_RUE  (BIT(27))
1217 #define RTC_IO_TOUCH_PAD1_RUE_M  (BIT(27))
1218 #define RTC_IO_TOUCH_PAD1_RUE_V  0x1
1219 #define RTC_IO_TOUCH_PAD1_RUE_S  27
1220 /* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
1221 /*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
1222 #define RTC_IO_TOUCH_PAD1_DAC  0x00000007
1223 #define RTC_IO_TOUCH_PAD1_DAC_M  ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S))
1224 #define RTC_IO_TOUCH_PAD1_DAC_V  0x7
1225 #define RTC_IO_TOUCH_PAD1_DAC_S  23
1226 /* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
1227 /*description: start touch sensor.*/
1228 #define RTC_IO_TOUCH_PAD1_START  (BIT(22))
1229 #define RTC_IO_TOUCH_PAD1_START_M  (BIT(22))
1230 #define RTC_IO_TOUCH_PAD1_START_V  0x1
1231 #define RTC_IO_TOUCH_PAD1_START_S  22
1232 /* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
1233 /*description: default touch sensor tie option. 0: tie low  1: tie high.*/
1234 #define RTC_IO_TOUCH_PAD1_TIE_OPT  (BIT(21))
1235 #define RTC_IO_TOUCH_PAD1_TIE_OPT_M  (BIT(21))
1236 #define RTC_IO_TOUCH_PAD1_TIE_OPT_V  0x1
1237 #define RTC_IO_TOUCH_PAD1_TIE_OPT_S  21
1238 /* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
1239 /*description: touch sensor power on.*/
1240 #define RTC_IO_TOUCH_PAD1_XPD  (BIT(20))
1241 #define RTC_IO_TOUCH_PAD1_XPD_M  (BIT(20))
1242 #define RTC_IO_TOUCH_PAD1_XPD_V  0x1
1243 #define RTC_IO_TOUCH_PAD1_XPD_S  20
1244 /* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
1245 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
1246 #define RTC_IO_TOUCH_PAD1_MUX_SEL  (BIT(19))
1247 #define RTC_IO_TOUCH_PAD1_MUX_SEL_M  (BIT(19))
1248 #define RTC_IO_TOUCH_PAD1_MUX_SEL_V  0x1
1249 #define RTC_IO_TOUCH_PAD1_MUX_SEL_S  19
1250 /* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
1251 /*description: the functional selection signal of the pad*/
1252 #define RTC_IO_TOUCH_PAD1_FUN_SEL  0x00000003
1253 #define RTC_IO_TOUCH_PAD1_FUN_SEL_M  ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S))
1254 #define RTC_IO_TOUCH_PAD1_FUN_SEL_V  0x3
1255 #define RTC_IO_TOUCH_PAD1_FUN_SEL_S  17
1256 /* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
1257 /*description: the sleep status selection signal of the pad*/
1258 #define RTC_IO_TOUCH_PAD1_SLP_SEL  (BIT(16))
1259 #define RTC_IO_TOUCH_PAD1_SLP_SEL_M  (BIT(16))
1260 #define RTC_IO_TOUCH_PAD1_SLP_SEL_V  0x1
1261 #define RTC_IO_TOUCH_PAD1_SLP_SEL_S  16
1262 /* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
1263 /*description: the input enable of the pad in sleep status*/
1264 #define RTC_IO_TOUCH_PAD1_SLP_IE  (BIT(15))
1265 #define RTC_IO_TOUCH_PAD1_SLP_IE_M  (BIT(15))
1266 #define RTC_IO_TOUCH_PAD1_SLP_IE_V  0x1
1267 #define RTC_IO_TOUCH_PAD1_SLP_IE_S  15
1268 /* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
1269 /*description: the output enable of the pad in sleep status*/
1270 #define RTC_IO_TOUCH_PAD1_SLP_OE  (BIT(14))
1271 #define RTC_IO_TOUCH_PAD1_SLP_OE_M  (BIT(14))
1272 #define RTC_IO_TOUCH_PAD1_SLP_OE_V  0x1
1273 #define RTC_IO_TOUCH_PAD1_SLP_OE_S  14
1274 /* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
1275 /*description: the input enable of the pad*/
1276 #define RTC_IO_TOUCH_PAD1_FUN_IE  (BIT(13))
1277 #define RTC_IO_TOUCH_PAD1_FUN_IE_M  (BIT(13))
1278 #define RTC_IO_TOUCH_PAD1_FUN_IE_V  0x1
1279 #define RTC_IO_TOUCH_PAD1_FUN_IE_S  13
1280 /* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
1281 /*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/
1282 #define RTC_IO_TOUCH_PAD1_TO_GPIO  (BIT(12))
1283 #define RTC_IO_TOUCH_PAD1_TO_GPIO_M  (BIT(12))
1284 #define RTC_IO_TOUCH_PAD1_TO_GPIO_V  0x1
1285 #define RTC_IO_TOUCH_PAD1_TO_GPIO_S  12
1286 
1287 #define RTC_IO_TOUCH_PAD2_REG          (DR_REG_RTCIO_BASE + 0x9c)
1288 /* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
1289 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
1290 #define RTC_IO_TOUCH_PAD2_HOLD  (BIT(31))
1291 #define RTC_IO_TOUCH_PAD2_HOLD_M  (BIT(31))
1292 #define RTC_IO_TOUCH_PAD2_HOLD_V  0x1
1293 #define RTC_IO_TOUCH_PAD2_HOLD_S  31
1294 /* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
1295 /*description: the driver strength of the pad*/
1296 #define RTC_IO_TOUCH_PAD2_DRV  0x00000003
1297 #define RTC_IO_TOUCH_PAD2_DRV_M  ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S))
1298 #define RTC_IO_TOUCH_PAD2_DRV_V  0x3
1299 #define RTC_IO_TOUCH_PAD2_DRV_S  29
1300 /* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
1301 /*description: the pull down enable of the pad*/
1302 #define RTC_IO_TOUCH_PAD2_RDE  (BIT(28))
1303 #define RTC_IO_TOUCH_PAD2_RDE_M  (BIT(28))
1304 #define RTC_IO_TOUCH_PAD2_RDE_V  0x1
1305 #define RTC_IO_TOUCH_PAD2_RDE_S  28
1306 /* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
1307 /*description: the pull up enable of the pad*/
1308 #define RTC_IO_TOUCH_PAD2_RUE  (BIT(27))
1309 #define RTC_IO_TOUCH_PAD2_RUE_M  (BIT(27))
1310 #define RTC_IO_TOUCH_PAD2_RUE_V  0x1
1311 #define RTC_IO_TOUCH_PAD2_RUE_S  27
1312 /* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
1313 /*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
1314 #define RTC_IO_TOUCH_PAD2_DAC  0x00000007
1315 #define RTC_IO_TOUCH_PAD2_DAC_M  ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S))
1316 #define RTC_IO_TOUCH_PAD2_DAC_V  0x7
1317 #define RTC_IO_TOUCH_PAD2_DAC_S  23
1318 /* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
1319 /*description: start touch sensor.*/
1320 #define RTC_IO_TOUCH_PAD2_START  (BIT(22))
1321 #define RTC_IO_TOUCH_PAD2_START_M  (BIT(22))
1322 #define RTC_IO_TOUCH_PAD2_START_V  0x1
1323 #define RTC_IO_TOUCH_PAD2_START_S  22
1324 /* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
1325 /*description: default touch sensor tie option. 0: tie low  1: tie high.*/
1326 #define RTC_IO_TOUCH_PAD2_TIE_OPT  (BIT(21))
1327 #define RTC_IO_TOUCH_PAD2_TIE_OPT_M  (BIT(21))
1328 #define RTC_IO_TOUCH_PAD2_TIE_OPT_V  0x1
1329 #define RTC_IO_TOUCH_PAD2_TIE_OPT_S  21
1330 /* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
1331 /*description: touch sensor power on.*/
1332 #define RTC_IO_TOUCH_PAD2_XPD  (BIT(20))
1333 #define RTC_IO_TOUCH_PAD2_XPD_M  (BIT(20))
1334 #define RTC_IO_TOUCH_PAD2_XPD_V  0x1
1335 #define RTC_IO_TOUCH_PAD2_XPD_S  20
1336 /* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
1337 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
1338 #define RTC_IO_TOUCH_PAD2_MUX_SEL  (BIT(19))
1339 #define RTC_IO_TOUCH_PAD2_MUX_SEL_M  (BIT(19))
1340 #define RTC_IO_TOUCH_PAD2_MUX_SEL_V  0x1
1341 #define RTC_IO_TOUCH_PAD2_MUX_SEL_S  19
1342 /* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
1343 /*description: the functional selection signal of the pad*/
1344 #define RTC_IO_TOUCH_PAD2_FUN_SEL  0x00000003
1345 #define RTC_IO_TOUCH_PAD2_FUN_SEL_M  ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S))
1346 #define RTC_IO_TOUCH_PAD2_FUN_SEL_V  0x3
1347 #define RTC_IO_TOUCH_PAD2_FUN_SEL_S  17
1348 /* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
1349 /*description: the sleep status selection signal of the pad*/
1350 #define RTC_IO_TOUCH_PAD2_SLP_SEL  (BIT(16))
1351 #define RTC_IO_TOUCH_PAD2_SLP_SEL_M  (BIT(16))
1352 #define RTC_IO_TOUCH_PAD2_SLP_SEL_V  0x1
1353 #define RTC_IO_TOUCH_PAD2_SLP_SEL_S  16
1354 /* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
1355 /*description: the input enable of the pad in sleep status*/
1356 #define RTC_IO_TOUCH_PAD2_SLP_IE  (BIT(15))
1357 #define RTC_IO_TOUCH_PAD2_SLP_IE_M  (BIT(15))
1358 #define RTC_IO_TOUCH_PAD2_SLP_IE_V  0x1
1359 #define RTC_IO_TOUCH_PAD2_SLP_IE_S  15
1360 /* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
1361 /*description: the output enable of the pad in sleep status*/
1362 #define RTC_IO_TOUCH_PAD2_SLP_OE  (BIT(14))
1363 #define RTC_IO_TOUCH_PAD2_SLP_OE_M  (BIT(14))
1364 #define RTC_IO_TOUCH_PAD2_SLP_OE_V  0x1
1365 #define RTC_IO_TOUCH_PAD2_SLP_OE_S  14
1366 /* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
1367 /*description: the input enable of the pad*/
1368 #define RTC_IO_TOUCH_PAD2_FUN_IE  (BIT(13))
1369 #define RTC_IO_TOUCH_PAD2_FUN_IE_M  (BIT(13))
1370 #define RTC_IO_TOUCH_PAD2_FUN_IE_V  0x1
1371 #define RTC_IO_TOUCH_PAD2_FUN_IE_S  13
1372 /* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
1373 /*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/
1374 #define RTC_IO_TOUCH_PAD2_TO_GPIO  (BIT(12))
1375 #define RTC_IO_TOUCH_PAD2_TO_GPIO_M  (BIT(12))
1376 #define RTC_IO_TOUCH_PAD2_TO_GPIO_V  0x1
1377 #define RTC_IO_TOUCH_PAD2_TO_GPIO_S  12
1378 
1379 #define RTC_IO_TOUCH_PAD3_REG          (DR_REG_RTCIO_BASE + 0xa0)
1380 /* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
1381 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
1382 #define RTC_IO_TOUCH_PAD3_HOLD  (BIT(31))
1383 #define RTC_IO_TOUCH_PAD3_HOLD_M  (BIT(31))
1384 #define RTC_IO_TOUCH_PAD3_HOLD_V  0x1
1385 #define RTC_IO_TOUCH_PAD3_HOLD_S  31
1386 /* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
1387 /*description: the driver strength of the pad*/
1388 #define RTC_IO_TOUCH_PAD3_DRV  0x00000003
1389 #define RTC_IO_TOUCH_PAD3_DRV_M  ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S))
1390 #define RTC_IO_TOUCH_PAD3_DRV_V  0x3
1391 #define RTC_IO_TOUCH_PAD3_DRV_S  29
1392 /* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
1393 /*description: the pull down enable of the pad*/
1394 #define RTC_IO_TOUCH_PAD3_RDE  (BIT(28))
1395 #define RTC_IO_TOUCH_PAD3_RDE_M  (BIT(28))
1396 #define RTC_IO_TOUCH_PAD3_RDE_V  0x1
1397 #define RTC_IO_TOUCH_PAD3_RDE_S  28
1398 /* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
1399 /*description: the pull up enable of the pad*/
1400 #define RTC_IO_TOUCH_PAD3_RUE  (BIT(27))
1401 #define RTC_IO_TOUCH_PAD3_RUE_M  (BIT(27))
1402 #define RTC_IO_TOUCH_PAD3_RUE_V  0x1
1403 #define RTC_IO_TOUCH_PAD3_RUE_S  27
1404 /* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
1405 /*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
1406 #define RTC_IO_TOUCH_PAD3_DAC  0x00000007
1407 #define RTC_IO_TOUCH_PAD3_DAC_M  ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S))
1408 #define RTC_IO_TOUCH_PAD3_DAC_V  0x7
1409 #define RTC_IO_TOUCH_PAD3_DAC_S  23
1410 /* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
1411 /*description: start touch sensor.*/
1412 #define RTC_IO_TOUCH_PAD3_START  (BIT(22))
1413 #define RTC_IO_TOUCH_PAD3_START_M  (BIT(22))
1414 #define RTC_IO_TOUCH_PAD3_START_V  0x1
1415 #define RTC_IO_TOUCH_PAD3_START_S  22
1416 /* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
1417 /*description: default touch sensor tie option. 0: tie low  1: tie high.*/
1418 #define RTC_IO_TOUCH_PAD3_TIE_OPT  (BIT(21))
1419 #define RTC_IO_TOUCH_PAD3_TIE_OPT_M  (BIT(21))
1420 #define RTC_IO_TOUCH_PAD3_TIE_OPT_V  0x1
1421 #define RTC_IO_TOUCH_PAD3_TIE_OPT_S  21
1422 /* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
1423 /*description: touch sensor power on.*/
1424 #define RTC_IO_TOUCH_PAD3_XPD  (BIT(20))
1425 #define RTC_IO_TOUCH_PAD3_XPD_M  (BIT(20))
1426 #define RTC_IO_TOUCH_PAD3_XPD_V  0x1
1427 #define RTC_IO_TOUCH_PAD3_XPD_S  20
1428 /* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
1429 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
1430 #define RTC_IO_TOUCH_PAD3_MUX_SEL  (BIT(19))
1431 #define RTC_IO_TOUCH_PAD3_MUX_SEL_M  (BIT(19))
1432 #define RTC_IO_TOUCH_PAD3_MUX_SEL_V  0x1
1433 #define RTC_IO_TOUCH_PAD3_MUX_SEL_S  19
1434 /* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
1435 /*description: the functional selection signal of the pad*/
1436 #define RTC_IO_TOUCH_PAD3_FUN_SEL  0x00000003
1437 #define RTC_IO_TOUCH_PAD3_FUN_SEL_M  ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S))
1438 #define RTC_IO_TOUCH_PAD3_FUN_SEL_V  0x3
1439 #define RTC_IO_TOUCH_PAD3_FUN_SEL_S  17
1440 /* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
1441 /*description: the sleep status selection signal of the pad*/
1442 #define RTC_IO_TOUCH_PAD3_SLP_SEL  (BIT(16))
1443 #define RTC_IO_TOUCH_PAD3_SLP_SEL_M  (BIT(16))
1444 #define RTC_IO_TOUCH_PAD3_SLP_SEL_V  0x1
1445 #define RTC_IO_TOUCH_PAD3_SLP_SEL_S  16
1446 /* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
1447 /*description: the input enable of the pad in sleep status*/
1448 #define RTC_IO_TOUCH_PAD3_SLP_IE  (BIT(15))
1449 #define RTC_IO_TOUCH_PAD3_SLP_IE_M  (BIT(15))
1450 #define RTC_IO_TOUCH_PAD3_SLP_IE_V  0x1
1451 #define RTC_IO_TOUCH_PAD3_SLP_IE_S  15
1452 /* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
1453 /*description: the output enable of the pad in sleep status*/
1454 #define RTC_IO_TOUCH_PAD3_SLP_OE  (BIT(14))
1455 #define RTC_IO_TOUCH_PAD3_SLP_OE_M  (BIT(14))
1456 #define RTC_IO_TOUCH_PAD3_SLP_OE_V  0x1
1457 #define RTC_IO_TOUCH_PAD3_SLP_OE_S  14
1458 /* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
1459 /*description: the input enable of the pad*/
1460 #define RTC_IO_TOUCH_PAD3_FUN_IE  (BIT(13))
1461 #define RTC_IO_TOUCH_PAD3_FUN_IE_M  (BIT(13))
1462 #define RTC_IO_TOUCH_PAD3_FUN_IE_V  0x1
1463 #define RTC_IO_TOUCH_PAD3_FUN_IE_S  13
1464 /* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
1465 /*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/
1466 #define RTC_IO_TOUCH_PAD3_TO_GPIO  (BIT(12))
1467 #define RTC_IO_TOUCH_PAD3_TO_GPIO_M  (BIT(12))
1468 #define RTC_IO_TOUCH_PAD3_TO_GPIO_V  0x1
1469 #define RTC_IO_TOUCH_PAD3_TO_GPIO_S  12
1470 
1471 #define RTC_IO_TOUCH_PAD4_REG          (DR_REG_RTCIO_BASE + 0xa4)
1472 /* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
1473 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
1474 #define RTC_IO_TOUCH_PAD4_HOLD  (BIT(31))
1475 #define RTC_IO_TOUCH_PAD4_HOLD_M  (BIT(31))
1476 #define RTC_IO_TOUCH_PAD4_HOLD_V  0x1
1477 #define RTC_IO_TOUCH_PAD4_HOLD_S  31
1478 /* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
1479 /*description: the driver strength of the pad*/
1480 #define RTC_IO_TOUCH_PAD4_DRV  0x00000003
1481 #define RTC_IO_TOUCH_PAD4_DRV_M  ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S))
1482 #define RTC_IO_TOUCH_PAD4_DRV_V  0x3
1483 #define RTC_IO_TOUCH_PAD4_DRV_S  29
1484 /* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
1485 /*description: the pull down enable of the pad*/
1486 #define RTC_IO_TOUCH_PAD4_RDE  (BIT(28))
1487 #define RTC_IO_TOUCH_PAD4_RDE_M  (BIT(28))
1488 #define RTC_IO_TOUCH_PAD4_RDE_V  0x1
1489 #define RTC_IO_TOUCH_PAD4_RDE_S  28
1490 /* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
1491 /*description: the pull up enable of the pad*/
1492 #define RTC_IO_TOUCH_PAD4_RUE  (BIT(27))
1493 #define RTC_IO_TOUCH_PAD4_RUE_M  (BIT(27))
1494 #define RTC_IO_TOUCH_PAD4_RUE_V  0x1
1495 #define RTC_IO_TOUCH_PAD4_RUE_S  27
1496 /* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
1497 /*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
1498 #define RTC_IO_TOUCH_PAD4_DAC  0x00000007
1499 #define RTC_IO_TOUCH_PAD4_DAC_M  ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S))
1500 #define RTC_IO_TOUCH_PAD4_DAC_V  0x7
1501 #define RTC_IO_TOUCH_PAD4_DAC_S  23
1502 /* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
1503 /*description: start touch sensor.*/
1504 #define RTC_IO_TOUCH_PAD4_START  (BIT(22))
1505 #define RTC_IO_TOUCH_PAD4_START_M  (BIT(22))
1506 #define RTC_IO_TOUCH_PAD4_START_V  0x1
1507 #define RTC_IO_TOUCH_PAD4_START_S  22
1508 /* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
1509 /*description: default touch sensor tie option. 0: tie low  1: tie high.*/
1510 #define RTC_IO_TOUCH_PAD4_TIE_OPT  (BIT(21))
1511 #define RTC_IO_TOUCH_PAD4_TIE_OPT_M  (BIT(21))
1512 #define RTC_IO_TOUCH_PAD4_TIE_OPT_V  0x1
1513 #define RTC_IO_TOUCH_PAD4_TIE_OPT_S  21
1514 /* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
1515 /*description: touch sensor power on.*/
1516 #define RTC_IO_TOUCH_PAD4_XPD  (BIT(20))
1517 #define RTC_IO_TOUCH_PAD4_XPD_M  (BIT(20))
1518 #define RTC_IO_TOUCH_PAD4_XPD_V  0x1
1519 #define RTC_IO_TOUCH_PAD4_XPD_S  20
1520 /* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
1521 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
1522 #define RTC_IO_TOUCH_PAD4_MUX_SEL  (BIT(19))
1523 #define RTC_IO_TOUCH_PAD4_MUX_SEL_M  (BIT(19))
1524 #define RTC_IO_TOUCH_PAD4_MUX_SEL_V  0x1
1525 #define RTC_IO_TOUCH_PAD4_MUX_SEL_S  19
1526 /* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
1527 /*description: the functional selection signal of the pad*/
1528 #define RTC_IO_TOUCH_PAD4_FUN_SEL  0x00000003
1529 #define RTC_IO_TOUCH_PAD4_FUN_SEL_M  ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S))
1530 #define RTC_IO_TOUCH_PAD4_FUN_SEL_V  0x3
1531 #define RTC_IO_TOUCH_PAD4_FUN_SEL_S  17
1532 /* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
1533 /*description: the sleep status selection signal of the pad*/
1534 #define RTC_IO_TOUCH_PAD4_SLP_SEL  (BIT(16))
1535 #define RTC_IO_TOUCH_PAD4_SLP_SEL_M  (BIT(16))
1536 #define RTC_IO_TOUCH_PAD4_SLP_SEL_V  0x1
1537 #define RTC_IO_TOUCH_PAD4_SLP_SEL_S  16
1538 /* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
1539 /*description: the input enable of the pad in sleep status*/
1540 #define RTC_IO_TOUCH_PAD4_SLP_IE  (BIT(15))
1541 #define RTC_IO_TOUCH_PAD4_SLP_IE_M  (BIT(15))
1542 #define RTC_IO_TOUCH_PAD4_SLP_IE_V  0x1
1543 #define RTC_IO_TOUCH_PAD4_SLP_IE_S  15
1544 /* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
1545 /*description: the output enable of the pad in sleep status*/
1546 #define RTC_IO_TOUCH_PAD4_SLP_OE  (BIT(14))
1547 #define RTC_IO_TOUCH_PAD4_SLP_OE_M  (BIT(14))
1548 #define RTC_IO_TOUCH_PAD4_SLP_OE_V  0x1
1549 #define RTC_IO_TOUCH_PAD4_SLP_OE_S  14
1550 /* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
1551 /*description: the input enable of the pad*/
1552 #define RTC_IO_TOUCH_PAD4_FUN_IE  (BIT(13))
1553 #define RTC_IO_TOUCH_PAD4_FUN_IE_M  (BIT(13))
1554 #define RTC_IO_TOUCH_PAD4_FUN_IE_V  0x1
1555 #define RTC_IO_TOUCH_PAD4_FUN_IE_S  13
1556 /* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
1557 /*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/
1558 #define RTC_IO_TOUCH_PAD4_TO_GPIO  (BIT(12))
1559 #define RTC_IO_TOUCH_PAD4_TO_GPIO_M  (BIT(12))
1560 #define RTC_IO_TOUCH_PAD4_TO_GPIO_V  0x1
1561 #define RTC_IO_TOUCH_PAD4_TO_GPIO_S  12
1562 
1563 #define RTC_IO_TOUCH_PAD5_REG          (DR_REG_RTCIO_BASE + 0xa8)
1564 /* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
1565 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
1566 #define RTC_IO_TOUCH_PAD5_HOLD  (BIT(31))
1567 #define RTC_IO_TOUCH_PAD5_HOLD_M  (BIT(31))
1568 #define RTC_IO_TOUCH_PAD5_HOLD_V  0x1
1569 #define RTC_IO_TOUCH_PAD5_HOLD_S  31
1570 /* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
1571 /*description: the driver strength of the pad*/
1572 #define RTC_IO_TOUCH_PAD5_DRV  0x00000003
1573 #define RTC_IO_TOUCH_PAD5_DRV_M  ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S))
1574 #define RTC_IO_TOUCH_PAD5_DRV_V  0x3
1575 #define RTC_IO_TOUCH_PAD5_DRV_S  29
1576 /* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
1577 /*description: the pull down enable of the pad*/
1578 #define RTC_IO_TOUCH_PAD5_RDE  (BIT(28))
1579 #define RTC_IO_TOUCH_PAD5_RDE_M  (BIT(28))
1580 #define RTC_IO_TOUCH_PAD5_RDE_V  0x1
1581 #define RTC_IO_TOUCH_PAD5_RDE_S  28
1582 /* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
1583 /*description: the pull up enable of the pad*/
1584 #define RTC_IO_TOUCH_PAD5_RUE  (BIT(27))
1585 #define RTC_IO_TOUCH_PAD5_RUE_M  (BIT(27))
1586 #define RTC_IO_TOUCH_PAD5_RUE_V  0x1
1587 #define RTC_IO_TOUCH_PAD5_RUE_S  27
1588 /* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
1589 /*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
1590 #define RTC_IO_TOUCH_PAD5_DAC  0x00000007
1591 #define RTC_IO_TOUCH_PAD5_DAC_M  ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S))
1592 #define RTC_IO_TOUCH_PAD5_DAC_V  0x7
1593 #define RTC_IO_TOUCH_PAD5_DAC_S  23
1594 /* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
1595 /*description: start touch sensor.*/
1596 #define RTC_IO_TOUCH_PAD5_START  (BIT(22))
1597 #define RTC_IO_TOUCH_PAD5_START_M  (BIT(22))
1598 #define RTC_IO_TOUCH_PAD5_START_V  0x1
1599 #define RTC_IO_TOUCH_PAD5_START_S  22
1600 /* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
1601 /*description: default touch sensor tie option. 0: tie low  1: tie high.*/
1602 #define RTC_IO_TOUCH_PAD5_TIE_OPT  (BIT(21))
1603 #define RTC_IO_TOUCH_PAD5_TIE_OPT_M  (BIT(21))
1604 #define RTC_IO_TOUCH_PAD5_TIE_OPT_V  0x1
1605 #define RTC_IO_TOUCH_PAD5_TIE_OPT_S  21
1606 /* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
1607 /*description: touch sensor power on.*/
1608 #define RTC_IO_TOUCH_PAD5_XPD  (BIT(20))
1609 #define RTC_IO_TOUCH_PAD5_XPD_M  (BIT(20))
1610 #define RTC_IO_TOUCH_PAD5_XPD_V  0x1
1611 #define RTC_IO_TOUCH_PAD5_XPD_S  20
1612 /* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
1613 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
1614 #define RTC_IO_TOUCH_PAD5_MUX_SEL  (BIT(19))
1615 #define RTC_IO_TOUCH_PAD5_MUX_SEL_M  (BIT(19))
1616 #define RTC_IO_TOUCH_PAD5_MUX_SEL_V  0x1
1617 #define RTC_IO_TOUCH_PAD5_MUX_SEL_S  19
1618 /* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
1619 /*description: the functional selection signal of the pad*/
1620 #define RTC_IO_TOUCH_PAD5_FUN_SEL  0x00000003
1621 #define RTC_IO_TOUCH_PAD5_FUN_SEL_M  ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S))
1622 #define RTC_IO_TOUCH_PAD5_FUN_SEL_V  0x3
1623 #define RTC_IO_TOUCH_PAD5_FUN_SEL_S  17
1624 /* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
1625 /*description: the sleep status selection signal of the pad*/
1626 #define RTC_IO_TOUCH_PAD5_SLP_SEL  (BIT(16))
1627 #define RTC_IO_TOUCH_PAD5_SLP_SEL_M  (BIT(16))
1628 #define RTC_IO_TOUCH_PAD5_SLP_SEL_V  0x1
1629 #define RTC_IO_TOUCH_PAD5_SLP_SEL_S  16
1630 /* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
1631 /*description: the input enable of the pad in sleep status*/
1632 #define RTC_IO_TOUCH_PAD5_SLP_IE  (BIT(15))
1633 #define RTC_IO_TOUCH_PAD5_SLP_IE_M  (BIT(15))
1634 #define RTC_IO_TOUCH_PAD5_SLP_IE_V  0x1
1635 #define RTC_IO_TOUCH_PAD5_SLP_IE_S  15
1636 /* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
1637 /*description: the output enable of the pad in sleep status*/
1638 #define RTC_IO_TOUCH_PAD5_SLP_OE  (BIT(14))
1639 #define RTC_IO_TOUCH_PAD5_SLP_OE_M  (BIT(14))
1640 #define RTC_IO_TOUCH_PAD5_SLP_OE_V  0x1
1641 #define RTC_IO_TOUCH_PAD5_SLP_OE_S  14
1642 /* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
1643 /*description: the input enable of the pad*/
1644 #define RTC_IO_TOUCH_PAD5_FUN_IE  (BIT(13))
1645 #define RTC_IO_TOUCH_PAD5_FUN_IE_M  (BIT(13))
1646 #define RTC_IO_TOUCH_PAD5_FUN_IE_V  0x1
1647 #define RTC_IO_TOUCH_PAD5_FUN_IE_S  13
1648 /* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
1649 /*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/
1650 #define RTC_IO_TOUCH_PAD5_TO_GPIO  (BIT(12))
1651 #define RTC_IO_TOUCH_PAD5_TO_GPIO_M  (BIT(12))
1652 #define RTC_IO_TOUCH_PAD5_TO_GPIO_V  0x1
1653 #define RTC_IO_TOUCH_PAD5_TO_GPIO_S  12
1654 
1655 #define RTC_IO_TOUCH_PAD6_REG          (DR_REG_RTCIO_BASE + 0xac)
1656 /* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
1657 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
1658 #define RTC_IO_TOUCH_PAD6_HOLD  (BIT(31))
1659 #define RTC_IO_TOUCH_PAD6_HOLD_M  (BIT(31))
1660 #define RTC_IO_TOUCH_PAD6_HOLD_V  0x1
1661 #define RTC_IO_TOUCH_PAD6_HOLD_S  31
1662 /* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
1663 /*description: the driver strength of the pad*/
1664 #define RTC_IO_TOUCH_PAD6_DRV  0x00000003
1665 #define RTC_IO_TOUCH_PAD6_DRV_M  ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S))
1666 #define RTC_IO_TOUCH_PAD6_DRV_V  0x3
1667 #define RTC_IO_TOUCH_PAD6_DRV_S  29
1668 /* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
1669 /*description: the pull down enable of the pad*/
1670 #define RTC_IO_TOUCH_PAD6_RDE  (BIT(28))
1671 #define RTC_IO_TOUCH_PAD6_RDE_M  (BIT(28))
1672 #define RTC_IO_TOUCH_PAD6_RDE_V  0x1
1673 #define RTC_IO_TOUCH_PAD6_RDE_S  28
1674 /* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
1675 /*description: the pull up enable of the pad*/
1676 #define RTC_IO_TOUCH_PAD6_RUE  (BIT(27))
1677 #define RTC_IO_TOUCH_PAD6_RUE_M  (BIT(27))
1678 #define RTC_IO_TOUCH_PAD6_RUE_V  0x1
1679 #define RTC_IO_TOUCH_PAD6_RUE_S  27
1680 /* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
1681 /*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
1682 #define RTC_IO_TOUCH_PAD6_DAC  0x00000007
1683 #define RTC_IO_TOUCH_PAD6_DAC_M  ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S))
1684 #define RTC_IO_TOUCH_PAD6_DAC_V  0x7
1685 #define RTC_IO_TOUCH_PAD6_DAC_S  23
1686 /* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
1687 /*description: start touch sensor.*/
1688 #define RTC_IO_TOUCH_PAD6_START  (BIT(22))
1689 #define RTC_IO_TOUCH_PAD6_START_M  (BIT(22))
1690 #define RTC_IO_TOUCH_PAD6_START_V  0x1
1691 #define RTC_IO_TOUCH_PAD6_START_S  22
1692 /* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
1693 /*description: default touch sensor tie option. 0: tie low  1: tie high.*/
1694 #define RTC_IO_TOUCH_PAD6_TIE_OPT  (BIT(21))
1695 #define RTC_IO_TOUCH_PAD6_TIE_OPT_M  (BIT(21))
1696 #define RTC_IO_TOUCH_PAD6_TIE_OPT_V  0x1
1697 #define RTC_IO_TOUCH_PAD6_TIE_OPT_S  21
1698 /* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
1699 /*description: touch sensor power on.*/
1700 #define RTC_IO_TOUCH_PAD6_XPD  (BIT(20))
1701 #define RTC_IO_TOUCH_PAD6_XPD_M  (BIT(20))
1702 #define RTC_IO_TOUCH_PAD6_XPD_V  0x1
1703 #define RTC_IO_TOUCH_PAD6_XPD_S  20
1704 /* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
1705 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
1706 #define RTC_IO_TOUCH_PAD6_MUX_SEL  (BIT(19))
1707 #define RTC_IO_TOUCH_PAD6_MUX_SEL_M  (BIT(19))
1708 #define RTC_IO_TOUCH_PAD6_MUX_SEL_V  0x1
1709 #define RTC_IO_TOUCH_PAD6_MUX_SEL_S  19
1710 /* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
1711 /*description: the functional selection signal of the pad*/
1712 #define RTC_IO_TOUCH_PAD6_FUN_SEL  0x00000003
1713 #define RTC_IO_TOUCH_PAD6_FUN_SEL_M  ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S))
1714 #define RTC_IO_TOUCH_PAD6_FUN_SEL_V  0x3
1715 #define RTC_IO_TOUCH_PAD6_FUN_SEL_S  17
1716 /* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
1717 /*description: the sleep status selection signal of the pad*/
1718 #define RTC_IO_TOUCH_PAD6_SLP_SEL  (BIT(16))
1719 #define RTC_IO_TOUCH_PAD6_SLP_SEL_M  (BIT(16))
1720 #define RTC_IO_TOUCH_PAD6_SLP_SEL_V  0x1
1721 #define RTC_IO_TOUCH_PAD6_SLP_SEL_S  16
1722 /* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
1723 /*description: the input enable of the pad in sleep status*/
1724 #define RTC_IO_TOUCH_PAD6_SLP_IE  (BIT(15))
1725 #define RTC_IO_TOUCH_PAD6_SLP_IE_M  (BIT(15))
1726 #define RTC_IO_TOUCH_PAD6_SLP_IE_V  0x1
1727 #define RTC_IO_TOUCH_PAD6_SLP_IE_S  15
1728 /* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
1729 /*description: the output enable of the pad in sleep status*/
1730 #define RTC_IO_TOUCH_PAD6_SLP_OE  (BIT(14))
1731 #define RTC_IO_TOUCH_PAD6_SLP_OE_M  (BIT(14))
1732 #define RTC_IO_TOUCH_PAD6_SLP_OE_V  0x1
1733 #define RTC_IO_TOUCH_PAD6_SLP_OE_S  14
1734 /* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
1735 /*description: the input enable of the pad*/
1736 #define RTC_IO_TOUCH_PAD6_FUN_IE  (BIT(13))
1737 #define RTC_IO_TOUCH_PAD6_FUN_IE_M  (BIT(13))
1738 #define RTC_IO_TOUCH_PAD6_FUN_IE_V  0x1
1739 #define RTC_IO_TOUCH_PAD6_FUN_IE_S  13
1740 /* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
1741 /*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/
1742 #define RTC_IO_TOUCH_PAD6_TO_GPIO  (BIT(12))
1743 #define RTC_IO_TOUCH_PAD6_TO_GPIO_M  (BIT(12))
1744 #define RTC_IO_TOUCH_PAD6_TO_GPIO_V  0x1
1745 #define RTC_IO_TOUCH_PAD6_TO_GPIO_S  12
1746 
1747 #define RTC_IO_TOUCH_PAD7_REG          (DR_REG_RTCIO_BASE + 0xb0)
1748 /* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
1749 /*description: hold the current value of the output when setting the hold to Ò1Ó*/
1750 #define RTC_IO_TOUCH_PAD7_HOLD  (BIT(31))
1751 #define RTC_IO_TOUCH_PAD7_HOLD_M  (BIT(31))
1752 #define RTC_IO_TOUCH_PAD7_HOLD_V  0x1
1753 #define RTC_IO_TOUCH_PAD7_HOLD_S  31
1754 /* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
1755 /*description: the driver strength of the pad*/
1756 #define RTC_IO_TOUCH_PAD7_DRV  0x00000003
1757 #define RTC_IO_TOUCH_PAD7_DRV_M  ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S))
1758 #define RTC_IO_TOUCH_PAD7_DRV_V  0x3
1759 #define RTC_IO_TOUCH_PAD7_DRV_S  29
1760 /* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
1761 /*description: the pull down enable of the pad*/
1762 #define RTC_IO_TOUCH_PAD7_RDE  (BIT(28))
1763 #define RTC_IO_TOUCH_PAD7_RDE_M  (BIT(28))
1764 #define RTC_IO_TOUCH_PAD7_RDE_V  0x1
1765 #define RTC_IO_TOUCH_PAD7_RDE_S  28
1766 /* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
1767 /*description: the pull up enable of the pad*/
1768 #define RTC_IO_TOUCH_PAD7_RUE  (BIT(27))
1769 #define RTC_IO_TOUCH_PAD7_RUE_M  (BIT(27))
1770 #define RTC_IO_TOUCH_PAD7_RUE_V  0x1
1771 #define RTC_IO_TOUCH_PAD7_RUE_S  27
1772 /* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
1773 /*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
1774 #define RTC_IO_TOUCH_PAD7_DAC  0x00000007
1775 #define RTC_IO_TOUCH_PAD7_DAC_M  ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S))
1776 #define RTC_IO_TOUCH_PAD7_DAC_V  0x7
1777 #define RTC_IO_TOUCH_PAD7_DAC_S  23
1778 /* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
1779 /*description: start touch sensor.*/
1780 #define RTC_IO_TOUCH_PAD7_START  (BIT(22))
1781 #define RTC_IO_TOUCH_PAD7_START_M  (BIT(22))
1782 #define RTC_IO_TOUCH_PAD7_START_V  0x1
1783 #define RTC_IO_TOUCH_PAD7_START_S  22
1784 /* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
1785 /*description: default touch sensor tie option. 0: tie low  1: tie high.*/
1786 #define RTC_IO_TOUCH_PAD7_TIE_OPT  (BIT(21))
1787 #define RTC_IO_TOUCH_PAD7_TIE_OPT_M  (BIT(21))
1788 #define RTC_IO_TOUCH_PAD7_TIE_OPT_V  0x1
1789 #define RTC_IO_TOUCH_PAD7_TIE_OPT_S  21
1790 /* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
1791 /*description: touch sensor power on.*/
1792 #define RTC_IO_TOUCH_PAD7_XPD  (BIT(20))
1793 #define RTC_IO_TOUCH_PAD7_XPD_M  (BIT(20))
1794 #define RTC_IO_TOUCH_PAD7_XPD_V  0x1
1795 #define RTC_IO_TOUCH_PAD7_XPD_S  20
1796 /* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
1797 /*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
1798 #define RTC_IO_TOUCH_PAD7_MUX_SEL  (BIT(19))
1799 #define RTC_IO_TOUCH_PAD7_MUX_SEL_M  (BIT(19))
1800 #define RTC_IO_TOUCH_PAD7_MUX_SEL_V  0x1
1801 #define RTC_IO_TOUCH_PAD7_MUX_SEL_S  19
1802 /* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
1803 /*description: the functional selection signal of the pad*/
1804 #define RTC_IO_TOUCH_PAD7_FUN_SEL  0x00000003
1805 #define RTC_IO_TOUCH_PAD7_FUN_SEL_M  ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S))
1806 #define RTC_IO_TOUCH_PAD7_FUN_SEL_V  0x3
1807 #define RTC_IO_TOUCH_PAD7_FUN_SEL_S  17
1808 /* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
1809 /*description: the sleep status selection signal of the pad*/
1810 #define RTC_IO_TOUCH_PAD7_SLP_SEL  (BIT(16))
1811 #define RTC_IO_TOUCH_PAD7_SLP_SEL_M  (BIT(16))
1812 #define RTC_IO_TOUCH_PAD7_SLP_SEL_V  0x1
1813 #define RTC_IO_TOUCH_PAD7_SLP_SEL_S  16
1814 /* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
1815 /*description: the input enable of the pad in sleep status*/
1816 #define RTC_IO_TOUCH_PAD7_SLP_IE  (BIT(15))
1817 #define RTC_IO_TOUCH_PAD7_SLP_IE_M  (BIT(15))
1818 #define RTC_IO_TOUCH_PAD7_SLP_IE_V  0x1
1819 #define RTC_IO_TOUCH_PAD7_SLP_IE_S  15
1820 /* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
1821 /*description: the output enable of the pad in sleep status*/
1822 #define RTC_IO_TOUCH_PAD7_SLP_OE  (BIT(14))
1823 #define RTC_IO_TOUCH_PAD7_SLP_OE_M  (BIT(14))
1824 #define RTC_IO_TOUCH_PAD7_SLP_OE_V  0x1
1825 #define RTC_IO_TOUCH_PAD7_SLP_OE_S  14
1826 /* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
1827 /*description: the input enable of the pad*/
1828 #define RTC_IO_TOUCH_PAD7_FUN_IE  (BIT(13))
1829 #define RTC_IO_TOUCH_PAD7_FUN_IE_M  (BIT(13))
1830 #define RTC_IO_TOUCH_PAD7_FUN_IE_V  0x1
1831 #define RTC_IO_TOUCH_PAD7_FUN_IE_S  13
1832 /* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
1833 /*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/
1834 #define RTC_IO_TOUCH_PAD7_TO_GPIO  (BIT(12))
1835 #define RTC_IO_TOUCH_PAD7_TO_GPIO_M  (BIT(12))
1836 #define RTC_IO_TOUCH_PAD7_TO_GPIO_V  0x1
1837 #define RTC_IO_TOUCH_PAD7_TO_GPIO_S  12
1838 
1839 #define RTC_IO_TOUCH_PAD8_REG          (DR_REG_RTCIO_BASE + 0xb4)
1840 /* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
1841 /*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
1842 #define RTC_IO_TOUCH_PAD8_DAC  0x00000007
1843 #define RTC_IO_TOUCH_PAD8_DAC_M  ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S))
1844 #define RTC_IO_TOUCH_PAD8_DAC_V  0x7
1845 #define RTC_IO_TOUCH_PAD8_DAC_S  23
1846 /* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
1847 /*description: start touch sensor.*/
1848 #define RTC_IO_TOUCH_PAD8_START  (BIT(22))
1849 #define RTC_IO_TOUCH_PAD8_START_M  (BIT(22))
1850 #define RTC_IO_TOUCH_PAD8_START_V  0x1
1851 #define RTC_IO_TOUCH_PAD8_START_S  22
1852 /* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
1853 /*description: default touch sensor tie option. 0: tie low  1: tie high.*/
1854 #define RTC_IO_TOUCH_PAD8_TIE_OPT  (BIT(21))
1855 #define RTC_IO_TOUCH_PAD8_TIE_OPT_M  (BIT(21))
1856 #define RTC_IO_TOUCH_PAD8_TIE_OPT_V  0x1
1857 #define RTC_IO_TOUCH_PAD8_TIE_OPT_S  21
1858 /* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
1859 /*description: touch sensor power on.*/
1860 #define RTC_IO_TOUCH_PAD8_XPD  (BIT(20))
1861 #define RTC_IO_TOUCH_PAD8_XPD_M  (BIT(20))
1862 #define RTC_IO_TOUCH_PAD8_XPD_V  0x1
1863 #define RTC_IO_TOUCH_PAD8_XPD_S  20
1864 /* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
1865 /*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
1866 #define RTC_IO_TOUCH_PAD8_TO_GPIO  (BIT(19))
1867 #define RTC_IO_TOUCH_PAD8_TO_GPIO_M  (BIT(19))
1868 #define RTC_IO_TOUCH_PAD8_TO_GPIO_V  0x1
1869 #define RTC_IO_TOUCH_PAD8_TO_GPIO_S  19
1870 
1871 #define RTC_IO_TOUCH_PAD9_REG          (DR_REG_RTCIO_BASE + 0xb8)
1872 /* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
1873 /*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
1874 #define RTC_IO_TOUCH_PAD9_DAC  0x00000007
1875 #define RTC_IO_TOUCH_PAD9_DAC_M  ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S))
1876 #define RTC_IO_TOUCH_PAD9_DAC_V  0x7
1877 #define RTC_IO_TOUCH_PAD9_DAC_S  23
1878 /* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
1879 /*description: start touch sensor.*/
1880 #define RTC_IO_TOUCH_PAD9_START  (BIT(22))
1881 #define RTC_IO_TOUCH_PAD9_START_M  (BIT(22))
1882 #define RTC_IO_TOUCH_PAD9_START_V  0x1
1883 #define RTC_IO_TOUCH_PAD9_START_S  22
1884 /* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
1885 /*description: default touch sensor tie option. 0: tie low  1: tie high.*/
1886 #define RTC_IO_TOUCH_PAD9_TIE_OPT  (BIT(21))
1887 #define RTC_IO_TOUCH_PAD9_TIE_OPT_M  (BIT(21))
1888 #define RTC_IO_TOUCH_PAD9_TIE_OPT_V  0x1
1889 #define RTC_IO_TOUCH_PAD9_TIE_OPT_S  21
1890 /* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
1891 /*description: touch sensor power on.*/
1892 #define RTC_IO_TOUCH_PAD9_XPD  (BIT(20))
1893 #define RTC_IO_TOUCH_PAD9_XPD_M  (BIT(20))
1894 #define RTC_IO_TOUCH_PAD9_XPD_V  0x1
1895 #define RTC_IO_TOUCH_PAD9_XPD_S  20
1896 /* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
1897 /*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
1898 #define RTC_IO_TOUCH_PAD9_TO_GPIO  (BIT(19))
1899 #define RTC_IO_TOUCH_PAD9_TO_GPIO_M  (BIT(19))
1900 #define RTC_IO_TOUCH_PAD9_TO_GPIO_V  0x1
1901 #define RTC_IO_TOUCH_PAD9_TO_GPIO_S  19
1902 
1903 #define RTC_IO_EXT_WAKEUP0_REG          (DR_REG_RTCIO_BASE + 0xbc)
1904 /* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
1905 /*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/
1906 #define RTC_IO_EXT_WAKEUP0_SEL  0x0000001F
1907 #define RTC_IO_EXT_WAKEUP0_SEL_M  ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))
1908 #define RTC_IO_EXT_WAKEUP0_SEL_V  0x1F
1909 #define RTC_IO_EXT_WAKEUP0_SEL_S  27
1910 
1911 #define RTC_IO_XTL_EXT_CTR_REG          (DR_REG_RTCIO_BASE + 0xc0)
1912 /* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
1913 /*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select
1914  GPIO2 ...Ò17Ó select GPIO17*/
1915 #define RTC_IO_XTL_EXT_CTR_SEL  0x0000001F
1916 #define RTC_IO_XTL_EXT_CTR_SEL_M  ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S))
1917 #define RTC_IO_XTL_EXT_CTR_SEL_V  0x1F
1918 #define RTC_IO_XTL_EXT_CTR_SEL_S  27
1919 
1920 #define RTC_IO_SAR_I2C_IO_REG          (DR_REG_RTCIO_BASE + 0xc4)
1921 /* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
1922 /*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/
1923 #define RTC_IO_SAR_I2C_SDA_SEL  0x00000003
1924 #define RTC_IO_SAR_I2C_SDA_SEL_M  ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S))
1925 #define RTC_IO_SAR_I2C_SDA_SEL_V  0x3
1926 #define RTC_IO_SAR_I2C_SDA_SEL_S  30
1927 /* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
1928 /*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/
1929 #define RTC_IO_SAR_I2C_SCL_SEL  0x00000003
1930 #define RTC_IO_SAR_I2C_SCL_SEL_M  ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S))
1931 #define RTC_IO_SAR_I2C_SCL_SEL_V  0x3
1932 #define RTC_IO_SAR_I2C_SCL_SEL_S  28
1933 /* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */
1934 /*description: */
1935 #define RTC_IO_SAR_DEBUG_BIT_SEL  0x0000001F
1936 #define RTC_IO_SAR_DEBUG_BIT_SEL_M  ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S))
1937 #define RTC_IO_SAR_DEBUG_BIT_SEL_V  0x1F
1938 #define RTC_IO_SAR_DEBUG_BIT_SEL_S  23
1939 
1940 #define RTC_IO_DATE_REG          (DR_REG_RTCIO_BASE + 0xc8)
1941 /* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */
1942 /*description: date*/
1943 #define RTC_IO_IO_DATE  0x0FFFFFFF
1944 #define RTC_IO_IO_DATE_M  ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S))
1945 #define RTC_IO_IO_DATE_V  0xFFFFFFF
1946 #define RTC_IO_IO_DATE_S  0
1947 #define RTC_IO_RTC_IO_DATE_VERSION 0x1703160
1948 
1949 
1950 
1951 
1952 #endif /*_SOC_RTC_IO_REG_H_ */
1953