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Searched refs:IO_MUX_GPIO0_REG (Results 1 – 23 of 23) sorted by relevance

/hal_espressif-3.7.0/components/hal/esp32c6/include/hal/
Dgpio_ll.h49 REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); in gpio_ll_pullup_en()
61 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); in gpio_ll_pullup_dis()
72 REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); in gpio_ll_pulldown_en()
93 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); in gpio_ll_pulldown_dis()
194 PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_disable()
205 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_enable()
216 PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_enable()
227 PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_disable()
343 SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S); in gpio_ll_set_drive_capability()
355 …*strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN… in gpio_ll_get_drive_capability()
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/hal_espressif-3.7.0/components/hal/esp32h2/include/hal/
Dgpio_ll.h48 REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); in gpio_ll_pullup_en()
60 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); in gpio_ll_pullup_dis()
71 REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); in gpio_ll_pulldown_en()
92 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); in gpio_ll_pulldown_dis()
193 PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_disable()
204 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_enable()
215 PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_enable()
226 PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_disable()
237 PIN_HYS_EN_SEL_EFUSE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_input_hysteresis_ctrl_sel_efuse()
248 PIN_HYS_EN_SEL_SOFT(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_input_hysteresis_ctrl_sel_soft()
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/hal_espressif-3.7.0/components/hal/esp32s2/include/hal/
Dgpio_ll.h56 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); in gpio_ll_pullup_dis()
79 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); in gpio_ll_pulldown_dis()
179 PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_disable()
190 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_enable()
201 PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_enable()
212 PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_disable()
281 PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); in gpio_ll_func_sel()
463 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4)); in gpio_ll_iomux_in()
/hal_espressif-3.7.0/components/hal/esp32s3/include/hal/
Dgpio_ll.h65 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); in gpio_ll_pullup_dis()
88 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); in gpio_ll_pulldown_dis()
192 PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_disable()
203 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_enable()
214 PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_enable()
225 PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_disable()
297 PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); in gpio_ll_func_sel()
479 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4)); in gpio_ll_iomux_in()
/hal_espressif-3.7.0/components/hal/esp32c2/include/hal/
Dgpio_ll.h54 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); in gpio_ll_pullup_dis()
77 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); in gpio_ll_pulldown_dis()
177 PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_disable()
188 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_enable()
199 PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_enable()
210 PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_disable()
270 PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); in gpio_ll_func_sel()
448 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4)); in gpio_ll_iomux_in()
/hal_espressif-3.7.0/components/hal/esp32c3/include/hal/
Dgpio_ll.h62 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); in gpio_ll_pullup_dis()
85 REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); in gpio_ll_pulldown_dis()
185 PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_disable()
196 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_input_enable()
207 PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_enable()
218 PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4)); in gpio_ll_pin_filter_disable()
282 PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); in gpio_ll_func_sel()
460 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4)); in gpio_ll_iomux_in()
/hal_espressif-3.7.0/components/soc/esp32c2/
Dgpio_periph.c10 IO_MUX_GPIO0_REG,
/hal_espressif-3.7.0/components/soc/esp32c3/
Dgpio_periph.c10 IO_MUX_GPIO0_REG,
/hal_espressif-3.7.0/components/soc/esp32/
Dgpio_periph.c11 IO_MUX_GPIO0_REG,
/hal_espressif-3.7.0/components/soc/esp32h2/
Dgpio_periph.c10 IO_MUX_GPIO0_REG,
/hal_espressif-3.7.0/components/soc/esp32c6/
Dgpio_periph.c10 IO_MUX_GPIO0_REG,
/hal_espressif-3.7.0/components/soc/esp32s2/
Dgpio_periph.c10 IO_MUX_GPIO0_REG,
/hal_espressif-3.7.0/components/soc/esp32s3/
Dgpio_periph.c10 IO_MUX_GPIO0_REG,
/hal_espressif-3.7.0/components/esp_hw_support/port/esp32c2/
Drtc_clk.c37 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG); in rtc_clk_32k_enable_external()
/hal_espressif-3.7.0/components/soc/esp32c3/include/soc/
Dio_mux_reg.h96 #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U macro
/hal_espressif-3.7.0/components/esp_hw_support/port/esp32c6/
Drtc_clk.c52 PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG); in rtc_clk_32k_enable_external()
/hal_espressif-3.7.0/components/soc/esp32c2/include/soc/
Dio_mux_reg.h97 #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U macro
/hal_espressif-3.7.0/components/hal/include/hal/
Dgpio_types.h22 #define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG
/hal_espressif-3.7.0/components/soc/esp32/include/soc/
Dio_mux_reg.h111 #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U macro
/hal_espressif-3.7.0/components/soc/esp32h2/include/soc/
Dio_mux_reg.h116 #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U macro
/hal_espressif-3.7.0/components/soc/esp32c6/include/soc/
Dio_mux_reg.h94 #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U macro
/hal_espressif-3.7.0/components/soc/esp32s3/include/soc/
Dio_mux_reg.h94 #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U macro
/hal_espressif-3.7.0/components/soc/esp32s2/include/soc/
Dio_mux_reg.h95 #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U macro