1 // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #ifndef _SOC_EXTMEM_REG_H_
15 #define _SOC_EXTMEM_REG_H_
16 
17 
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21 #include "soc.h"
22 #define EXTMEM_PRO_DCACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x000)
23 /* EXTMEM_PRO_DCACHE_LOCK_DONE : RO ;bitpos:[25] ;default: 1'b0 ; */
24 /*description: The bit is used to indicate lock operation is finished.*/
25 #define EXTMEM_PRO_DCACHE_LOCK_DONE  (BIT(25))
26 #define EXTMEM_PRO_DCACHE_LOCK_DONE_M  (BIT(25))
27 #define EXTMEM_PRO_DCACHE_LOCK_DONE_V  0x1
28 #define EXTMEM_PRO_DCACHE_LOCK_DONE_S  25
29 /* EXTMEM_PRO_DCACHE_LOCK_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
30 /*description: The bit is used to enable lock operation. It will be cleared
31  by hardware after lock operation done.*/
32 #define EXTMEM_PRO_DCACHE_LOCK_ENA  (BIT(24))
33 #define EXTMEM_PRO_DCACHE_LOCK_ENA_M  (BIT(24))
34 #define EXTMEM_PRO_DCACHE_LOCK_ENA_V  0x1
35 #define EXTMEM_PRO_DCACHE_LOCK_ENA_S  24
36 /* EXTMEM_PRO_DCACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */
37 /*description: The bit is used to indicate unlock operation is finished.*/
38 #define EXTMEM_PRO_DCACHE_UNLOCK_DONE  (BIT(23))
39 #define EXTMEM_PRO_DCACHE_UNLOCK_DONE_M  (BIT(23))
40 #define EXTMEM_PRO_DCACHE_UNLOCK_DONE_V  0x1
41 #define EXTMEM_PRO_DCACHE_UNLOCK_DONE_S  23
42 /* EXTMEM_PRO_DCACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
43 /*description: The bit is used to enable unlock operation. It will be cleared
44  by hardware after unlock operation done.*/
45 #define EXTMEM_PRO_DCACHE_UNLOCK_ENA  (BIT(22))
46 #define EXTMEM_PRO_DCACHE_UNLOCK_ENA_M  (BIT(22))
47 #define EXTMEM_PRO_DCACHE_UNLOCK_ENA_V  0x1
48 #define EXTMEM_PRO_DCACHE_UNLOCK_ENA_S  22
49 /* EXTMEM_PRO_DCACHE_PRELOAD_DONE : RO ;bitpos:[21] ;default: 1'b0 ; */
50 /*description: The bit is used to indicate preload operation is finished.*/
51 #define EXTMEM_PRO_DCACHE_PRELOAD_DONE  (BIT(21))
52 #define EXTMEM_PRO_DCACHE_PRELOAD_DONE_M  (BIT(21))
53 #define EXTMEM_PRO_DCACHE_PRELOAD_DONE_V  0x1
54 #define EXTMEM_PRO_DCACHE_PRELOAD_DONE_S  21
55 /* EXTMEM_PRO_DCACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
56 /*description: The bit is used to enable preload operation. It will be cleared
57  by hardware after preload operation done.*/
58 #define EXTMEM_PRO_DCACHE_PRELOAD_ENA  (BIT(20))
59 #define EXTMEM_PRO_DCACHE_PRELOAD_ENA_M  (BIT(20))
60 #define EXTMEM_PRO_DCACHE_PRELOAD_ENA_V  0x1
61 #define EXTMEM_PRO_DCACHE_PRELOAD_ENA_S  20
62 /* EXTMEM_PRO_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b0 ; */
63 /*description: The bit is used to indicate conditional-preload operation is finished.*/
64 #define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE  (BIT(19))
65 #define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_M  (BIT(19))
66 #define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_V  0x1
67 #define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_S  19
68 /* EXTMEM_PRO_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
69 /*description: The bit is used to enable and disable conditional-preload operation.
70  It is combined with pre_dcache_autoload_done. 1: enable  0: disable.*/
71 #define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA  (BIT(18))
72 #define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_M  (BIT(18))
73 #define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_V  0x1
74 #define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_S  18
75 /* EXTMEM_PRO_DCACHE_LOCK1_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
76 /*description: The bit is used to enable pre-lock operation which is combined
77  with PRO_DCACHE_LOCK1_ADDR_REG and PRO_DCACHE_LOCK1_SIZE_REG.*/
78 #define EXTMEM_PRO_DCACHE_LOCK1_EN  (BIT(15))
79 #define EXTMEM_PRO_DCACHE_LOCK1_EN_M  (BIT(15))
80 #define EXTMEM_PRO_DCACHE_LOCK1_EN_V  0x1
81 #define EXTMEM_PRO_DCACHE_LOCK1_EN_S  15
82 /* EXTMEM_PRO_DCACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
83 /*description: The bit is used to enable pre-lock operation which is combined
84  with PRO_DCACHE_LOCK0_ADDR_REG and PRO_DCACHE_LOCK0_SIZE_REG.*/
85 #define EXTMEM_PRO_DCACHE_LOCK0_EN  (BIT(14))
86 #define EXTMEM_PRO_DCACHE_LOCK0_EN_M  (BIT(14))
87 #define EXTMEM_PRO_DCACHE_LOCK0_EN_V  0x1
88 #define EXTMEM_PRO_DCACHE_LOCK0_EN_S  14
89 /* EXTMEM_PRO_DCACHE_CLEAN_DONE : RO ;bitpos:[13] ;default: 1'b0 ; */
90 /*description: The bit is used to indicate clean operation is finished.*/
91 #define EXTMEM_PRO_DCACHE_CLEAN_DONE  (BIT(13))
92 #define EXTMEM_PRO_DCACHE_CLEAN_DONE_M  (BIT(13))
93 #define EXTMEM_PRO_DCACHE_CLEAN_DONE_V  0x1
94 #define EXTMEM_PRO_DCACHE_CLEAN_DONE_S  13
95 /* EXTMEM_PRO_DCACHE_CLEAN_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
96 /*description: The bit is used to enable clean operation. It will be cleared
97  by hardware after clean operation done.*/
98 #define EXTMEM_PRO_DCACHE_CLEAN_ENA  (BIT(12))
99 #define EXTMEM_PRO_DCACHE_CLEAN_ENA_M  (BIT(12))
100 #define EXTMEM_PRO_DCACHE_CLEAN_ENA_V  0x1
101 #define EXTMEM_PRO_DCACHE_CLEAN_ENA_S  12
102 /* EXTMEM_PRO_DCACHE_FLUSH_DONE : RO ;bitpos:[11] ;default: 1'b0 ; */
103 /*description: The bit is used to indicate flush operation is finished.*/
104 #define EXTMEM_PRO_DCACHE_FLUSH_DONE  (BIT(11))
105 #define EXTMEM_PRO_DCACHE_FLUSH_DONE_M  (BIT(11))
106 #define EXTMEM_PRO_DCACHE_FLUSH_DONE_V  0x1
107 #define EXTMEM_PRO_DCACHE_FLUSH_DONE_S  11
108 /* EXTMEM_PRO_DCACHE_FLUSH_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
109 /*description: The bit is used to enable flush operation. It will be cleared
110  by hardware after flush operation done.*/
111 #define EXTMEM_PRO_DCACHE_FLUSH_ENA  (BIT(10))
112 #define EXTMEM_PRO_DCACHE_FLUSH_ENA_M  (BIT(10))
113 #define EXTMEM_PRO_DCACHE_FLUSH_ENA_V  0x1
114 #define EXTMEM_PRO_DCACHE_FLUSH_ENA_S  10
115 /* EXTMEM_PRO_DCACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */
116 /*description: The bit is used to indicate invalidate operation is finished.*/
117 #define EXTMEM_PRO_DCACHE_INVALIDATE_DONE  (BIT(9))
118 #define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_M  (BIT(9))
119 #define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_V  0x1
120 #define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_S  9
121 /* EXTMEM_PRO_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[8] ;default: 1'b1 ; */
122 /*description: The bit is used to enable invalidate operation. It will be cleared
123  by hardware after invalidate operation done.*/
124 #define EXTMEM_PRO_DCACHE_INVALIDATE_ENA  (BIT(8))
125 #define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_M  (BIT(8))
126 #define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_V  0x1
127 #define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_S  8
128 /* EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
129 /*description: The bit is used to configure cache block size.0: 16 bytes  1: 32 bytes*/
130 #define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE  (BIT(3))
131 #define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_M  (BIT(3))
132 #define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_V  0x1
133 #define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_S  3
134 /* EXTMEM_PRO_DCACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
135 /*description: The bit is used to configure cache memory size.0: 8KB  1: 16KB*/
136 #define EXTMEM_PRO_DCACHE_SETSIZE_MODE  (BIT(2))
137 #define EXTMEM_PRO_DCACHE_SETSIZE_MODE_M  (BIT(2))
138 #define EXTMEM_PRO_DCACHE_SETSIZE_MODE_V  0x1
139 #define EXTMEM_PRO_DCACHE_SETSIZE_MODE_S  2
140 /* EXTMEM_PRO_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
141 /*description: The bit is used to activate the data cache. 0: disable  1: enable*/
142 #define EXTMEM_PRO_DCACHE_ENABLE  (BIT(0))
143 #define EXTMEM_PRO_DCACHE_ENABLE_M  (BIT(0))
144 #define EXTMEM_PRO_DCACHE_ENABLE_V  0x1
145 #define EXTMEM_PRO_DCACHE_ENABLE_S  0
146 
147 #define EXTMEM_PRO_DCACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x004)
148 /* EXTMEM_PRO_DCACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */
149 /*description: The bit is used to disable dbus2  0: enable  1: disable*/
150 #define EXTMEM_PRO_DCACHE_MASK_BUS2  (BIT(2))
151 #define EXTMEM_PRO_DCACHE_MASK_BUS2_M  (BIT(2))
152 #define EXTMEM_PRO_DCACHE_MASK_BUS2_V  0x1
153 #define EXTMEM_PRO_DCACHE_MASK_BUS2_S  2
154 /* EXTMEM_PRO_DCACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
155 /*description: The bit is used to disable dbus1  0: enable  1: disable*/
156 #define EXTMEM_PRO_DCACHE_MASK_BUS1  (BIT(1))
157 #define EXTMEM_PRO_DCACHE_MASK_BUS1_M  (BIT(1))
158 #define EXTMEM_PRO_DCACHE_MASK_BUS1_V  0x1
159 #define EXTMEM_PRO_DCACHE_MASK_BUS1_S  1
160 /* EXTMEM_PRO_DCACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
161 /*description: The bit is used to disable dbus0  0: enable  1: disable*/
162 #define EXTMEM_PRO_DCACHE_MASK_BUS0  (BIT(0))
163 #define EXTMEM_PRO_DCACHE_MASK_BUS0_M  (BIT(0))
164 #define EXTMEM_PRO_DCACHE_MASK_BUS0_V  0x1
165 #define EXTMEM_PRO_DCACHE_MASK_BUS0_S  0
166 #define EXTMEM_PRO_DCACHE_MASK_DRAM0 EXTMEM_PRO_DCACHE_MASK_BUS0
167 #define EXTMEM_PRO_DCACHE_MASK_DRAM1 EXTMEM_PRO_DCACHE_MASK_BUS1
168 #define EXTMEM_PRO_DCACHE_MASK_DPORT EXTMEM_PRO_DCACHE_MASK_BUS2
169 
170 #define EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x008)
171 /* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
172 /*description: The bit is used to power dcache tag memory down  0: follow  rtc_lslp_pd
173   1: power up*/
174 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU  (BIT(2))
175 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_M  (BIT(2))
176 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_V  0x1
177 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_S  2
178 /* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
179 /*description: The bit is used to power dcache tag memory down  0: follow  rtc_lslp_pd
180   1: power down*/
181 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD  (BIT(1))
182 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_M  (BIT(1))
183 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_V  0x1
184 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_S  1
185 /* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
186 /*description: The bit is used to close clock gating of dcache tag memory. 1:
187  close gating  0: open clock gating.*/
188 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON  (BIT(0))
189 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
190 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_V  0x1
191 #define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_S  0
192 
193 #define EXTMEM_PRO_DCACHE_LOCK0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x00C)
194 /* EXTMEM_PRO_DCACHE_LOCK0_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
195 /*description: The bits are used to configure the first start virtual address
196  of data locking  which is combined with PRO_DCACHE_LOCK0_SIZE_REG*/
197 #define EXTMEM_PRO_DCACHE_LOCK0_ADDR  0xFFFFFFFF
198 #define EXTMEM_PRO_DCACHE_LOCK0_ADDR_M  ((EXTMEM_PRO_DCACHE_LOCK0_ADDR_V)<<(EXTMEM_PRO_DCACHE_LOCK0_ADDR_S))
199 #define EXTMEM_PRO_DCACHE_LOCK0_ADDR_V  0xFFFFFFFF
200 #define EXTMEM_PRO_DCACHE_LOCK0_ADDR_S  0
201 
202 #define EXTMEM_PRO_DCACHE_LOCK0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x010)
203 /* EXTMEM_PRO_DCACHE_LOCK0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
204 /*description: The bits are used to configure the first length of data locking
205   which is combined with PRO_DCACHE_LOCK0_ADDR_REG*/
206 #define EXTMEM_PRO_DCACHE_LOCK0_SIZE  0x0000FFFF
207 #define EXTMEM_PRO_DCACHE_LOCK0_SIZE_M  ((EXTMEM_PRO_DCACHE_LOCK0_SIZE_V)<<(EXTMEM_PRO_DCACHE_LOCK0_SIZE_S))
208 #define EXTMEM_PRO_DCACHE_LOCK0_SIZE_V  0xFFFF
209 #define EXTMEM_PRO_DCACHE_LOCK0_SIZE_S  0
210 
211 #define EXTMEM_PRO_DCACHE_LOCK1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x014)
212 /* EXTMEM_PRO_DCACHE_LOCK1_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
213 /*description: The bits are used to configure the second start virtual address
214  of data locking  which is combined with PRO_DCACHE_LOCK1_SIZE_REG*/
215 #define EXTMEM_PRO_DCACHE_LOCK1_ADDR  0xFFFFFFFF
216 #define EXTMEM_PRO_DCACHE_LOCK1_ADDR_M  ((EXTMEM_PRO_DCACHE_LOCK1_ADDR_V)<<(EXTMEM_PRO_DCACHE_LOCK1_ADDR_S))
217 #define EXTMEM_PRO_DCACHE_LOCK1_ADDR_V  0xFFFFFFFF
218 #define EXTMEM_PRO_DCACHE_LOCK1_ADDR_S  0
219 
220 #define EXTMEM_PRO_DCACHE_LOCK1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x018)
221 /* EXTMEM_PRO_DCACHE_LOCK1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
222 /*description: The bits are used to configure the second length of data locking
223   which is combined with PRO_DCACHE_LOCK1_ADDR_REG*/
224 #define EXTMEM_PRO_DCACHE_LOCK1_SIZE  0x0000FFFF
225 #define EXTMEM_PRO_DCACHE_LOCK1_SIZE_M  ((EXTMEM_PRO_DCACHE_LOCK1_SIZE_V)<<(EXTMEM_PRO_DCACHE_LOCK1_SIZE_S))
226 #define EXTMEM_PRO_DCACHE_LOCK1_SIZE_V  0xFFFF
227 #define EXTMEM_PRO_DCACHE_LOCK1_SIZE_S  0
228 
229 #define EXTMEM_PRO_DCACHE_MEM_SYNC0_REG          (DR_REG_EXTMEM_BASE + 0x01C)
230 /* EXTMEM_PRO_DCACHE_MEMSYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
231 /*description: The bits are used to configure the start virtual address for
232  invalidate  flush  clean  lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC1.*/
233 #define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR  0xFFFFFFFF
234 #define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_M  ((EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_V)<<(EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_S))
235 #define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_V  0xFFFFFFFF
236 #define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_S  0
237 
238 #define EXTMEM_PRO_DCACHE_MEM_SYNC1_REG          (DR_REG_EXTMEM_BASE + 0x020)
239 /* EXTMEM_PRO_DCACHE_MEMSYNC_SIZE : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
240 /*description: The bits are used to configure the length for invalidate  flush
241   clean  lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC0.*/
242 #define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE  0x0007FFFF
243 #define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_M  ((EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_V)<<(EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_S))
244 #define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_V  0x7FFFF
245 #define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_S  0
246 
247 #define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x024)
248 /* EXTMEM_PRO_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
249 /*description: The bits are used to configure the start virtual address for
250  manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_SIZE_REG.*/
251 #define EXTMEM_PRO_DCACHE_PRELOAD_ADDR  0xFFFFFFFF
252 #define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_M  ((EXTMEM_PRO_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_PRO_DCACHE_PRELOAD_ADDR_S))
253 #define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_V  0xFFFFFFFF
254 #define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_S  0
255 
256 #define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x028)
257 /* EXTMEM_PRO_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */
258 /*description: The bits are used to configure the direction of manual pre-load
259  operation. 1: descending  0: ascending.*/
260 #define EXTMEM_PRO_DCACHE_PRELOAD_ORDER  (BIT(10))
261 #define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_M  (BIT(10))
262 #define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_V  0x1
263 #define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_S  10
264 /* EXTMEM_PRO_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[9:0] ;default: 10'h200 ; */
265 /*description: The bits are used to configure the length for manual pre-load
266  operation.  It should be combined with PRO_DCACHE_PRELOAD_ADDR_REG..*/
267 #define EXTMEM_PRO_DCACHE_PRELOAD_SIZE  0x000003FF
268 #define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_M  ((EXTMEM_PRO_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_PRO_DCACHE_PRELOAD_SIZE_S))
269 #define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_V  0x3FF
270 #define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_S  0
271 
272 #define EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_REG          (DR_REG_EXTMEM_BASE + 0x02C)
273 /* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
274 /*description: The bits are used to enable the first section for conditional
275  pre-load operation.*/
276 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA  (BIT(9))
277 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_M  (BIT(9))
278 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_V  0x1
279 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_S  9
280 /* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
281 /*description: The bits are used to enable the second section for conditional
282  pre-load operation.*/
283 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA  (BIT(8))
284 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_M  (BIT(8))
285 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_V  0x1
286 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_S  8
287 /* EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
288 /*description: The bits are used to configure the numbers of the cache block
289  for the issuing conditional pre-load operation.*/
290 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE  0x00000003
291 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_M  ((EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_S))
292 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_V  0x3
293 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_S  6
294 /* EXTMEM_PRO_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ;default: 1'b0 ; */
295 /*description: The bits are used to configure trigger conditions for conditional
296  pre-load. 0/3: cache miss  1: cache hit  2: both cache miss and hit.*/
297 #define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST  0x00000003
298 #define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_M  ((EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_S))
299 #define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_V  0x3
300 #define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_S  4
301 /* EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[3] ;default: 1'b0 ; */
302 /*description: The bits are used to configure the direction of conditional pre-load
303  operation. 1: descending  0: ascending.*/
304 #define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER  (BIT(3))
305 #define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_M  (BIT(3))
306 #define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_V  0x1
307 #define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_S  3
308 /* EXTMEM_PRO_DCACHE_AUTOLOAD_STEP : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
309 /*description: Reserved.*/
310 #define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP  0x00000003
311 #define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_M  ((EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_S))
312 #define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_V  0x3
313 #define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_S  1
314 /* EXTMEM_PRO_DCACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;default: 1'd0 ; */
315 /*description: Reserved.*/
316 #define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE  (BIT(0))
317 #define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_M  (BIT(0))
318 #define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_V  0x1
319 #define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_S  0
320 
321 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x030)
322 /* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
323 /*description: The bits are used to configure the start virtual address of the
324  first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena.*/
325 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR  0xFFFFFFFF
326 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S))
327 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
328 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S  0
329 
330 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x034)
331 /* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
332 /*description: The bits are used to configure the length of the first section
333  for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena.*/
334 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE  0x00FFFFFF
335 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S))
336 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFF
337 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S  0
338 
339 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x038)
340 /* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
341 /*description: The bits are used to configure the start virtual address of the
342  second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena.*/
343 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR  0xFFFFFFFF
344 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S))
345 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
346 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S  0
347 
348 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x03C)
349 /* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
350 /*description: The bits are used to configure the length of the second section
351  for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena.*/
352 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE  0x00FFFFFF
353 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S))
354 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFF
355 #define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S  0
356 
357 #define EXTMEM_PRO_ICACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x040)
358 /* EXTMEM_PRO_ICACHE_LOCK_DONE : RO ;bitpos:[25] ;default: 1'b0 ; */
359 /*description: The bit is used to indicate lock operation is finished.*/
360 #define EXTMEM_PRO_ICACHE_LOCK_DONE  (BIT(25))
361 #define EXTMEM_PRO_ICACHE_LOCK_DONE_M  (BIT(25))
362 #define EXTMEM_PRO_ICACHE_LOCK_DONE_V  0x1
363 #define EXTMEM_PRO_ICACHE_LOCK_DONE_S  25
364 /* EXTMEM_PRO_ICACHE_LOCK_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
365 /*description: The bit is used to enable lock operation. It will be cleared
366  by hardware after lock operation done.*/
367 #define EXTMEM_PRO_ICACHE_LOCK_ENA  (BIT(24))
368 #define EXTMEM_PRO_ICACHE_LOCK_ENA_M  (BIT(24))
369 #define EXTMEM_PRO_ICACHE_LOCK_ENA_V  0x1
370 #define EXTMEM_PRO_ICACHE_LOCK_ENA_S  24
371 /* EXTMEM_PRO_ICACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */
372 /*description: The bit is used to indicate unlock operation is finished.*/
373 #define EXTMEM_PRO_ICACHE_UNLOCK_DONE  (BIT(23))
374 #define EXTMEM_PRO_ICACHE_UNLOCK_DONE_M  (BIT(23))
375 #define EXTMEM_PRO_ICACHE_UNLOCK_DONE_V  0x1
376 #define EXTMEM_PRO_ICACHE_UNLOCK_DONE_S  23
377 /* EXTMEM_PRO_ICACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
378 /*description: The bit is used to enable unlock operation. It will be cleared
379  by hardware after unlock operation done.*/
380 #define EXTMEM_PRO_ICACHE_UNLOCK_ENA  (BIT(22))
381 #define EXTMEM_PRO_ICACHE_UNLOCK_ENA_M  (BIT(22))
382 #define EXTMEM_PRO_ICACHE_UNLOCK_ENA_V  0x1
383 #define EXTMEM_PRO_ICACHE_UNLOCK_ENA_S  22
384 /* EXTMEM_PRO_ICACHE_PRELOAD_DONE : RO ;bitpos:[21] ;default: 1'b0 ; */
385 /*description: The bit is used to indicate preload operation is finished.*/
386 #define EXTMEM_PRO_ICACHE_PRELOAD_DONE  (BIT(21))
387 #define EXTMEM_PRO_ICACHE_PRELOAD_DONE_M  (BIT(21))
388 #define EXTMEM_PRO_ICACHE_PRELOAD_DONE_V  0x1
389 #define EXTMEM_PRO_ICACHE_PRELOAD_DONE_S  21
390 /* EXTMEM_PRO_ICACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
391 /*description: The bit is used to enable preload operation. It will be cleared
392  by hardware after preload operation done.*/
393 #define EXTMEM_PRO_ICACHE_PRELOAD_ENA  (BIT(20))
394 #define EXTMEM_PRO_ICACHE_PRELOAD_ENA_M  (BIT(20))
395 #define EXTMEM_PRO_ICACHE_PRELOAD_ENA_V  0x1
396 #define EXTMEM_PRO_ICACHE_PRELOAD_ENA_S  20
397 /* EXTMEM_PRO_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b0 ; */
398 /*description: The bit is used to indicate conditional-preload operation is finished.*/
399 #define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE  (BIT(19))
400 #define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_M  (BIT(19))
401 #define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_V  0x1
402 #define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_S  19
403 /* EXTMEM_PRO_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
404 /*description: The bit is used to enable and disable conditional-preload operation.
405  It is combined with pre_dcache_autoload_done. 1: enable  0: disable.*/
406 #define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA  (BIT(18))
407 #define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_M  (BIT(18))
408 #define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_V  0x1
409 #define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_S  18
410 /* EXTMEM_PRO_ICACHE_LOCK1_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
411 /*description: The bit is used to enable pre-lock operation which is combined
412  with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG.*/
413 #define EXTMEM_PRO_ICACHE_LOCK1_EN  (BIT(15))
414 #define EXTMEM_PRO_ICACHE_LOCK1_EN_M  (BIT(15))
415 #define EXTMEM_PRO_ICACHE_LOCK1_EN_V  0x1
416 #define EXTMEM_PRO_ICACHE_LOCK1_EN_S  15
417 /* EXTMEM_PRO_ICACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
418 /*description: The bit is used to enable pre-lock operation which is combined
419  with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG.*/
420 #define EXTMEM_PRO_ICACHE_LOCK0_EN  (BIT(14))
421 #define EXTMEM_PRO_ICACHE_LOCK0_EN_M  (BIT(14))
422 #define EXTMEM_PRO_ICACHE_LOCK0_EN_V  0x1
423 #define EXTMEM_PRO_ICACHE_LOCK0_EN_S  14
424 /* EXTMEM_PRO_ICACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */
425 /*description: The bit is used to indicate invalidate operation is finished.*/
426 #define EXTMEM_PRO_ICACHE_INVALIDATE_DONE  (BIT(9))
427 #define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_M  (BIT(9))
428 #define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_V  0x1
429 #define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_S  9
430 /* EXTMEM_PRO_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[8] ;default: 1'b1 ; */
431 /*description: The bit is used to enable invalidate operation. It will be cleared
432  by hardware after invalidate operation done.*/
433 #define EXTMEM_PRO_ICACHE_INVALIDATE_ENA  (BIT(8))
434 #define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_M  (BIT(8))
435 #define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_V  0x1
436 #define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_S  8
437 /* EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
438 /*description: The bit is used to configure cache block size.0: 16 bytes  1: 32 bytes*/
439 #define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE  (BIT(3))
440 #define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_M  (BIT(3))
441 #define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_V  0x1
442 #define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_S  3
443 /* EXTMEM_PRO_ICACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
444 /*description: The bit is used to configure cache memory size.0: 8KB  1: 16KB*/
445 #define EXTMEM_PRO_ICACHE_SETSIZE_MODE  (BIT(2))
446 #define EXTMEM_PRO_ICACHE_SETSIZE_MODE_M  (BIT(2))
447 #define EXTMEM_PRO_ICACHE_SETSIZE_MODE_V  0x1
448 #define EXTMEM_PRO_ICACHE_SETSIZE_MODE_S  2
449 /* EXTMEM_PRO_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
450 /*description: The bit is used to activate the data cache. 0: disable  1: enable*/
451 #define EXTMEM_PRO_ICACHE_ENABLE  (BIT(0))
452 #define EXTMEM_PRO_ICACHE_ENABLE_M  (BIT(0))
453 #define EXTMEM_PRO_ICACHE_ENABLE_V  0x1
454 #define EXTMEM_PRO_ICACHE_ENABLE_S  0
455 
456 #define EXTMEM_PRO_ICACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x044)
457 /* EXTMEM_PRO_ICACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */
458 /*description: The bit is used to disable ibus2  0: enable  1: disable*/
459 #define EXTMEM_PRO_ICACHE_MASK_BUS2  (BIT(2))
460 #define EXTMEM_PRO_ICACHE_MASK_BUS2_M  (BIT(2))
461 #define EXTMEM_PRO_ICACHE_MASK_BUS2_V  0x1
462 #define EXTMEM_PRO_ICACHE_MASK_BUS2_S  2
463 /* EXTMEM_PRO_ICACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
464 /*description: The bit is used to disable ibus1  0: enable  1: disable*/
465 #define EXTMEM_PRO_ICACHE_MASK_BUS1  (BIT(1))
466 #define EXTMEM_PRO_ICACHE_MASK_BUS1_M  (BIT(1))
467 #define EXTMEM_PRO_ICACHE_MASK_BUS1_V  0x1
468 #define EXTMEM_PRO_ICACHE_MASK_BUS1_S  1
469 /* EXTMEM_PRO_ICACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
470 /*description: The bit is used to disable ibus0  0: enable  1: disable*/
471 #define EXTMEM_PRO_ICACHE_MASK_BUS0  (BIT(0))
472 #define EXTMEM_PRO_ICACHE_MASK_BUS0_M  (BIT(0))
473 #define EXTMEM_PRO_ICACHE_MASK_BUS0_V  0x1
474 #define EXTMEM_PRO_ICACHE_MASK_BUS0_S  0
475 #define EXTMEM_PRO_ICACHE_MASK_IRAM0 EXTMEM_PRO_ICACHE_MASK_BUS0
476 #define EXTMEM_PRO_ICACHE_MASK_IRAM1 EXTMEM_PRO_ICACHE_MASK_BUS1
477 #define EXTMEM_PRO_ICACHE_MASK_DROM0 EXTMEM_PRO_ICACHE_MASK_BUS2
478 
479 #define EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x048)
480 /* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
481 /*description: The bit is used to power icache tag memory down  0: follow rtc_lslp  1: power up*/
482 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU  (BIT(2))
483 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_M  (BIT(2))
484 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_V  0x1
485 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_S  2
486 /* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
487 /*description: The bit is used to power icache tag memory down  0: follow rtc_lslp
488   1: power down*/
489 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD  (BIT(1))
490 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_M  (BIT(1))
491 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_V  0x1
492 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_S  1
493 /* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
494 /*description: The bit is used to close clock gating of icache tag memory. 1:
495  close gating  0: open clock gating.*/
496 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON  (BIT(0))
497 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
498 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_V  0x1
499 #define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_S  0
500 
501 #define EXTMEM_PRO_ICACHE_LOCK0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x04C)
502 /* EXTMEM_PRO_ICACHE_LOCK0_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
503 /*description: The bits are used to configure the first start virtual address
504  of data locking  which is combined with PRO_ICACHE_LOCK0_SIZE_REG*/
505 #define EXTMEM_PRO_ICACHE_LOCK0_ADDR  0xFFFFFFFF
506 #define EXTMEM_PRO_ICACHE_LOCK0_ADDR_M  ((EXTMEM_PRO_ICACHE_LOCK0_ADDR_V)<<(EXTMEM_PRO_ICACHE_LOCK0_ADDR_S))
507 #define EXTMEM_PRO_ICACHE_LOCK0_ADDR_V  0xFFFFFFFF
508 #define EXTMEM_PRO_ICACHE_LOCK0_ADDR_S  0
509 
510 #define EXTMEM_PRO_ICACHE_LOCK0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x050)
511 /* EXTMEM_PRO_ICACHE_LOCK0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
512 /*description: The bits are used to configure the first length of data locking
513   which is combined with PRO_ICACHE_LOCK0_ADDR_REG*/
514 #define EXTMEM_PRO_ICACHE_LOCK0_SIZE  0x0000FFFF
515 #define EXTMEM_PRO_ICACHE_LOCK0_SIZE_M  ((EXTMEM_PRO_ICACHE_LOCK0_SIZE_V)<<(EXTMEM_PRO_ICACHE_LOCK0_SIZE_S))
516 #define EXTMEM_PRO_ICACHE_LOCK0_SIZE_V  0xFFFF
517 #define EXTMEM_PRO_ICACHE_LOCK0_SIZE_S  0
518 
519 #define EXTMEM_PRO_ICACHE_LOCK1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x054)
520 /* EXTMEM_PRO_ICACHE_LOCK1_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
521 /*description: The bits are used to configure the second start virtual address
522  of data locking  which is combined with PRO_ICACHE_LOCK1_SIZE_REG*/
523 #define EXTMEM_PRO_ICACHE_LOCK1_ADDR  0xFFFFFFFF
524 #define EXTMEM_PRO_ICACHE_LOCK1_ADDR_M  ((EXTMEM_PRO_ICACHE_LOCK1_ADDR_V)<<(EXTMEM_PRO_ICACHE_LOCK1_ADDR_S))
525 #define EXTMEM_PRO_ICACHE_LOCK1_ADDR_V  0xFFFFFFFF
526 #define EXTMEM_PRO_ICACHE_LOCK1_ADDR_S  0
527 
528 #define EXTMEM_PRO_ICACHE_LOCK1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x058)
529 /* EXTMEM_PRO_ICACHE_LOCK1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
530 /*description: The bits are used to configure the second length of data locking
531   which is combined with PRO_ICACHE_LOCK1_ADDR_REG*/
532 #define EXTMEM_PRO_ICACHE_LOCK1_SIZE  0x0000FFFF
533 #define EXTMEM_PRO_ICACHE_LOCK1_SIZE_M  ((EXTMEM_PRO_ICACHE_LOCK1_SIZE_V)<<(EXTMEM_PRO_ICACHE_LOCK1_SIZE_S))
534 #define EXTMEM_PRO_ICACHE_LOCK1_SIZE_V  0xFFFF
535 #define EXTMEM_PRO_ICACHE_LOCK1_SIZE_S  0
536 
537 #define EXTMEM_PRO_ICACHE_MEM_SYNC0_REG          (DR_REG_EXTMEM_BASE + 0x05C)
538 /* EXTMEM_PRO_ICACHE_MEMSYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
539 /*description: The bits are used to configure the start virtual address for
540  invalidate  flush  clean  lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC1.*/
541 #define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR  0xFFFFFFFF
542 #define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_M  ((EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_V)<<(EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_S))
543 #define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_V  0xFFFFFFFF
544 #define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_S  0
545 
546 #define EXTMEM_PRO_ICACHE_MEM_SYNC1_REG          (DR_REG_EXTMEM_BASE + 0x060)
547 /* EXTMEM_PRO_ICACHE_MEMSYNC_SIZE : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
548 /*description: The bits are used to configure the length for invalidate  flush
549   clean  lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC0.*/
550 #define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE  0x0007FFFF
551 #define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_M  ((EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_V)<<(EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_S))
552 #define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_V  0x7FFFF
553 #define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_S  0
554 
555 #define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x064)
556 /* EXTMEM_PRO_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
557 /*description: The bits are used to configure the start virtual address for
558  manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_SIZE_REG.*/
559 #define EXTMEM_PRO_ICACHE_PRELOAD_ADDR  0xFFFFFFFF
560 #define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_M  ((EXTMEM_PRO_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_S))
561 #define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_V  0xFFFFFFFF
562 #define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_S  0
563 
564 #define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x068)
565 /* EXTMEM_PRO_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */
566 /*description: The bits are used to configure the direction of manual pre-load
567  operation. 1: descending  0: ascending.*/
568 #define EXTMEM_PRO_ICACHE_PRELOAD_ORDER  (BIT(10))
569 #define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_M  (BIT(10))
570 #define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_V  0x1
571 #define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_S  10
572 /* EXTMEM_PRO_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[9:0] ;default: 10'h200 ; */
573 /*description: The bits are used to configure the length for manual pre-load
574  operation.  It should be combined with PRO_ICACHE_PRELOAD_ADDR_REG..*/
575 #define EXTMEM_PRO_ICACHE_PRELOAD_SIZE  0x000003FF
576 #define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_M  ((EXTMEM_PRO_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_S))
577 #define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_V  0x3FF
578 #define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_S  0
579 
580 #define EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_REG          (DR_REG_EXTMEM_BASE + 0x06C)
581 /* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
582 /*description: The bits are used to enable the first section for conditional
583  pre-load operation.*/
584 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA  (BIT(9))
585 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_M  (BIT(9))
586 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_V  0x1
587 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_S  9
588 /* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
589 /*description: The bits are used to enable the second section for conditional
590  pre-load operation.*/
591 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA  (BIT(8))
592 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_M  (BIT(8))
593 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_V  0x1
594 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_S  8
595 /* EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
596 /*description: The bits are used to configure the numbers of the cache block
597  for the issuing conditional pre-load operation.*/
598 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE  0x00000003
599 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_M  ((EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_S))
600 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_V  0x3
601 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_S  6
602 /* EXTMEM_PRO_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ;default: 1'b0 ; */
603 /*description: The bits are used to configure trigger conditions for conditional
604  pre-load. 0/3: cache miss  1: cache hit  2: both cache miss and hit.*/
605 #define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST  0x00000003
606 #define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_M  ((EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_S))
607 #define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_V  0x3
608 #define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_S  4
609 /* EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[3] ;default: 1'b0 ; */
610 /*description: The bits are used to configure the direction of conditional pre-load
611  operation. 1: descending  0: ascending.*/
612 #define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER  (BIT(3))
613 #define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_M  (BIT(3))
614 #define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_V  0x1
615 #define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_S  3
616 /* EXTMEM_PRO_ICACHE_AUTOLOAD_STEP : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
617 /*description: Reserved.*/
618 #define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP  0x00000003
619 #define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_M  ((EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_S))
620 #define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_V  0x3
621 #define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_S  1
622 /* EXTMEM_PRO_ICACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;default: 1'd0 ; */
623 /*description: Reserved.*/
624 #define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE  (BIT(0))
625 #define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_M  (BIT(0))
626 #define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_V  0x1
627 #define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_S  0
628 
629 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x070)
630 /* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
631 /*description: The bits are used to configure the start virtual address of the
632  first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena.*/
633 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR  0xFFFFFFFF
634 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S))
635 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
636 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S  0
637 
638 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x074)
639 /* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
640 /*description: The bits are used to configure the length of the first section
641  for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena.*/
642 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE  0x00FFFFFF
643 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S))
644 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFF
645 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S  0
646 
647 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x078)
648 /* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
649 /*description: The bits are used to configure the start virtual address of the
650  second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena.*/
651 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR  0xFFFFFFFF
652 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S))
653 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
654 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S  0
655 
656 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x07C)
657 /* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
658 /*description: The bits are used to configure the length of the second section
659  for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena.*/
660 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE  0x00FFFFFF
661 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S))
662 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFF
663 #define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S  0
664 
665 #define EXTMEM_IC_PRELOAD_CNT_REG          (DR_REG_EXTMEM_BASE + 0x080)
666 /* EXTMEM_IC_PRELOAD_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
667 /*description: The bits are used to count the number of issued pre-load which
668  include manual pre-load and conditional pre-load.*/
669 #define EXTMEM_IC_PRELOAD_CNT  0x0000FFFF
670 #define EXTMEM_IC_PRELOAD_CNT_M  ((EXTMEM_IC_PRELOAD_CNT_V)<<(EXTMEM_IC_PRELOAD_CNT_S))
671 #define EXTMEM_IC_PRELOAD_CNT_V  0xFFFF
672 #define EXTMEM_IC_PRELOAD_CNT_S  0
673 
674 #define EXTMEM_IC_PRELOAD_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x084)
675 /* EXTMEM_IC_PRELOAD_MISS_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
676 /*description: The bits are used to count the number of missed pre-load which
677  include manual pre-load and conditional pre-load.*/
678 #define EXTMEM_IC_PRELOAD_MISS_CNT  0x0000FFFF
679 #define EXTMEM_IC_PRELOAD_MISS_CNT_M  ((EXTMEM_IC_PRELOAD_MISS_CNT_V)<<(EXTMEM_IC_PRELOAD_MISS_CNT_S))
680 #define EXTMEM_IC_PRELOAD_MISS_CNT_V  0xFFFF
681 #define EXTMEM_IC_PRELOAD_MISS_CNT_S  0
682 
683 #define EXTMEM_IBUS2_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x088)
684 /* EXTMEM_IBUS2_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
685 /*description: The bits are used to count the number of the abandoned ibus2 access.*/
686 #define EXTMEM_IBUS2_ABANDON_CNT  0x0000FFFF
687 #define EXTMEM_IBUS2_ABANDON_CNT_M  ((EXTMEM_IBUS2_ABANDON_CNT_V)<<(EXTMEM_IBUS2_ABANDON_CNT_S))
688 #define EXTMEM_IBUS2_ABANDON_CNT_V  0xFFFF
689 #define EXTMEM_IBUS2_ABANDON_CNT_S  0
690 
691 #define EXTMEM_IBUS1_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x08C)
692 /* EXTMEM_IBUS1_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
693 /*description: The bits are used to count the number of the abandoned ibus1 access.*/
694 #define EXTMEM_IBUS1_ABANDON_CNT  0x0000FFFF
695 #define EXTMEM_IBUS1_ABANDON_CNT_M  ((EXTMEM_IBUS1_ABANDON_CNT_V)<<(EXTMEM_IBUS1_ABANDON_CNT_S))
696 #define EXTMEM_IBUS1_ABANDON_CNT_V  0xFFFF
697 #define EXTMEM_IBUS1_ABANDON_CNT_S  0
698 
699 #define EXTMEM_IBUS0_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x090)
700 /* EXTMEM_IBUS0_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
701 /*description: The bits are used to count the number of the abandoned ibus0 access.*/
702 #define EXTMEM_IBUS0_ABANDON_CNT  0x0000FFFF
703 #define EXTMEM_IBUS0_ABANDON_CNT_M  ((EXTMEM_IBUS0_ABANDON_CNT_V)<<(EXTMEM_IBUS0_ABANDON_CNT_S))
704 #define EXTMEM_IBUS0_ABANDON_CNT_V  0xFFFF
705 #define EXTMEM_IBUS0_ABANDON_CNT_S  0
706 
707 #define EXTMEM_IBUS2_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x094)
708 /* EXTMEM_IBUS2_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
709 /*description: The bits are used to count the number of the cache miss caused by ibus2 access.*/
710 #define EXTMEM_IBUS2_ACS_MISS_CNT  0xFFFFFFFF
711 #define EXTMEM_IBUS2_ACS_MISS_CNT_M  ((EXTMEM_IBUS2_ACS_MISS_CNT_V)<<(EXTMEM_IBUS2_ACS_MISS_CNT_S))
712 #define EXTMEM_IBUS2_ACS_MISS_CNT_V  0xFFFFFFFF
713 #define EXTMEM_IBUS2_ACS_MISS_CNT_S  0
714 
715 #define EXTMEM_IBUS1_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x098)
716 /* EXTMEM_IBUS1_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
717 /*description: The bits are used to count the number of the cache miss caused by ibus1 access.*/
718 #define EXTMEM_IBUS1_ACS_MISS_CNT  0xFFFFFFFF
719 #define EXTMEM_IBUS1_ACS_MISS_CNT_M  ((EXTMEM_IBUS1_ACS_MISS_CNT_V)<<(EXTMEM_IBUS1_ACS_MISS_CNT_S))
720 #define EXTMEM_IBUS1_ACS_MISS_CNT_V  0xFFFFFFFF
721 #define EXTMEM_IBUS1_ACS_MISS_CNT_S  0
722 
723 #define EXTMEM_IBUS0_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x09C)
724 /* EXTMEM_IBUS0_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
725 /*description: The bits are used to count the number of the cache miss caused by ibus0 access.*/
726 #define EXTMEM_IBUS0_ACS_MISS_CNT  0xFFFFFFFF
727 #define EXTMEM_IBUS0_ACS_MISS_CNT_M  ((EXTMEM_IBUS0_ACS_MISS_CNT_V)<<(EXTMEM_IBUS0_ACS_MISS_CNT_S))
728 #define EXTMEM_IBUS0_ACS_MISS_CNT_V  0xFFFFFFFF
729 #define EXTMEM_IBUS0_ACS_MISS_CNT_S  0
730 
731 #define EXTMEM_IBUS2_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0A0)
732 /* EXTMEM_IBUS2_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
733 /*description: The bits are used to count the number of ibus2 access icache.*/
734 #define EXTMEM_IBUS2_ACS_CNT  0xFFFFFFFF
735 #define EXTMEM_IBUS2_ACS_CNT_M  ((EXTMEM_IBUS2_ACS_CNT_V)<<(EXTMEM_IBUS2_ACS_CNT_S))
736 #define EXTMEM_IBUS2_ACS_CNT_V  0xFFFFFFFF
737 #define EXTMEM_IBUS2_ACS_CNT_S  0
738 
739 #define EXTMEM_IBUS1_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0A4)
740 /* EXTMEM_IBUS1_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
741 /*description: The bits are used to count the number of ibus1 access icache.*/
742 #define EXTMEM_IBUS1_ACS_CNT  0xFFFFFFFF
743 #define EXTMEM_IBUS1_ACS_CNT_M  ((EXTMEM_IBUS1_ACS_CNT_V)<<(EXTMEM_IBUS1_ACS_CNT_S))
744 #define EXTMEM_IBUS1_ACS_CNT_V  0xFFFFFFFF
745 #define EXTMEM_IBUS1_ACS_CNT_S  0
746 
747 #define EXTMEM_IBUS0_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0A8)
748 /* EXTMEM_IBUS0_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
749 /*description: The bits are used to count the number of ibus0 access icache.*/
750 #define EXTMEM_IBUS0_ACS_CNT  0xFFFFFFFF
751 #define EXTMEM_IBUS0_ACS_CNT_M  ((EXTMEM_IBUS0_ACS_CNT_V)<<(EXTMEM_IBUS0_ACS_CNT_S))
752 #define EXTMEM_IBUS0_ACS_CNT_V  0xFFFFFFFF
753 #define EXTMEM_IBUS0_ACS_CNT_S  0
754 
755 #define EXTMEM_DC_PRELOAD_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0AC)
756 /* EXTMEM_DC_PRELOAD_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
757 /*description: The bits are used to count the number of issued pre-load which
758  include manual pre-load and conditional pre-load.*/
759 #define EXTMEM_DC_PRELOAD_CNT  0x0000FFFF
760 #define EXTMEM_DC_PRELOAD_CNT_M  ((EXTMEM_DC_PRELOAD_CNT_V)<<(EXTMEM_DC_PRELOAD_CNT_S))
761 #define EXTMEM_DC_PRELOAD_CNT_V  0xFFFF
762 #define EXTMEM_DC_PRELOAD_CNT_S  0
763 
764 #define EXTMEM_DC_PRELOAD_EVICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0B0)
765 /* EXTMEM_DC_PRELOAD_EVICT_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
766 /*description: The bits are used to count the number of cache evictions by pre-load
767  which include manual pre-load and conditional pre-load.*/
768 #define EXTMEM_DC_PRELOAD_EVICT_CNT  0x0000FFFF
769 #define EXTMEM_DC_PRELOAD_EVICT_CNT_M  ((EXTMEM_DC_PRELOAD_EVICT_CNT_V)<<(EXTMEM_DC_PRELOAD_EVICT_CNT_S))
770 #define EXTMEM_DC_PRELOAD_EVICT_CNT_V  0xFFFF
771 #define EXTMEM_DC_PRELOAD_EVICT_CNT_S  0
772 
773 #define EXTMEM_DC_PRELOAD_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0B4)
774 /* EXTMEM_DC_PRELOAD_MISS_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
775 /*description: The bits are used to count the number of missed pre-load which
776  include manual pre-load and conditional pre-load.*/
777 #define EXTMEM_DC_PRELOAD_MISS_CNT  0x0000FFFF
778 #define EXTMEM_DC_PRELOAD_MISS_CNT_M  ((EXTMEM_DC_PRELOAD_MISS_CNT_V)<<(EXTMEM_DC_PRELOAD_MISS_CNT_S))
779 #define EXTMEM_DC_PRELOAD_MISS_CNT_V  0xFFFF
780 #define EXTMEM_DC_PRELOAD_MISS_CNT_S  0
781 
782 #define EXTMEM_DBUS2_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0B8)
783 /* EXTMEM_DBUS2_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
784 /*description: The bits are used to count the number of the abandoned dbus2 access.*/
785 #define EXTMEM_DBUS2_ABANDON_CNT  0x0000FFFF
786 #define EXTMEM_DBUS2_ABANDON_CNT_M  ((EXTMEM_DBUS2_ABANDON_CNT_V)<<(EXTMEM_DBUS2_ABANDON_CNT_S))
787 #define EXTMEM_DBUS2_ABANDON_CNT_V  0xFFFF
788 #define EXTMEM_DBUS2_ABANDON_CNT_S  0
789 
790 #define EXTMEM_DBUS1_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0BC)
791 /* EXTMEM_DBUS1_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
792 /*description: The bits are used to count the number of the abandoned dbus1 access.*/
793 #define EXTMEM_DBUS1_ABANDON_CNT  0x0000FFFF
794 #define EXTMEM_DBUS1_ABANDON_CNT_M  ((EXTMEM_DBUS1_ABANDON_CNT_V)<<(EXTMEM_DBUS1_ABANDON_CNT_S))
795 #define EXTMEM_DBUS1_ABANDON_CNT_V  0xFFFF
796 #define EXTMEM_DBUS1_ABANDON_CNT_S  0
797 
798 #define EXTMEM_DBUS0_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0C0)
799 /* EXTMEM_DBUS0_ABANDON_CNT : RO ;bitpos:[15:0] ;default: 16'h0 ; */
800 /*description: The bits are used to count the number of the abandoned dbus0 access.*/
801 #define EXTMEM_DBUS0_ABANDON_CNT  0x0000FFFF
802 #define EXTMEM_DBUS0_ABANDON_CNT_M  ((EXTMEM_DBUS0_ABANDON_CNT_V)<<(EXTMEM_DBUS0_ABANDON_CNT_S))
803 #define EXTMEM_DBUS0_ABANDON_CNT_V  0xFFFF
804 #define EXTMEM_DBUS0_ABANDON_CNT_S  0
805 
806 #define EXTMEM_DBUS2_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0C4)
807 /* EXTMEM_DBUS2_ACS_WB_CNT : RO ;bitpos:[19:0] ;default: 20'h0 ; */
808 /*description: The bits are used to count the number of cache evictions by dbus2 access cache.*/
809 #define EXTMEM_DBUS2_ACS_WB_CNT  0x000FFFFF
810 #define EXTMEM_DBUS2_ACS_WB_CNT_M  ((EXTMEM_DBUS2_ACS_WB_CNT_V)<<(EXTMEM_DBUS2_ACS_WB_CNT_S))
811 #define EXTMEM_DBUS2_ACS_WB_CNT_V  0xFFFFF
812 #define EXTMEM_DBUS2_ACS_WB_CNT_S  0
813 
814 #define EXTMEM_DBUS1_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0C8)
815 /* EXTMEM_DBUS1_ACS_WB_CNT : RO ;bitpos:[19:0] ;default: 20'h0 ; */
816 /*description: The bits are used to count the number of cache evictions by dbus1 access cache.*/
817 #define EXTMEM_DBUS1_ACS_WB_CNT  0x000FFFFF
818 #define EXTMEM_DBUS1_ACS_WB_CNT_M  ((EXTMEM_DBUS1_ACS_WB_CNT_V)<<(EXTMEM_DBUS1_ACS_WB_CNT_S))
819 #define EXTMEM_DBUS1_ACS_WB_CNT_V  0xFFFFF
820 #define EXTMEM_DBUS1_ACS_WB_CNT_S  0
821 
822 #define EXTMEM_DBUS0_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0CC)
823 /* EXTMEM_DBUS0_ACS_WB_CNT : RO ;bitpos:[19:0] ;default: 20'h0 ; */
824 /*description: The bits are used to count the number of cache evictions by dbus0 access cache.*/
825 #define EXTMEM_DBUS0_ACS_WB_CNT  0x000FFFFF
826 #define EXTMEM_DBUS0_ACS_WB_CNT_M  ((EXTMEM_DBUS0_ACS_WB_CNT_V)<<(EXTMEM_DBUS0_ACS_WB_CNT_S))
827 #define EXTMEM_DBUS0_ACS_WB_CNT_V  0xFFFFF
828 #define EXTMEM_DBUS0_ACS_WB_CNT_S  0
829 
830 #define EXTMEM_DBUS2_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0D0)
831 /* EXTMEM_DBUS2_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
832 /*description: The bits are used to count the number of the cache miss caused by dbus2 access.*/
833 #define EXTMEM_DBUS2_ACS_MISS_CNT  0xFFFFFFFF
834 #define EXTMEM_DBUS2_ACS_MISS_CNT_M  ((EXTMEM_DBUS2_ACS_MISS_CNT_V)<<(EXTMEM_DBUS2_ACS_MISS_CNT_S))
835 #define EXTMEM_DBUS2_ACS_MISS_CNT_V  0xFFFFFFFF
836 #define EXTMEM_DBUS2_ACS_MISS_CNT_S  0
837 
838 #define EXTMEM_DBUS1_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0D4)
839 /* EXTMEM_DBUS1_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
840 /*description: The bits are used to count the number of the cache miss caused by dbus1 access.*/
841 #define EXTMEM_DBUS1_ACS_MISS_CNT  0xFFFFFFFF
842 #define EXTMEM_DBUS1_ACS_MISS_CNT_M  ((EXTMEM_DBUS1_ACS_MISS_CNT_V)<<(EXTMEM_DBUS1_ACS_MISS_CNT_S))
843 #define EXTMEM_DBUS1_ACS_MISS_CNT_V  0xFFFFFFFF
844 #define EXTMEM_DBUS1_ACS_MISS_CNT_S  0
845 
846 #define EXTMEM_DBUS0_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0D8)
847 /* EXTMEM_DBUS0_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
848 /*description: The bits are used to count the number of the cache miss caused by dbus0 access.*/
849 #define EXTMEM_DBUS0_ACS_MISS_CNT  0xFFFFFFFF
850 #define EXTMEM_DBUS0_ACS_MISS_CNT_M  ((EXTMEM_DBUS0_ACS_MISS_CNT_V)<<(EXTMEM_DBUS0_ACS_MISS_CNT_S))
851 #define EXTMEM_DBUS0_ACS_MISS_CNT_V  0xFFFFFFFF
852 #define EXTMEM_DBUS0_ACS_MISS_CNT_S  0
853 
854 #define EXTMEM_DBUS2_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0DC)
855 /* EXTMEM_DBUS2_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
856 /*description: The bits are used to count the number of dbus2 access dcache.*/
857 #define EXTMEM_DBUS2_ACS_CNT  0xFFFFFFFF
858 #define EXTMEM_DBUS2_ACS_CNT_M  ((EXTMEM_DBUS2_ACS_CNT_V)<<(EXTMEM_DBUS2_ACS_CNT_S))
859 #define EXTMEM_DBUS2_ACS_CNT_V  0xFFFFFFFF
860 #define EXTMEM_DBUS2_ACS_CNT_S  0
861 
862 #define EXTMEM_DBUS1_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0E0)
863 /* EXTMEM_DBUS1_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
864 /*description: The bits are used to count the number of dbus1 access dcache.*/
865 #define EXTMEM_DBUS1_ACS_CNT  0xFFFFFFFF
866 #define EXTMEM_DBUS1_ACS_CNT_M  ((EXTMEM_DBUS1_ACS_CNT_V)<<(EXTMEM_DBUS1_ACS_CNT_S))
867 #define EXTMEM_DBUS1_ACS_CNT_V  0xFFFFFFFF
868 #define EXTMEM_DBUS1_ACS_CNT_S  0
869 
870 #define EXTMEM_DBUS0_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0E4)
871 /* EXTMEM_DBUS0_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
872 /*description: The bits are used to count the number of dbus0 access dcache.*/
873 #define EXTMEM_DBUS0_ACS_CNT  0xFFFFFFFF
874 #define EXTMEM_DBUS0_ACS_CNT_M  ((EXTMEM_DBUS0_ACS_CNT_V)<<(EXTMEM_DBUS0_ACS_CNT_S))
875 #define EXTMEM_DBUS0_ACS_CNT_V  0xFFFFFFFF
876 #define EXTMEM_DBUS0_ACS_CNT_S  0
877 
878 #define EXTMEM_CACHE_DBG_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x0E8)
879 /* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
880 /*description: The bit is used to enable interrupt by mmu entry fault.*/
881 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA  (BIT(19))
882 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M  (BIT(19))
883 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V  0x1
884 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S  19
885 /* EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
886 /*description: The bit is used to enable interrupt by illegal writing lock registers
887  of dcache while dcache is busy to issue lock sync or pre-load operations.*/
888 #define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA  (BIT(18))
889 #define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_M  (BIT(18))
890 #define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_V  0x1
891 #define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_S  18
892 /* EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
893 /*description: The bit is used to enable interrupt by illegal writing sync registers
894  of dcache while dcache is busy to issue lock sync and pre-load operations.*/
895 #define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA  (BIT(17))
896 #define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_M  (BIT(17))
897 #define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_V  0x1
898 #define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_S  17
899 /* EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
900 /*description: The bit is used to enable interrupt by illegal writing preload
901  registers of dcache while dcache is busy to issue lock sync and pre-load operations.*/
902 #define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA  (BIT(16))
903 #define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_M  (BIT(16))
904 #define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_V  0x1
905 #define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_S  16
906 /* EXTMEM_DCACHE_REJECT_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
907 /*description: The bit is used to enable interrupt by authentication fail.*/
908 #define EXTMEM_DCACHE_REJECT_INT_ENA  (BIT(15))
909 #define EXTMEM_DCACHE_REJECT_INT_ENA_M  (BIT(15))
910 #define EXTMEM_DCACHE_REJECT_INT_ENA_V  0x1
911 #define EXTMEM_DCACHE_REJECT_INT_ENA_S  15
912 /* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
913 /*description: The bit is used to enable interrupt by dcache trying to write flash.*/
914 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA  (BIT(14))
915 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M  (BIT(14))
916 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V  0x1
917 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S  14
918 /* EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
919 /*description: The bit is used to enable interrupt by manual pre-load configurations fault.*/
920 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA  (BIT(13))
921 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_M  (BIT(13))
922 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_V  0x1
923 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_S  13
924 /* EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
925 /*description: The bit is used to enable interrupt by manual sync configurations fault.*/
926 #define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA  (BIT(12))
927 #define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_M  (BIT(12))
928 #define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_V  0x1
929 #define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_S  12
930 /* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
931 /*description: The bit is used to enable interrupt by dbus counter overflow.*/
932 #define EXTMEM_DBUS_CNT_OVF_INT_ENA  (BIT(11))
933 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_M  (BIT(11))
934 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_V  0x1
935 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_S  11
936 /* EXTMEM_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
937 /*description: The bit is used to enable interrupt by cpu access dcache while
938  the corresponding dbus is disabled which include speculative access.*/
939 #define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA  (BIT(10))
940 #define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_M  (BIT(10))
941 #define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_V  0x1
942 #define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_S  10
943 /* EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
944 /*description: The bit is used to enable interrupt by illegal writing lock registers
945  of icache while icache is busy to issue lock sync or pre-load operations.*/
946 #define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA  (BIT(9))
947 #define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_M  (BIT(9))
948 #define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_V  0x1
949 #define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_S  9
950 /* EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
951 /*description: The bit is used to enable interrupt by illegal writing sync registers
952  of icache while icache is busy to issue lock sync and pre-load operations.*/
953 #define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA  (BIT(8))
954 #define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_M  (BIT(8))
955 #define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_V  0x1
956 #define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_S  8
957 /* EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
958 /*description: The bit is used to enable interrupt by illegal writing preload
959  registers of icache while icache is busy to issue lock sync and pre-load operations.*/
960 #define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA  (BIT(7))
961 #define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_M  (BIT(7))
962 #define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_V  0x1
963 #define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_S  7
964 /* EXTMEM_ICACHE_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
965 /*description: The bit is used to enable interrupt by authentication fail.*/
966 #define EXTMEM_ICACHE_REJECT_INT_ENA  (BIT(6))
967 #define EXTMEM_ICACHE_REJECT_INT_ENA_M  (BIT(6))
968 #define EXTMEM_ICACHE_REJECT_INT_ENA_V  0x1
969 #define EXTMEM_ICACHE_REJECT_INT_ENA_S  6
970 /* EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
971 /*description: The bit is used to enable interrupt by manual pre-load configurations fault.*/
972 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA  (BIT(5))
973 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_M  (BIT(5))
974 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_V  0x1
975 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_S  5
976 /* EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
977 /*description: The bit is used to enable interrupt by manual sync configurations fault.*/
978 #define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA  (BIT(4))
979 #define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_M  (BIT(4))
980 #define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_V  0x1
981 #define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_S  4
982 /* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
983 /*description: The bit is used to enable interrupt by ibus counter overflow.*/
984 #define EXTMEM_IBUS_CNT_OVF_INT_ENA  (BIT(3))
985 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_M  (BIT(3))
986 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_V  0x1
987 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_S  3
988 /* EXTMEM_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
989 /*description: The bit is used to enable interrupt by cpu access icache while
990  the corresponding ibus is disabled which include speculative access.*/
991 #define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA  (BIT(2))
992 #define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(2))
993 #define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
994 #define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_S  2
995 /* EXTMEM_CACHE_DBG_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
996 /*description: The bit is used to activate the cache track function. 1: enable  0: disable.*/
997 #define EXTMEM_CACHE_DBG_EN  (BIT(0))
998 #define EXTMEM_CACHE_DBG_EN_M  (BIT(0))
999 #define EXTMEM_CACHE_DBG_EN_V  0x1
1000 #define EXTMEM_CACHE_DBG_EN_S  0
1001 
1002 #define EXTMEM_CACHE_DBG_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x0EC)
1003 /* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[13] ;default: 1'b0 ; */
1004 /*description: The bit is used to clear interrupt by mmu entry fault.*/
1005 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR  (BIT(13))
1006 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M  (BIT(13))
1007 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V  0x1
1008 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S  13
1009 /* EXTMEM_DCACHE_SET_ILG_INT_CLR : WOD ;bitpos:[12] ;default: 1'b0 ; */
1010 /*description: The bit is used to clear interrupt by illegal writing lock registers
1011  of dcache while dcache is busy to issue lock sync or pre-load operations.*/
1012 #define EXTMEM_DCACHE_SET_ILG_INT_CLR  (BIT(12))
1013 #define EXTMEM_DCACHE_SET_ILG_INT_CLR_M  (BIT(12))
1014 #define EXTMEM_DCACHE_SET_ILG_INT_CLR_V  0x1
1015 #define EXTMEM_DCACHE_SET_ILG_INT_CLR_S  12
1016 /* EXTMEM_DCACHE_REJECT_INT_CLR : WOD ;bitpos:[11] ;default: 1'b0 ; */
1017 /*description: The bit is used to clear interrupt by authentication fail.*/
1018 #define EXTMEM_DCACHE_REJECT_INT_CLR  (BIT(11))
1019 #define EXTMEM_DCACHE_REJECT_INT_CLR_M  (BIT(11))
1020 #define EXTMEM_DCACHE_REJECT_INT_CLR_V  0x1
1021 #define EXTMEM_DCACHE_REJECT_INT_CLR_S  11
1022 /* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD ;bitpos:[10] ;default: 1'b0 ; */
1023 /*description: The bit is used to clear interrupt by dcache trying to write flash.*/
1024 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR  (BIT(10))
1025 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M  (BIT(10))
1026 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V  0x1
1027 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S  10
1028 /* EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR : WOD ;bitpos:[9] ;default: 1'b0 ; */
1029 /*description: The bit is used to clear interrupt by manual pre-load configurations fault.*/
1030 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR  (BIT(9))
1031 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_M  (BIT(9))
1032 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_V  0x1
1033 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_S  9
1034 /* EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */
1035 /*description: The bit is used to clear interrupt by manual sync configurations fault.*/
1036 #define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR  (BIT(8))
1037 #define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_M  (BIT(8))
1038 #define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_V  0x1
1039 #define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_S  8
1040 /* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */
1041 /*description: The bit is used to clear interrupt by dbus counter overflow.*/
1042 #define EXTMEM_DBUS_CNT_OVF_INT_CLR  (BIT(7))
1043 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_M  (BIT(7))
1044 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_V  0x1
1045 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_S  7
1046 /* EXTMEM_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */
1047 /*description: The bit is used to clear interrupt by cpu access dcache while
1048  the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
1049 #define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR  (BIT(6))
1050 #define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_M  (BIT(6))
1051 #define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_V  0x1
1052 #define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_S  6
1053 /* EXTMEM_ICACHE_SET_ILG_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
1054 /*description: The bit is used to clear interrupt by illegal writing lock registers
1055  of icache while icache is busy to issue lock sync or pre-load operations.*/
1056 #define EXTMEM_ICACHE_SET_ILG_INT_CLR  (BIT(5))
1057 #define EXTMEM_ICACHE_SET_ILG_INT_CLR_M  (BIT(5))
1058 #define EXTMEM_ICACHE_SET_ILG_INT_CLR_V  0x1
1059 #define EXTMEM_ICACHE_SET_ILG_INT_CLR_S  5
1060 /* EXTMEM_ICACHE_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
1061 /*description: The bit is used to clear interrupt by authentication fail.*/
1062 #define EXTMEM_ICACHE_REJECT_INT_CLR  (BIT(4))
1063 #define EXTMEM_ICACHE_REJECT_INT_CLR_M  (BIT(4))
1064 #define EXTMEM_ICACHE_REJECT_INT_CLR_V  0x1
1065 #define EXTMEM_ICACHE_REJECT_INT_CLR_S  4
1066 /* EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
1067 /*description: The bit is used to clear interrupt by manual pre-load configurations fault.*/
1068 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR  (BIT(3))
1069 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_M  (BIT(3))
1070 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_V  0x1
1071 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_S  3
1072 /* EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
1073 /*description: The bit is used to clear interrupt by manual sync configurations fault.*/
1074 #define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR  (BIT(2))
1075 #define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_M  (BIT(2))
1076 #define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_V  0x1
1077 #define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_S  2
1078 /* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
1079 /*description: The bit is used to clear interrupt by ibus counter overflow.*/
1080 #define EXTMEM_IBUS_CNT_OVF_INT_CLR  (BIT(1))
1081 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_M  (BIT(1))
1082 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_V  0x1
1083 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_S  1
1084 /* EXTMEM_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
1085 /*description: The bit is used to clear interrupt by cpu access icache while
1086  the corresponding ibus is disabled or icache is disabled which include speculative access.*/
1087 #define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR  (BIT(0))
1088 #define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_M  (BIT(0))
1089 #define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_V  0x1
1090 #define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_S  0
1091 
1092 #define EXTMEM_CACHE_DBG_STATUS0_REG          (DR_REG_EXTMEM_BASE + 0x0F0)
1093 /* EXTMEM_ICACHE_SET_LOCK_ILG_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
1094 /*description: The bit is used to indicate interrupt by illegal writing lock
1095  registers of icache while icache is busy to issue lock sync or pre-load operations.*/
1096 #define EXTMEM_ICACHE_SET_LOCK_ILG_ST  (BIT(24))
1097 #define EXTMEM_ICACHE_SET_LOCK_ILG_ST_M  (BIT(24))
1098 #define EXTMEM_ICACHE_SET_LOCK_ILG_ST_V  0x1
1099 #define EXTMEM_ICACHE_SET_LOCK_ILG_ST_S  24
1100 /* EXTMEM_ICACHE_SET_SYNC_ILG_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
1101 /*description: The bit is used to indicate interrupt by illegal writing sync
1102  registers of icache while icache is busy to issue lock sync and pre-load operations.*/
1103 #define EXTMEM_ICACHE_SET_SYNC_ILG_ST  (BIT(23))
1104 #define EXTMEM_ICACHE_SET_SYNC_ILG_ST_M  (BIT(23))
1105 #define EXTMEM_ICACHE_SET_SYNC_ILG_ST_V  0x1
1106 #define EXTMEM_ICACHE_SET_SYNC_ILG_ST_S  23
1107 /* EXTMEM_ICACHE_SET_PRELOAD_ILG_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
1108 /*description: The bit is used to indicate interrupt by illegal writing preload
1109  registers of icache while icache is busy to issue lock sync and pre-load operations.*/
1110 #define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST  (BIT(22))
1111 #define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_M  (BIT(22))
1112 #define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_V  0x1
1113 #define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_S  22
1114 /* EXTMEM_ICACHE_REJECT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
1115 /*description: The bit is used to indicate interrupt by authentication fail.*/
1116 #define EXTMEM_ICACHE_REJECT_ST  (BIT(21))
1117 #define EXTMEM_ICACHE_REJECT_ST_M  (BIT(21))
1118 #define EXTMEM_ICACHE_REJECT_ST_V  0x1
1119 #define EXTMEM_ICACHE_REJECT_ST_S  21
1120 /* EXTMEM_IC_PRELOAD_SIZE_FAULT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
1121 /*description: The bit is used to indicate interrupt by manual pre-load configurations fault.*/
1122 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST  (BIT(20))
1123 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_M  (BIT(20))
1124 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_V  0x1
1125 #define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_S  20
1126 /* EXTMEM_IC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
1127 /*description: The bit is used to indicate interrupt by manual sync configurations fault.*/
1128 #define EXTMEM_IC_SYNC_SIZE_FAULT_ST  (BIT(19))
1129 #define EXTMEM_IC_SYNC_SIZE_FAULT_ST_M  (BIT(19))
1130 #define EXTMEM_IC_SYNC_SIZE_FAULT_ST_V  0x1
1131 #define EXTMEM_IC_SYNC_SIZE_FAULT_ST_S  19
1132 /* EXTMEM_IC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
1133 /*description: The bit is used to indicate interrupt by pre-load counter overflow.*/
1134 #define EXTMEM_IC_PRELOAD_CNT_OVF_ST  (BIT(18))
1135 #define EXTMEM_IC_PRELOAD_CNT_OVF_ST_M  (BIT(18))
1136 #define EXTMEM_IC_PRELOAD_CNT_OVF_ST_V  0x1
1137 #define EXTMEM_IC_PRELOAD_CNT_OVF_ST_S  18
1138 /* EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
1139 /*description: The bit is used to indicate interrupt by pre-load miss counter overflow.*/
1140 #define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST  (BIT(16))
1141 #define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_M  (BIT(16))
1142 #define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_V  0x1
1143 #define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_S  16
1144 /* EXTMEM_IBUS2_ABANDON_CNT_OVF_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
1145 /*description: The bit is used to indicate interrupt by ibus2 abandon counter overflow.*/
1146 #define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST  (BIT(14))
1147 #define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_M  (BIT(14))
1148 #define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_V  0x1
1149 #define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_S  14
1150 /* EXTMEM_IBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
1151 /*description: The bit is used to indicate interrupt by ibus1 abandon counter overflow.*/
1152 #define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST  (BIT(13))
1153 #define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_M  (BIT(13))
1154 #define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_V  0x1
1155 #define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_S  13
1156 /* EXTMEM_IBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
1157 /*description: The bit is used to indicate interrupt by ibus0 abandon counter overflow.*/
1158 #define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST  (BIT(12))
1159 #define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_M  (BIT(12))
1160 #define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_V  0x1
1161 #define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_S  12
1162 /* EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
1163 /*description: The bit is used to indicate interrupt by ibus2 miss counter overflow.*/
1164 #define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST  (BIT(10))
1165 #define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_M  (BIT(10))
1166 #define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_V  0x1
1167 #define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_S  10
1168 /* EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
1169 /*description: The bit is used to indicate interrupt by ibus1 miss counter overflow.*/
1170 #define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST  (BIT(9))
1171 #define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_M  (BIT(9))
1172 #define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_V  0x1
1173 #define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_S  9
1174 /* EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
1175 /*description: The bit is used to indicate interrupt by ibus0 miss counter overflow.*/
1176 #define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST  (BIT(8))
1177 #define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
1178 #define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_V  0x1
1179 #define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_S  8
1180 /* EXTMEM_IBUS2_ACS_CNT_OVF_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
1181 /*description: The bit is used to indicate interrupt by ibus2 counter overflow.*/
1182 #define EXTMEM_IBUS2_ACS_CNT_OVF_ST  (BIT(6))
1183 #define EXTMEM_IBUS2_ACS_CNT_OVF_ST_M  (BIT(6))
1184 #define EXTMEM_IBUS2_ACS_CNT_OVF_ST_V  0x1
1185 #define EXTMEM_IBUS2_ACS_CNT_OVF_ST_S  6
1186 /* EXTMEM_IBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
1187 /*description: The bit is used to indicate interrupt by ibus1 counter overflow.*/
1188 #define EXTMEM_IBUS1_ACS_CNT_OVF_ST  (BIT(5))
1189 #define EXTMEM_IBUS1_ACS_CNT_OVF_ST_M  (BIT(5))
1190 #define EXTMEM_IBUS1_ACS_CNT_OVF_ST_V  0x1
1191 #define EXTMEM_IBUS1_ACS_CNT_OVF_ST_S  5
1192 /* EXTMEM_IBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
1193 /*description: The bit is used to indicate interrupt by ibus0 counter overflow.*/
1194 #define EXTMEM_IBUS0_ACS_CNT_OVF_ST  (BIT(4))
1195 #define EXTMEM_IBUS0_ACS_CNT_OVF_ST_M  (BIT(4))
1196 #define EXTMEM_IBUS0_ACS_CNT_OVF_ST_V  0x1
1197 #define EXTMEM_IBUS0_ACS_CNT_OVF_ST_S  4
1198 /* EXTMEM_IBUS2_ACS_MSK_ICACHE_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
1199 /*description: The bit is used to indicate interrupt by cpu access icache while
1200  the ibus2 is disabled or icache is disabled which include speculative access.*/
1201 #define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST  (BIT(2))
1202 #define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_M  (BIT(2))
1203 #define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_V  0x1
1204 #define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_S  2
1205 /* EXTMEM_IBUS1_ACS_MSK_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
1206 /*description: The bit is used to indicate interrupt by cpu access icache while
1207  the ibus1 is disabled or icache is disabled which include speculative access.*/
1208 #define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST  (BIT(1))
1209 #define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_M  (BIT(1))
1210 #define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_V  0x1
1211 #define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_S  1
1212 /* EXTMEM_IBUS0_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
1213 /*description: The bit is used to indicate interrupt by cpu access icache while
1214  the ibus0 is disabled or icache is disabled which include speculative access.*/
1215 #define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST  (BIT(0))
1216 #define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_M  (BIT(0))
1217 #define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_V  0x1
1218 #define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_S  0
1219 
1220 #define EXTMEM_CACHE_DBG_STATUS1_REG          (DR_REG_EXTMEM_BASE + 0x0F4)
1221 /* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
1222 /*description: The bit is used to indicate interrupt by mmu entry fault.*/
1223 #define EXTMEM_MMU_ENTRY_FAULT_ST  (BIT(30))
1224 #define EXTMEM_MMU_ENTRY_FAULT_ST_M  (BIT(30))
1225 #define EXTMEM_MMU_ENTRY_FAULT_ST_V  0x1
1226 #define EXTMEM_MMU_ENTRY_FAULT_ST_S  30
1227 /* EXTMEM_DCACHE_SET_LOCK_ILG_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
1228 /*description: The bit is used to indicate interrupt by illegal writing lock
1229  registers of icache while icache is busy to issue lock sync or pre-load operations.*/
1230 #define EXTMEM_DCACHE_SET_LOCK_ILG_ST  (BIT(29))
1231 #define EXTMEM_DCACHE_SET_LOCK_ILG_ST_M  (BIT(29))
1232 #define EXTMEM_DCACHE_SET_LOCK_ILG_ST_V  0x1
1233 #define EXTMEM_DCACHE_SET_LOCK_ILG_ST_S  29
1234 /* EXTMEM_DCACHE_SET_SYNC_ILG_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
1235 /*description: The bit is used to indicate interrupt by illegal writing sync
1236  registers of icache while icache is busy to issue lock sync and pre-load operations.*/
1237 #define EXTMEM_DCACHE_SET_SYNC_ILG_ST  (BIT(28))
1238 #define EXTMEM_DCACHE_SET_SYNC_ILG_ST_M  (BIT(28))
1239 #define EXTMEM_DCACHE_SET_SYNC_ILG_ST_V  0x1
1240 #define EXTMEM_DCACHE_SET_SYNC_ILG_ST_S  28
1241 /* EXTMEM_DCACHE_SET_PRELOAD_ILG_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
1242 /*description: The bit is used to indicate interrupt by illegal writing preload
1243  registers of icache while icache is busy to issue lock sync and pre-load operations.*/
1244 #define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST  (BIT(27))
1245 #define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_M  (BIT(27))
1246 #define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_V  0x1
1247 #define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_S  27
1248 /* EXTMEM_DCACHE_REJECT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
1249 /*description: The bit is used to indicate interrupt by authentication fail.*/
1250 #define EXTMEM_DCACHE_REJECT_ST  (BIT(26))
1251 #define EXTMEM_DCACHE_REJECT_ST_M  (BIT(26))
1252 #define EXTMEM_DCACHE_REJECT_ST_V  0x1
1253 #define EXTMEM_DCACHE_REJECT_ST_S  26
1254 /* EXTMEM_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
1255 /*description: The bit is used to indicate interrupt by dcache trying to write flash.*/
1256 #define EXTMEM_DCACHE_WRITE_FLASH_ST  (BIT(25))
1257 #define EXTMEM_DCACHE_WRITE_FLASH_ST_M  (BIT(25))
1258 #define EXTMEM_DCACHE_WRITE_FLASH_ST_V  0x1
1259 #define EXTMEM_DCACHE_WRITE_FLASH_ST_S  25
1260 /* EXTMEM_DC_PRELOAD_SIZE_FAULT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
1261 /*description: The bit is used to indicate interrupt by manual pre-load configurations fault.*/
1262 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST  (BIT(24))
1263 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_M  (BIT(24))
1264 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_V  0x1
1265 #define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_S  24
1266 /* EXTMEM_DC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
1267 /*description: The bit is used to indicate interrupt by manual sync configurations fault.*/
1268 #define EXTMEM_DC_SYNC_SIZE_FAULT_ST  (BIT(23))
1269 #define EXTMEM_DC_SYNC_SIZE_FAULT_ST_M  (BIT(23))
1270 #define EXTMEM_DC_SYNC_SIZE_FAULT_ST_V  0x1
1271 #define EXTMEM_DC_SYNC_SIZE_FAULT_ST_S  23
1272 /* EXTMEM_DC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
1273 /*description: The bit is used to indicate interrupt by pre-load counter overflow.*/
1274 #define EXTMEM_DC_PRELOAD_CNT_OVF_ST  (BIT(22))
1275 #define EXTMEM_DC_PRELOAD_CNT_OVF_ST_M  (BIT(22))
1276 #define EXTMEM_DC_PRELOAD_CNT_OVF_ST_V  0x1
1277 #define EXTMEM_DC_PRELOAD_CNT_OVF_ST_S  22
1278 /* EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
1279 /*description: The bit is used to indicate interrupt by pre-load eviction counter overflow.*/
1280 #define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST  (BIT(21))
1281 #define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_M  (BIT(21))
1282 #define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_V  0x1
1283 #define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_S  21
1284 /* EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
1285 /*description: The bit is used to indicate interrupt by pre-load miss counter overflow.*/
1286 #define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST  (BIT(20))
1287 #define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_M  (BIT(20))
1288 #define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_V  0x1
1289 #define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_S  20
1290 /* EXTMEM_DBUS2_ABANDON_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
1291 /*description: The bit is used to indicate interrupt by dbus2 abandon counter overflow.*/
1292 #define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST  (BIT(18))
1293 #define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_M  (BIT(18))
1294 #define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_V  0x1
1295 #define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_S  18
1296 /* EXTMEM_DBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
1297 /*description: The bit is used to indicate interrupt by dbus1 abandon counter overflow.*/
1298 #define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST  (BIT(17))
1299 #define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_M  (BIT(17))
1300 #define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_V  0x1
1301 #define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_S  17
1302 /* EXTMEM_DBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
1303 /*description: The bit is used to indicate interrupt by dbus0 abandon counter overflow.*/
1304 #define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST  (BIT(16))
1305 #define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_M  (BIT(16))
1306 #define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_V  0x1
1307 #define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_S  16
1308 /* EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
1309 /*description: The bit is used to indicate interrupt by dbus2 eviction counter overflow.*/
1310 #define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST  (BIT(14))
1311 #define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_M  (BIT(14))
1312 #define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_V  0x1
1313 #define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_S  14
1314 /* EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
1315 /*description: The bit is used to indicate interrupt by dbus1 eviction counter overflow.*/
1316 #define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST  (BIT(13))
1317 #define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_M  (BIT(13))
1318 #define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_V  0x1
1319 #define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_S  13
1320 /* EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
1321 /*description: The bit is used to indicate interrupt by dbus0 eviction counter overflow.*/
1322 #define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST  (BIT(12))
1323 #define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_M  (BIT(12))
1324 #define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_V  0x1
1325 #define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_S  12
1326 /* EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
1327 /*description: The bit is used to indicate interrupt by dbus2 miss counter overflow.*/
1328 #define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST  (BIT(10))
1329 #define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_M  (BIT(10))
1330 #define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_V  0x1
1331 #define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_S  10
1332 /* EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
1333 /*description: The bit is used to indicate interrupt by dbus1 miss counter overflow.*/
1334 #define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST  (BIT(9))
1335 #define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_M  (BIT(9))
1336 #define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_V  0x1
1337 #define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_S  9
1338 /* EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
1339 /*description: The bit is used to indicate interrupt by dbus0 miss counter overflow.*/
1340 #define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST  (BIT(8))
1341 #define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
1342 #define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_V  0x1
1343 #define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_S  8
1344 /* EXTMEM_DBUS2_ACS_CNT_OVF_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
1345 /*description: The bit is used to indicate interrupt by dbus2 counter overflow.*/
1346 #define EXTMEM_DBUS2_ACS_CNT_OVF_ST  (BIT(6))
1347 #define EXTMEM_DBUS2_ACS_CNT_OVF_ST_M  (BIT(6))
1348 #define EXTMEM_DBUS2_ACS_CNT_OVF_ST_V  0x1
1349 #define EXTMEM_DBUS2_ACS_CNT_OVF_ST_S  6
1350 /* EXTMEM_DBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
1351 /*description: The bit is used to indicate interrupt by dbus1 counter overflow.*/
1352 #define EXTMEM_DBUS1_ACS_CNT_OVF_ST  (BIT(5))
1353 #define EXTMEM_DBUS1_ACS_CNT_OVF_ST_M  (BIT(5))
1354 #define EXTMEM_DBUS1_ACS_CNT_OVF_ST_V  0x1
1355 #define EXTMEM_DBUS1_ACS_CNT_OVF_ST_S  5
1356 /* EXTMEM_DBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
1357 /*description: The bit is used to indicate interrupt by dbus0 counter overflow.*/
1358 #define EXTMEM_DBUS0_ACS_CNT_OVF_ST  (BIT(4))
1359 #define EXTMEM_DBUS0_ACS_CNT_OVF_ST_M  (BIT(4))
1360 #define EXTMEM_DBUS0_ACS_CNT_OVF_ST_V  0x1
1361 #define EXTMEM_DBUS0_ACS_CNT_OVF_ST_S  4
1362 /* EXTMEM_DBUS2_ACS_MSK_DCACHE_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
1363 /*description: The bit is used to indicate interrupt by cpu access dcache while
1364  the dbus2 is disabled or dcache is disabled which include speculative access.*/
1365 #define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST  (BIT(2))
1366 #define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_M  (BIT(2))
1367 #define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_V  0x1
1368 #define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_S  2
1369 /* EXTMEM_DBUS1_ACS_MSK_DCACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
1370 /*description: The bit is used to indicate interrupt by cpu access dcache while
1371  the dbus1 is disabled or dcache is disabled which include speculative access.*/
1372 #define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST  (BIT(1))
1373 #define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_M  (BIT(1))
1374 #define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_V  0x1
1375 #define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_S  1
1376 /* EXTMEM_DBUS0_ACS_MSK_DCACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
1377 /*description: The bit is used to indicate interrupt by cpu access dcache while
1378  the dbus0 is disabled or dcache is disabled which include speculative access.*/
1379 #define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST  (BIT(0))
1380 #define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_M  (BIT(0))
1381 #define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_V  0x1
1382 #define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_S  0
1383 
1384 #define EXTMEM_PRO_CACHE_ACS_CNT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x0F8)
1385 /* EXTMEM_PRO_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
1386 /*description: The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG
1387   IC_PRELOAD_MISS_CNT_REG  IBUS0-2_ABANDON_CNT_REG  IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG.*/
1388 #define EXTMEM_PRO_ICACHE_ACS_CNT_CLR  (BIT(1))
1389 #define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_M  (BIT(1))
1390 #define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_V  0x1
1391 #define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_S  1
1392 /* EXTMEM_PRO_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
1393 /*description: The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG
1394   DC_PRELOAD_EVICT_CNT_REG  DC_PRELOAD_MISS_CNT_REG  DBUS0-2_ABANDON_CNT_REG  DBUS0-2_ACS_WB_CNT_REG  DBUS0-2_ACS_MISS_CNT_REG and DBUS0-2_ACS_CNT_REG.*/
1395 #define EXTMEM_PRO_DCACHE_ACS_CNT_CLR  (BIT(0))
1396 #define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_M  (BIT(0))
1397 #define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_V  0x1
1398 #define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_S  0
1399 
1400 #define EXTMEM_PRO_DCACHE_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x0FC)
1401 /* EXTMEM_PRO_DCACHE_CPU_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
1402 /*description: The bits are used to indicate the attribute of CPU access dcache
1403  when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
1404 #define EXTMEM_PRO_DCACHE_CPU_ATTR  0x00000007
1405 #define EXTMEM_PRO_DCACHE_CPU_ATTR_M  ((EXTMEM_PRO_DCACHE_CPU_ATTR_V)<<(EXTMEM_PRO_DCACHE_CPU_ATTR_S))
1406 #define EXTMEM_PRO_DCACHE_CPU_ATTR_V  0x7
1407 #define EXTMEM_PRO_DCACHE_CPU_ATTR_S  3
1408 /* EXTMEM_PRO_DCACHE_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
1409 /*description: The bits are used to indicate the attribute of data from external
1410  memory when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
1411 #define EXTMEM_PRO_DCACHE_TAG_ATTR  0x00000007
1412 #define EXTMEM_PRO_DCACHE_TAG_ATTR_M  ((EXTMEM_PRO_DCACHE_TAG_ATTR_V)<<(EXTMEM_PRO_DCACHE_TAG_ATTR_S))
1413 #define EXTMEM_PRO_DCACHE_TAG_ATTR_V  0x7
1414 #define EXTMEM_PRO_DCACHE_TAG_ATTR_S  0
1415 
1416 #define EXTMEM_PRO_DCACHE_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x100)
1417 /* EXTMEM_PRO_DCACHE_CPU_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1418 /*description: The bits are used to indicate the virtual address of CPU access
1419  dcache when authentication fail.*/
1420 #define EXTMEM_PRO_DCACHE_CPU_VADDR  0xFFFFFFFF
1421 #define EXTMEM_PRO_DCACHE_CPU_VADDR_M  ((EXTMEM_PRO_DCACHE_CPU_VADDR_V)<<(EXTMEM_PRO_DCACHE_CPU_VADDR_S))
1422 #define EXTMEM_PRO_DCACHE_CPU_VADDR_V  0xFFFFFFFF
1423 #define EXTMEM_PRO_DCACHE_CPU_VADDR_S  0
1424 
1425 #define EXTMEM_PRO_ICACHE_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x104)
1426 /* EXTMEM_PRO_ICACHE_CPU_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
1427 /*description: The bits are used to indicate the attribute of CPU access icache
1428  when authentication fail. 0: invalidate  1: execute-able  2: read-able*/
1429 #define EXTMEM_PRO_ICACHE_CPU_ATTR  0x00000007
1430 #define EXTMEM_PRO_ICACHE_CPU_ATTR_M  ((EXTMEM_PRO_ICACHE_CPU_ATTR_V)<<(EXTMEM_PRO_ICACHE_CPU_ATTR_S))
1431 #define EXTMEM_PRO_ICACHE_CPU_ATTR_V  0x7
1432 #define EXTMEM_PRO_ICACHE_CPU_ATTR_S  3
1433 /* EXTMEM_PRO_ICACHE_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
1434 /*description: The bits are used to indicate the attribute of data from external
1435  memory when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
1436 #define EXTMEM_PRO_ICACHE_TAG_ATTR  0x00000007
1437 #define EXTMEM_PRO_ICACHE_TAG_ATTR_M  ((EXTMEM_PRO_ICACHE_TAG_ATTR_V)<<(EXTMEM_PRO_ICACHE_TAG_ATTR_S))
1438 #define EXTMEM_PRO_ICACHE_TAG_ATTR_V  0x7
1439 #define EXTMEM_PRO_ICACHE_TAG_ATTR_S  0
1440 
1441 #define EXTMEM_PRO_ICACHE_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x108)
1442 /* EXTMEM_PRO_ICACHE_CPU_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1443 /*description: The bits are used to indicate the virtual address of CPU access
1444  icache when authentication fail.*/
1445 #define EXTMEM_PRO_ICACHE_CPU_VADDR  0xFFFFFFFF
1446 #define EXTMEM_PRO_ICACHE_CPU_VADDR_M  ((EXTMEM_PRO_ICACHE_CPU_VADDR_V)<<(EXTMEM_PRO_ICACHE_CPU_VADDR_S))
1447 #define EXTMEM_PRO_ICACHE_CPU_VADDR_V  0xFFFFFFFF
1448 #define EXTMEM_PRO_ICACHE_CPU_VADDR_S  0
1449 
1450 #define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0x10C)
1451 /* EXTMEM_PRO_CACHE_MMU_FAULT_CODE : RO ;bitpos:[19:17] ;default: 3'h0 ; */
1452 /*description: The bits are used to indicate the operations which cause mmu
1453  fault occurrence. 0: default  1: cpu miss  2: preload miss  3: flush  4: cpu miss evict recovery address  5: load miss evict recovery address  6: external dma tx  7: external dma rx*/
1454 #define EXTMEM_PRO_CACHE_MMU_FAULT_CODE  0x00000007
1455 #define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_M  ((EXTMEM_PRO_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_PRO_CACHE_MMU_FAULT_CODE_S))
1456 #define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_V  0x7
1457 #define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_S  17
1458 /* EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[16:0] ;default: 17'h0 ; */
1459 /*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/
1460 #define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT  0x0001FFFF
1461 #define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_M  ((EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_S))
1462 #define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_V  0x1FFFF
1463 #define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_S  0
1464 
1465 #define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x110)
1466 /* EXTMEM_PRO_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1467 /*description: The bits are used to indicate the virtual address which cause mmu fault..*/
1468 #define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR  0xFFFFFFFF
1469 #define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_M  ((EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_S))
1470 #define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_V  0xFFFFFFFF
1471 #define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_S  0
1472 
1473 #define EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x114)
1474 /* EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */
1475 /*description: The bit is used to enable wrap around mode when read data from spiram.*/
1476 #define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND  (BIT(1))
1477 #define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_M  (BIT(1))
1478 #define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_V  0x1
1479 #define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_S  1
1480 /* EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
1481 /*description: The bit is used to enable wrap around mode when read data from flash.*/
1482 #define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND  (BIT(0))
1483 #define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_M  (BIT(0))
1484 #define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_V  0x1
1485 #define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_S  0
1486 
1487 #define EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x118)
1488 /* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
1489 /*description: The bit is used to power mmu memory down  0: follow_rtc_lslp_pd  1: power up*/
1490 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU  (BIT(2))
1491 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_M  (BIT(2))
1492 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_V  0x1
1493 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_S  2
1494 /* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
1495 /*description: The bit is used to power mmu memory down  0: follow_rtc_lslp_pd  1: power down*/
1496 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD  (BIT(1))
1497 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_M  (BIT(1))
1498 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_V  0x1
1499 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_S  1
1500 /* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
1501 /*description: The bit is used to enable clock gating to save power when access
1502  mmu memory  0: enable  1: disable*/
1503 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON  (BIT(0))
1504 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_M  (BIT(0))
1505 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_V  0x1
1506 #define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_S  0
1507 
1508 #define EXTMEM_PRO_CACHE_STATE_REG          (DR_REG_EXTMEM_BASE + 0x11C)
1509 /* EXTMEM_PRO_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h0 ; */
1510 /*description: The bit is used to indicate dcache main fsm is in idle state
1511  or not. 1: in idle state   0: not in idle state*/
1512 #define EXTMEM_PRO_DCACHE_STATE  0x00000FFF
1513 #define EXTMEM_PRO_DCACHE_STATE_M  ((EXTMEM_PRO_DCACHE_STATE_V)<<(EXTMEM_PRO_DCACHE_STATE_S))
1514 #define EXTMEM_PRO_DCACHE_STATE_V  0xFFF
1515 #define EXTMEM_PRO_DCACHE_STATE_S  12
1516 /* EXTMEM_PRO_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h0 ; */
1517 /*description: The bit is used to indicate icache main fsm is in idle state
1518  or not. 1: in idle state   0: not in idle state*/
1519 #define EXTMEM_PRO_ICACHE_STATE  0x00000FFF
1520 #define EXTMEM_PRO_ICACHE_STATE_M  ((EXTMEM_PRO_ICACHE_STATE_V)<<(EXTMEM_PRO_ICACHE_STATE_S))
1521 #define EXTMEM_PRO_ICACHE_STATE_V  0xFFF
1522 #define EXTMEM_PRO_ICACHE_STATE_S  0
1523 
1524 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG          (DR_REG_EXTMEM_BASE + 0x120)
1525 /* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
1526 /*description: Reserved.*/
1527 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT  (BIT(1))
1528 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M  (BIT(1))
1529 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V  0x1
1530 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S  1
1531 /* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
1532 /*description: Reserved.*/
1533 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT  (BIT(0))
1534 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M  (BIT(0))
1535 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V  0x1
1536 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S  0
1537 
1538 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG          (DR_REG_EXTMEM_BASE + 0x124)
1539 /* EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
1540 /*description: The bit is used to close clock gating of encrypt and decrypt
1541  clock. 1: close gating  0: open clock gating.*/
1542 #define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT  (BIT(2))
1543 #define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_M  (BIT(2))
1544 #define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_V  0x1
1545 #define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_S  2
1546 /* EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
1547 /*description: The bit is used to close clock gating of decrypt clock. 1: close
1548  gating  0: open clock gating.*/
1549 #define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT  (BIT(1))
1550 #define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_M  (BIT(1))
1551 #define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_V  0x1
1552 #define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_S  1
1553 /* EXTMEM_CLK_FORCE_ON_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
1554 /*description: The bit is used to close clock gating of encrypt clock. 1: close
1555  gating  0: open clock gating.*/
1556 #define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT  (BIT(0))
1557 #define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_M  (BIT(0))
1558 #define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_V  0x1
1559 #define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_S  0
1560 
1561 #define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x128)
1562 /* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */
1563 /*description: Reserved.*/
1564 #define EXTMEM_ALLOC_WB_HOLD_ARBITER  (BIT(0))
1565 #define EXTMEM_ALLOC_WB_HOLD_ARBITER_M  (BIT(0))
1566 #define EXTMEM_ALLOC_WB_HOLD_ARBITER_V  0x1
1567 #define EXTMEM_ALLOC_WB_HOLD_ARBITER_S  0
1568 
1569 #define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x12C)
1570 /* EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
1571 /*description: The bit is used to clear the interrupt by dcache pre-load done.*/
1572 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR  (BIT(5))
1573 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_M  (BIT(5))
1574 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_V  0x1
1575 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_S  5
1576 /* EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
1577 /*description: The bit is used to enable the interrupt by dcache pre-load done.*/
1578 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA  (BIT(4))
1579 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_M  (BIT(4))
1580 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_V  0x1
1581 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_S  4
1582 /* EXTMEM_PRO_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
1583 /*description: The bit is used to indicate the interrupt by dcache pre-load done.*/
1584 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST  (BIT(3))
1585 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_M  (BIT(3))
1586 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_V  0x1
1587 #define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_S  3
1588 /* EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
1589 /*description: The bit is used to clear the interrupt by icache pre-load done.*/
1590 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR  (BIT(2))
1591 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_M  (BIT(2))
1592 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_V  0x1
1593 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_S  2
1594 /* EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
1595 /*description: The bit is used to enable the interrupt by icache pre-load done.*/
1596 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA  (BIT(1))
1597 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_M  (BIT(1))
1598 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_V  0x1
1599 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_S  1
1600 /* EXTMEM_PRO_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
1601 /*description: The bit is used to indicate the interrupt by icache pre-load done.*/
1602 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST  (BIT(0))
1603 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_M  (BIT(0))
1604 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_V  0x1
1605 #define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_S  0
1606 
1607 #define EXTMEM_CACHE_SYNC_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x130)
1608 /* EXTMEM_PRO_DCACHE_SYNC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
1609 /*description: The bit is used to clear the interrupt by dcache sync done.*/
1610 #define EXTMEM_PRO_DCACHE_SYNC_INT_CLR  (BIT(5))
1611 #define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_M  (BIT(5))
1612 #define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_V  0x1
1613 #define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_S  5
1614 /* EXTMEM_PRO_DCACHE_SYNC_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
1615 /*description: The bit is used to enable the interrupt by dcache sync done.*/
1616 #define EXTMEM_PRO_DCACHE_SYNC_INT_ENA  (BIT(4))
1617 #define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_M  (BIT(4))
1618 #define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_V  0x1
1619 #define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_S  4
1620 /* EXTMEM_PRO_DCACHE_SYNC_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
1621 /*description: The bit is used to indicate the interrupt by dcache sync done.*/
1622 #define EXTMEM_PRO_DCACHE_SYNC_INT_ST  (BIT(3))
1623 #define EXTMEM_PRO_DCACHE_SYNC_INT_ST_M  (BIT(3))
1624 #define EXTMEM_PRO_DCACHE_SYNC_INT_ST_V  0x1
1625 #define EXTMEM_PRO_DCACHE_SYNC_INT_ST_S  3
1626 /* EXTMEM_PRO_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
1627 /*description: The bit is used to clear the interrupt by icache sync done.*/
1628 #define EXTMEM_PRO_ICACHE_SYNC_INT_CLR  (BIT(2))
1629 #define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_M  (BIT(2))
1630 #define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_V  0x1
1631 #define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_S  2
1632 /* EXTMEM_PRO_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
1633 /*description: The bit is used to enable the interrupt by icache sync done.*/
1634 #define EXTMEM_PRO_ICACHE_SYNC_INT_ENA  (BIT(1))
1635 #define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_M  (BIT(1))
1636 #define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_V  0x1
1637 #define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_S  1
1638 /* EXTMEM_PRO_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
1639 /*description: The bit is used to indicate the interrupt by icache sync done.*/
1640 #define EXTMEM_PRO_ICACHE_SYNC_INT_ST  (BIT(0))
1641 #define EXTMEM_PRO_ICACHE_SYNC_INT_ST_M  (BIT(0))
1642 #define EXTMEM_PRO_ICACHE_SYNC_INT_ST_V  0x1
1643 #define EXTMEM_PRO_ICACHE_SYNC_INT_ST_S  0
1644 
1645 #define EXTMEM_CACHE_CONF_MISC_REG          (DR_REG_EXTMEM_BASE + 0x134)
1646 /* EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */
1647 /*description: The bit is used to disable checking mmu entry fault by sync operation.*/
1648 #define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT  (BIT(1))
1649 #define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M  (BIT(1))
1650 #define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V  0x1
1651 #define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S  1
1652 /* EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */
1653 /*description: The bit is used to disable checking mmu entry fault by preload operation.*/
1654 #define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT  (BIT(0))
1655 #define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M  (BIT(0))
1656 #define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V  0x1
1657 #define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S  0
1658 
1659 #define EXTMEM_CLOCK_GATE_REG          (DR_REG_EXTMEM_BASE + 0x138)
1660 /* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
1661 /*description: Reserved.*/
1662 #define EXTMEM_CLK_EN  (BIT(0))
1663 #define EXTMEM_CLK_EN_M  (BIT(0))
1664 #define EXTMEM_CLK_EN_V  0x1
1665 #define EXTMEM_CLK_EN_S  0
1666 
1667 #define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
1668 /* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1904180 ; */
1669 /*description: Reserved.*/
1670 #define EXTMEM_DATE  0x0FFFFFFF
1671 #define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
1672 #define EXTMEM_DATE_V  0xFFFFFFF
1673 #define EXTMEM_DATE_S  0
1674 
1675 #ifdef __cplusplus
1676 }
1677 #endif
1678 
1679 
1680 
1681 #endif /*_SOC_EXTMEM_REG_H_ */
1682