1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 #define EXTMEM_L1_CACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4) 15 /* EXTMEM_L1_CACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'h0 ; */ 16 /*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/ 17 #define EXTMEM_L1_CACHE_SHUT_DBUS (BIT(1)) 18 #define EXTMEM_L1_CACHE_SHUT_DBUS_M (BIT(1)) 19 #define EXTMEM_L1_CACHE_SHUT_DBUS_V 0x1 20 #define EXTMEM_L1_CACHE_SHUT_DBUS_S 1 21 /* EXTMEM_L1_CACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'h0 ; */ 22 /*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/ 23 #define EXTMEM_L1_CACHE_SHUT_IBUS (BIT(0)) 24 #define EXTMEM_L1_CACHE_SHUT_IBUS_M (BIT(0)) 25 #define EXTMEM_L1_CACHE_SHUT_IBUS_V 0x1 26 #define EXTMEM_L1_CACHE_SHUT_IBUS_S 0 27 28 #define EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20) 29 /* EXTMEM_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */ 30 /*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/ 31 #define EXTMEM_L1_CACHE_WRAP (BIT(4)) 32 #define EXTMEM_L1_CACHE_WRAP_M (BIT(4)) 33 #define EXTMEM_L1_CACHE_WRAP_V 0x1 34 #define EXTMEM_L1_CACHE_WRAP_S 4 35 36 #define EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x24) 37 /* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ 38 /*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/ 39 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU (BIT(18)) 40 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_M (BIT(18)) 41 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_V 0x1 42 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_S 18 43 /* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ 44 /*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power 45 down.*/ 46 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD (BIT(17)) 47 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_M (BIT(17)) 48 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_V 0x1 49 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_S 17 50 /* EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ 51 /*description: The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 52 0: open clock gating..*/ 53 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON (BIT(16)) 54 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_M (BIT(16)) 55 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_V 0x1 56 #define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_S 16 57 58 #define EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) 59 /* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */ 60 /*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u 61 p.*/ 62 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU (BIT(18)) 63 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_M (BIT(18)) 64 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_V 0x1 65 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_S 18 66 /* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */ 67 /*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power 68 down.*/ 69 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD (BIT(17)) 70 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_M (BIT(17)) 71 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_V 0x1 72 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_S 17 73 /* EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */ 74 /*description: The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 75 0: open clock gating..*/ 76 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON (BIT(16)) 77 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_M (BIT(16)) 78 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_V 0x1 79 #define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_S 16 80 81 #define EXTMEM_L1_CACHE_FREEZE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x2C) 82 /* EXTMEM_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */ 83 /*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or 84 not. 0: not finished. 1: finished..*/ 85 #define EXTMEM_L1_CACHE_FREEZE_DONE (BIT(18)) 86 #define EXTMEM_L1_CACHE_FREEZE_DONE_M (BIT(18)) 87 #define EXTMEM_L1_CACHE_FREEZE_DONE_V 0x1 88 #define EXTMEM_L1_CACHE_FREEZE_DONE_S 18 89 /* EXTMEM_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */ 90 /*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access 91 will not stuck. 1: a miss-access will stuck..*/ 92 #define EXTMEM_L1_CACHE_FREEZE_MODE (BIT(17)) 93 #define EXTMEM_L1_CACHE_FREEZE_MODE_M (BIT(17)) 94 #define EXTMEM_L1_CACHE_FREEZE_MODE_V 0x1 95 #define EXTMEM_L1_CACHE_FREEZE_MODE_S 17 96 /* EXTMEM_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ 97 /*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof 98 tware..*/ 99 #define EXTMEM_L1_CACHE_FREEZE_EN (BIT(16)) 100 #define EXTMEM_L1_CACHE_FREEZE_EN_M (BIT(16)) 101 #define EXTMEM_L1_CACHE_FREEZE_EN_V 0x1 102 #define EXTMEM_L1_CACHE_FREEZE_EN_S 16 103 104 #define EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x30) 105 /* EXTMEM_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ 106 /*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 107 1: enable..*/ 108 #define EXTMEM_L1_CACHE_DATA_MEM_WR_EN (BIT(17)) 109 #define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_M (BIT(17)) 110 #define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_V 0x1 111 #define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_S 17 112 /* EXTMEM_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ 113 /*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1 114 : enable..*/ 115 #define EXTMEM_L1_CACHE_DATA_MEM_RD_EN (BIT(16)) 116 #define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_M (BIT(16)) 117 #define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_V 0x1 118 #define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_S 16 119 120 #define EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_EXTMEM_BASE + 0x34) 121 /* EXTMEM_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */ 122 /*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1 123 : enable..*/ 124 #define EXTMEM_L1_CACHE_TAG_MEM_WR_EN (BIT(17)) 125 #define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_M (BIT(17)) 126 #define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_V 0x1 127 #define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_S 17 128 /* EXTMEM_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */ 129 /*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: 130 enable..*/ 131 #define EXTMEM_L1_CACHE_TAG_MEM_RD_EN (BIT(16)) 132 #define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_M (BIT(16)) 133 #define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_V 0x1 134 #define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_S 16 135 136 #define EXTMEM_L1_CACHE_PRELOCK_CONF_REG (DR_REG_EXTMEM_BASE + 0x78) 137 /* EXTMEM_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ 138 /*description: The bit is used to enable the second section of prelock function on L1-Cache..*/ 139 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN (BIT(1)) 140 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_M (BIT(1)) 141 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_V 0x1 142 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_S 1 143 /* EXTMEM_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 144 /*description: The bit is used to enable the first section of prelock function on L1-Cache..*/ 145 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN (BIT(0)) 146 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_M (BIT(0)) 147 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_V 0x1 148 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_S 0 149 150 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x7C) 151 /* EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 152 /*description: Those bits are used to configure the start virtual address of the first section 153 of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0 154 _SIZE_REG.*/ 155 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF 156 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S)) 157 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF 158 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S 0 159 160 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) 161 /* EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 162 /*description: Those bits are used to configure the start virtual address of the second section 163 of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT 164 1_SIZE_REG.*/ 165 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF 166 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S)) 167 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF 168 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S 0 169 170 #define EXTMEM_L1_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) 171 /* EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */ 172 /*description: Those bits are used to configure the size of the second section of prelock on L1 173 -Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/ 174 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE 0x00003FFF 175 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S)) 176 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V 0x3FFF 177 #define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S 16 178 /* EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */ 179 /*description: Those bits are used to configure the size of the first section of prelock on L1- 180 Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/ 181 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE 0x00003FFF 182 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S)) 183 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V 0x3FFF 184 #define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S 0 185 186 #define EXTMEM_L1_CACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) 187 /* EXTMEM_L1_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */ 188 /*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0: 189 not finished. 1: finished..*/ 190 #define EXTMEM_L1_CACHE_LOCK_DONE (BIT(2)) 191 #define EXTMEM_L1_CACHE_LOCK_DONE_M (BIT(2)) 192 #define EXTMEM_L1_CACHE_LOCK_DONE_V 0x1 193 #define EXTMEM_L1_CACHE_LOCK_DONE_S 2 194 /* EXTMEM_L1_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ 195 /*description: The bit is used to enable unlock operation. It will be cleared by hardware after 196 unlock operation done.*/ 197 #define EXTMEM_L1_CACHE_UNLOCK_ENA (BIT(1)) 198 #define EXTMEM_L1_CACHE_UNLOCK_ENA_M (BIT(1)) 199 #define EXTMEM_L1_CACHE_UNLOCK_ENA_V 0x1 200 #define EXTMEM_L1_CACHE_UNLOCK_ENA_S 1 201 /* EXTMEM_L1_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ 202 /*description: The bit is used to enable lock operation. It will be cleared by hardware after l 203 ock operation done.*/ 204 #define EXTMEM_L1_CACHE_LOCK_ENA (BIT(0)) 205 #define EXTMEM_L1_CACHE_LOCK_ENA_M (BIT(0)) 206 #define EXTMEM_L1_CACHE_LOCK_ENA_V 0x1 207 #define EXTMEM_L1_CACHE_LOCK_ENA_S 0 208 209 #define EXTMEM_L1_CACHE_LOCK_MAP_REG (DR_REG_EXTMEM_BASE + 0x8C) 210 /* EXTMEM_L1_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ 211 /*description: Those bits are used to indicate which caches in the two-level cache structure wi 212 ll apply this lock/unlock operation. [4]: L1-Cache.*/ 213 #define EXTMEM_L1_CACHE_LOCK_MAP 0x0000003F 214 #define EXTMEM_L1_CACHE_LOCK_MAP_M ((EXTMEM_L1_CACHE_LOCK_MAP_V)<<(EXTMEM_L1_CACHE_LOCK_MAP_S)) 215 #define EXTMEM_L1_CACHE_LOCK_MAP_V 0x3F 216 #define EXTMEM_L1_CACHE_LOCK_MAP_S 0 217 218 #define EXTMEM_L1_CACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x90) 219 /* EXTMEM_L1_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 220 /*description: Those bits are used to configure the start virtual address of the lock/unlock op 221 eration, which should be used together with CACHE_LOCK_SIZE_REG.*/ 222 #define EXTMEM_L1_CACHE_LOCK_ADDR 0xFFFFFFFF 223 #define EXTMEM_L1_CACHE_LOCK_ADDR_M ((EXTMEM_L1_CACHE_LOCK_ADDR_V)<<(EXTMEM_L1_CACHE_LOCK_ADDR_S)) 224 #define EXTMEM_L1_CACHE_LOCK_ADDR_V 0xFFFFFFFF 225 #define EXTMEM_L1_CACHE_LOCK_ADDR_S 0 226 227 #define EXTMEM_L1_CACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x94) 228 /* EXTMEM_L1_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 229 /*description: Those bits are used to configure the size of the lock/unlock operation, which sh 230 ould be used together with CACHE_LOCK_ADDR_REG.*/ 231 #define EXTMEM_L1_CACHE_LOCK_SIZE 0x0000FFFF 232 #define EXTMEM_L1_CACHE_LOCK_SIZE_M ((EXTMEM_L1_CACHE_LOCK_SIZE_V)<<(EXTMEM_L1_CACHE_LOCK_SIZE_S)) 233 #define EXTMEM_L1_CACHE_LOCK_SIZE_V 0xFFFF 234 #define EXTMEM_L1_CACHE_LOCK_SIZE_S 0 235 236 #define EXTMEM_L1_CACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x98) 237 /* EXTMEM_L1_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */ 238 /*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback 239 , writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/ 240 #define EXTMEM_L1_CACHE_SYNC_DONE (BIT(4)) 241 #define EXTMEM_L1_CACHE_SYNC_DONE_M (BIT(4)) 242 #define EXTMEM_L1_CACHE_SYNC_DONE_V 0x1 243 #define EXTMEM_L1_CACHE_SYNC_DONE_S 4 244 /* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */ 245 /*description: The bit is used to enable writeback-invalidate operation. It will be cleared by 246 hardware after writeback-invalidate operation done. Note that this bit and the o 247 ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive 248 , that is, those bits can not be set to 1 at the same time..*/ 249 #define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA (BIT(3)) 250 #define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M (BIT(3)) 251 #define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_V 0x1 252 #define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_S 3 253 /* EXTMEM_L1_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */ 254 /*description: The bit is used to enable writeback operation. It will be cleared by hardware af 255 ter writeback operation done. Note that this bit and the other sync-bits (invali 256 date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, 257 those bits can not be set to 1 at the same time..*/ 258 #define EXTMEM_L1_CACHE_WRITEBACK_ENA (BIT(2)) 259 #define EXTMEM_L1_CACHE_WRITEBACK_ENA_M (BIT(2)) 260 #define EXTMEM_L1_CACHE_WRITEBACK_ENA_V 0x1 261 #define EXTMEM_L1_CACHE_WRITEBACK_ENA_S 2 262 /* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */ 263 /*description: The bit is used to enable clean operation. It will be cleared by hardware after 264 clean operation done. Note that this bit and the other sync-bits (invalidate_ena 265 , writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos 266 e bits can not be set to 1 at the same time..*/ 267 #define EXTMEM_L1_CACHE_CLEAN_ENA (BIT(1)) 268 #define EXTMEM_L1_CACHE_CLEAN_ENA_M (BIT(1)) 269 #define EXTMEM_L1_CACHE_CLEAN_ENA_V 0x1 270 #define EXTMEM_L1_CACHE_CLEAN_ENA_S 1 271 /* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */ 272 /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a 273 fter invalidate operation done. Note that this bit and the other sync-bits (clea 274 n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, 275 those bits can not be set to 1 at the same time..*/ 276 #define EXTMEM_L1_CACHE_INVALIDATE_ENA (BIT(0)) 277 #define EXTMEM_L1_CACHE_INVALIDATE_ENA_M (BIT(0)) 278 #define EXTMEM_L1_CACHE_INVALIDATE_ENA_V 0x1 279 #define EXTMEM_L1_CACHE_INVALIDATE_ENA_S 0 280 281 #define EXTMEM_L1_CACHE_SYNC_MAP_REG (DR_REG_EXTMEM_BASE + 0x9C) 282 /* EXTMEM_L1_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */ 283 /*description: Those bits are used to indicate which caches in the two-level cache structure wi 284 ll apply the sync operation. [4]: L1-Cache.*/ 285 #define EXTMEM_L1_CACHE_SYNC_MAP 0x0000003F 286 #define EXTMEM_L1_CACHE_SYNC_MAP_M ((EXTMEM_L1_CACHE_SYNC_MAP_V)<<(EXTMEM_L1_CACHE_SYNC_MAP_S)) 287 #define EXTMEM_L1_CACHE_SYNC_MAP_V 0x3F 288 #define EXTMEM_L1_CACHE_SYNC_MAP_S 0 289 290 #define EXTMEM_L1_CACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA0) 291 /* EXTMEM_L1_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 292 /*description: Those bits are used to configure the start virtual address of the sync operation 293 , which should be used together with CACHE_SYNC_SIZE_REG.*/ 294 #define EXTMEM_L1_CACHE_SYNC_ADDR 0xFFFFFFFF 295 #define EXTMEM_L1_CACHE_SYNC_ADDR_M ((EXTMEM_L1_CACHE_SYNC_ADDR_V)<<(EXTMEM_L1_CACHE_SYNC_ADDR_S)) 296 #define EXTMEM_L1_CACHE_SYNC_ADDR_V 0xFFFFFFFF 297 #define EXTMEM_L1_CACHE_SYNC_ADDR_S 0 298 299 #define EXTMEM_L1_CACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA4) 300 /* EXTMEM_L1_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ 301 /*description: Those bits are used to configure the size of the sync operation, which should be 302 used together with CACHE_SYNC_ADDR_REG.*/ 303 #define EXTMEM_L1_CACHE_SYNC_SIZE 0x00FFFFFF 304 #define EXTMEM_L1_CACHE_SYNC_SIZE_M ((EXTMEM_L1_CACHE_SYNC_SIZE_V)<<(EXTMEM_L1_CACHE_SYNC_SIZE_S)) 305 #define EXTMEM_L1_CACHE_SYNC_SIZE_V 0xFFFFFF 306 #define EXTMEM_L1_CACHE_SYNC_SIZE_S 0 307 308 #define EXTMEM_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xD8) 309 /* EXTMEM_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */ 310 /*description: The bit is used to set the gid of l1 cache preload..*/ 311 #define EXTMEM_L1_CACHE_PRELOAD_RGID 0x0000000F 312 #define EXTMEM_L1_CACHE_PRELOAD_RGID_M ((EXTMEM_L1_CACHE_PRELOAD_RGID_V)<<(EXTMEM_L1_CACHE_PRELOAD_RGID_S)) 313 #define EXTMEM_L1_CACHE_PRELOAD_RGID_V 0xF 314 #define EXTMEM_L1_CACHE_PRELOAD_RGID_S 3 315 /* EXTMEM_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ 316 /*description: The bit is used to configure the direction of preload operation. 0: ascending, 1 317 : descending..*/ 318 #define EXTMEM_L1_CACHE_PRELOAD_ORDER (BIT(2)) 319 #define EXTMEM_L1_CACHE_PRELOAD_ORDER_M (BIT(2)) 320 #define EXTMEM_L1_CACHE_PRELOAD_ORDER_V 0x1 321 #define EXTMEM_L1_CACHE_PRELOAD_ORDER_S 2 322 /* EXTMEM_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ 323 /*description: The bit is used to indicate whether preload operation is finished or not. 0: not 324 finished. 1: finished..*/ 325 #define EXTMEM_L1_CACHE_PRELOAD_DONE (BIT(1)) 326 #define EXTMEM_L1_CACHE_PRELOAD_DONE_M (BIT(1)) 327 #define EXTMEM_L1_CACHE_PRELOAD_DONE_V 0x1 328 #define EXTMEM_L1_CACHE_PRELOAD_DONE_S 1 329 /* EXTMEM_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */ 330 /*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h 331 ardware automatically after preload operation is done..*/ 332 #define EXTMEM_L1_CACHE_PRELOAD_ENA (BIT(0)) 333 #define EXTMEM_L1_CACHE_PRELOAD_ENA_M (BIT(0)) 334 #define EXTMEM_L1_CACHE_PRELOAD_ENA_V 0x1 335 #define EXTMEM_L1_CACHE_PRELOAD_ENA_S 0 336 337 #define EXTMEM_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0xDC) 338 /* EXTMEM_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 339 /*description: Those bits are used to configure the start virtual address of preload on L1-Cach 340 e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/ 341 #define EXTMEM_L1_CACHE_PRELOAD_ADDR 0xFFFFFFFF 342 #define EXTMEM_L1_CACHE_PRELOAD_ADDR_M ((EXTMEM_L1_CACHE_PRELOAD_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOAD_ADDR_S)) 343 #define EXTMEM_L1_CACHE_PRELOAD_ADDR_V 0xFFFFFFFF 344 #define EXTMEM_L1_CACHE_PRELOAD_ADDR_S 0 345 346 #define EXTMEM_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0xE0) 347 /* EXTMEM_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 348 /*description: Those bits are used to configure the size of the first section of prelock on L1- 349 Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/ 350 #define EXTMEM_L1_CACHE_PRELOAD_SIZE 0x00003FFF 351 #define EXTMEM_L1_CACHE_PRELOAD_SIZE_M ((EXTMEM_L1_CACHE_PRELOAD_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOAD_SIZE_S)) 352 #define EXTMEM_L1_CACHE_PRELOAD_SIZE_V 0x3FFF 353 #define EXTMEM_L1_CACHE_PRELOAD_SIZE_S 0 354 355 #define EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x134) 356 /* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */ 357 /*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/ 358 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA (BIT(9)) 359 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_M (BIT(9)) 360 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_V 0x1 361 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_S 9 362 /* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ 363 /*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/ 364 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA (BIT(8)) 365 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_M (BIT(8)) 366 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_V 0x1 367 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_S 8 368 /* EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ 369 /*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0 370 /3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/ 371 #define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE 0x00000003 372 #define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M ((EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S)) 373 #define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V 0x3 374 #define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S 3 375 /* EXTMEM_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */ 376 /*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0: 377 ascending. 1: descending..*/ 378 #define EXTMEM_L1_CACHE_AUTOLOAD_ORDER (BIT(2)) 379 #define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_M (BIT(2)) 380 #define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_V 0x1 381 #define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_S 2 382 /* EXTMEM_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */ 383 /*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o 384 r not. 0: not finished. 1: finished..*/ 385 #define EXTMEM_L1_CACHE_AUTOLOAD_DONE (BIT(1)) 386 #define EXTMEM_L1_CACHE_AUTOLOAD_DONE_M (BIT(1)) 387 #define EXTMEM_L1_CACHE_AUTOLOAD_DONE_V 0x1 388 #define EXTMEM_L1_CACHE_AUTOLOAD_DONE_S 1 389 /* EXTMEM_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ 390 /*description: The bit is used to enable and disable autoload operation on L1-Cache. 1: enable 391 , 0: disable..*/ 392 #define EXTMEM_L1_CACHE_AUTOLOAD_ENA (BIT(0)) 393 #define EXTMEM_L1_CACHE_AUTOLOAD_ENA_M (BIT(0)) 394 #define EXTMEM_L1_CACHE_AUTOLOAD_ENA_V 0x1 395 #define EXTMEM_L1_CACHE_AUTOLOAD_ENA_S 0 396 397 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x138) 398 /* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 399 /*description: Those bits are used to configure the start virtual address of the first section 400 for autoload operation on L1-Cache. Note that it should be used together with L1 401 _CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/ 402 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF 403 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S)) 404 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF 405 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S 0 406 407 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x13C) 408 /* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ 409 /*description: Those bits are used to configure the size of the first section for autoload oper 410 ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S 411 CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/ 412 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE 0x0FFFFFFF 413 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S)) 414 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V 0xFFFFFFF 415 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S 0 416 417 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x140) 418 /* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 419 /*description: Those bits are used to configure the start virtual address of the second section 420 for autoload operation on L1-Cache. Note that it should be used together with L 421 1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/ 422 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF 423 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S)) 424 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF 425 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S 0 426 427 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x144) 428 /* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */ 429 /*description: Those bits are used to configure the size of the second section for autoload ope 430 ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_ 431 SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/ 432 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE 0x0FFFFFFF 433 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S)) 434 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V 0xFFFFFFF 435 #define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S 0 436 437 #define EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) 438 /* EXTMEM_L1_DBUS_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 439 /*description: The bit is used to enable interrupt of one of counters overflow that occurs in L 440 1-DCache due to bus1 accesses L1-DCache..*/ 441 #define EXTMEM_L1_DBUS_OVF_INT_ENA (BIT(5)) 442 #define EXTMEM_L1_DBUS_OVF_INT_ENA_M (BIT(5)) 443 #define EXTMEM_L1_DBUS_OVF_INT_ENA_V 0x1 444 #define EXTMEM_L1_DBUS_OVF_INT_ENA_S 5 445 /* EXTMEM_L1_IBUS_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 446 /*description: The bit is used to enable interrupt of one of counters overflow that occurs in L 447 1-DCache due to bus0 accesses L1-DCache..*/ 448 #define EXTMEM_L1_IBUS_OVF_INT_ENA (BIT(4)) 449 #define EXTMEM_L1_IBUS_OVF_INT_ENA_M (BIT(4)) 450 #define EXTMEM_L1_IBUS_OVF_INT_ENA_V 0x1 451 #define EXTMEM_L1_IBUS_OVF_INT_ENA_S 4 452 453 #define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x15C) 454 /* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ 455 /*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d 456 ue to bus1 accesses L1-DCache..*/ 457 #define EXTMEM_L1_DBUS_OVF_INT_CLR (BIT(5)) 458 #define EXTMEM_L1_DBUS_OVF_INT_CLR_M (BIT(5)) 459 #define EXTMEM_L1_DBUS_OVF_INT_CLR_V 0x1 460 #define EXTMEM_L1_DBUS_OVF_INT_CLR_S 5 461 /* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ 462 /*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d 463 ue to bus0 accesses L1-DCache..*/ 464 #define EXTMEM_L1_IBUS_OVF_INT_CLR (BIT(4)) 465 #define EXTMEM_L1_IBUS_OVF_INT_CLR_M (BIT(4)) 466 #define EXTMEM_L1_IBUS_OVF_INT_CLR_V 0x1 467 #define EXTMEM_L1_IBUS_OVF_INT_CLR_S 4 468 469 #define EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x160) 470 /* EXTMEM_L1_DBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ 471 /*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach 472 e due to bus1 accesses L1-DCache..*/ 473 #define EXTMEM_L1_DBUS_OVF_INT_RAW (BIT(5)) 474 #define EXTMEM_L1_DBUS_OVF_INT_RAW_M (BIT(5)) 475 #define EXTMEM_L1_DBUS_OVF_INT_RAW_V 0x1 476 #define EXTMEM_L1_DBUS_OVF_INT_RAW_S 5 477 /* EXTMEM_L1_IBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ 478 /*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach 479 e due to bus0 accesses L1-DCache..*/ 480 #define EXTMEM_L1_IBUS_OVF_INT_RAW (BIT(4)) 481 #define EXTMEM_L1_IBUS_OVF_INT_RAW_M (BIT(4)) 482 #define EXTMEM_L1_IBUS_OVF_INT_RAW_V 0x1 483 #define EXTMEM_L1_IBUS_OVF_INT_RAW_S 4 484 485 #define EXTMEM_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x164) 486 /* EXTMEM_L1_DBUS_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 487 /*description: The bit indicates the interrupt status of one of counters overflow that occurs i 488 n L1-DCache due to bus1 accesses L1-DCache..*/ 489 #define EXTMEM_L1_DBUS_OVF_INT_ST (BIT(5)) 490 #define EXTMEM_L1_DBUS_OVF_INT_ST_M (BIT(5)) 491 #define EXTMEM_L1_DBUS_OVF_INT_ST_V 0x1 492 #define EXTMEM_L1_DBUS_OVF_INT_ST_S 5 493 /* EXTMEM_L1_IBUS_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 494 /*description: The bit indicates the interrupt status of one of counters overflow that occurs i 495 n L1-DCache due to bus0 accesses L1-DCache..*/ 496 #define EXTMEM_L1_IBUS_OVF_INT_ST (BIT(4)) 497 #define EXTMEM_L1_IBUS_OVF_INT_ST_M (BIT(4)) 498 #define EXTMEM_L1_IBUS_OVF_INT_ST_V 0x1 499 #define EXTMEM_L1_IBUS_OVF_INT_ST_S 4 500 501 #define EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x168) 502 /* EXTMEM_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 503 /*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due 504 to cpu accesses L1-DCache..*/ 505 #define EXTMEM_L1_CACHE_FAIL_INT_ENA (BIT(4)) 506 #define EXTMEM_L1_CACHE_FAIL_INT_ENA_M (BIT(4)) 507 #define EXTMEM_L1_CACHE_FAIL_INT_ENA_V 0x1 508 #define EXTMEM_L1_CACHE_FAIL_INT_ENA_S 4 509 510 #define EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x16C) 511 /* EXTMEM_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ 512 /*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t 513 o cpu accesses L1-DCache..*/ 514 #define EXTMEM_L1_CACHE_FAIL_INT_CLR (BIT(4)) 515 #define EXTMEM_L1_CACHE_FAIL_INT_CLR_M (BIT(4)) 516 #define EXTMEM_L1_CACHE_FAIL_INT_CLR_V 0x1 517 #define EXTMEM_L1_CACHE_FAIL_INT_CLR_S 4 518 519 #define EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x170) 520 /* EXTMEM_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ 521 /*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/ 522 #define EXTMEM_L1_CACHE_FAIL_INT_RAW (BIT(4)) 523 #define EXTMEM_L1_CACHE_FAIL_INT_RAW_M (BIT(4)) 524 #define EXTMEM_L1_CACHE_FAIL_INT_RAW_V 0x1 525 #define EXTMEM_L1_CACHE_FAIL_INT_RAW_S 4 526 527 #define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x174) 528 /* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 529 /*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d 530 ue to cpu accesses L1-DCache..*/ 531 #define EXTMEM_L1_CACHE_FAIL_INT_ST (BIT(4)) 532 #define EXTMEM_L1_CACHE_FAIL_INT_ST_M (BIT(4)) 533 #define EXTMEM_L1_CACHE_FAIL_INT_ST_V 0x1 534 #define EXTMEM_L1_CACHE_FAIL_INT_ST_S 4 535 536 #define EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x178) 537 /* EXTMEM_L1_DBUS_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */ 538 /*description: The bit is used to clear dbus1 counter in L1-DCache..*/ 539 #define EXTMEM_L1_DBUS_CNT_CLR (BIT(21)) 540 #define EXTMEM_L1_DBUS_CNT_CLR_M (BIT(21)) 541 #define EXTMEM_L1_DBUS_CNT_CLR_V 0x1 542 #define EXTMEM_L1_DBUS_CNT_CLR_S 21 543 /* EXTMEM_L1_IBUS_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ 544 /*description: The bit is used to clear dbus0 counter in L1-DCache..*/ 545 #define EXTMEM_L1_IBUS_CNT_CLR (BIT(20)) 546 #define EXTMEM_L1_IBUS_CNT_CLR_M (BIT(20)) 547 #define EXTMEM_L1_IBUS_CNT_CLR_V 0x1 548 #define EXTMEM_L1_IBUS_CNT_CLR_S 20 549 /* EXTMEM_L1_DBUS_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 550 /*description: The bit is used to enable dbus1 counter in L1-DCache..*/ 551 #define EXTMEM_L1_DBUS_CNT_ENA (BIT(5)) 552 #define EXTMEM_L1_DBUS_CNT_ENA_M (BIT(5)) 553 #define EXTMEM_L1_DBUS_CNT_ENA_V 0x1 554 #define EXTMEM_L1_DBUS_CNT_ENA_S 5 555 /* EXTMEM_L1_IBUS_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 556 /*description: The bit is used to enable dbus0 counter in L1-DCache..*/ 557 #define EXTMEM_L1_IBUS_CNT_ENA (BIT(4)) 558 #define EXTMEM_L1_IBUS_CNT_ENA_M (BIT(4)) 559 #define EXTMEM_L1_IBUS_CNT_ENA_V 0x1 560 #define EXTMEM_L1_IBUS_CNT_ENA_S 4 561 562 #define EXTMEM_L1_IBUS_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1BC) 563 /* EXTMEM_L1_IBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 564 /*description: The register records the number of hits when bus0 accesses L1-Cache..*/ 565 #define EXTMEM_L1_IBUS_HIT_CNT 0xFFFFFFFF 566 #define EXTMEM_L1_IBUS_HIT_CNT_M ((EXTMEM_L1_IBUS_HIT_CNT_V)<<(EXTMEM_L1_IBUS_HIT_CNT_S)) 567 #define EXTMEM_L1_IBUS_HIT_CNT_V 0xFFFFFFFF 568 #define EXTMEM_L1_IBUS_HIT_CNT_S 0 569 570 #define EXTMEM_L1_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C0) 571 /* EXTMEM_L1_IBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 572 /*description: The register records the number of missing when bus0 accesses L1-Cache..*/ 573 #define EXTMEM_L1_IBUS_MISS_CNT 0xFFFFFFFF 574 #define EXTMEM_L1_IBUS_MISS_CNT_M ((EXTMEM_L1_IBUS_MISS_CNT_V)<<(EXTMEM_L1_IBUS_MISS_CNT_S)) 575 #define EXTMEM_L1_IBUS_MISS_CNT_V 0xFFFFFFFF 576 #define EXTMEM_L1_IBUS_MISS_CNT_S 0 577 578 #define EXTMEM_L1_IBUS_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C4) 579 /* EXTMEM_L1_IBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 580 /*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/ 581 #define EXTMEM_L1_IBUS_CONFLICT_CNT 0xFFFFFFFF 582 #define EXTMEM_L1_IBUS_CONFLICT_CNT_M ((EXTMEM_L1_IBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_IBUS_CONFLICT_CNT_S)) 583 #define EXTMEM_L1_IBUS_CONFLICT_CNT_V 0xFFFFFFFF 584 #define EXTMEM_L1_IBUS_CONFLICT_CNT_S 0 585 586 #define EXTMEM_L1_IBUS_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1C8) 587 /* EXTMEM_L1_IBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 588 /*description: The register records the number of times that L1-Cache accesses L2-Cache due to 589 bus0 accessing L1-Cache..*/ 590 #define EXTMEM_L1_IBUS_NXTLVL_CNT 0xFFFFFFFF 591 #define EXTMEM_L1_IBUS_NXTLVL_CNT_M ((EXTMEM_L1_IBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_IBUS_NXTLVL_CNT_S)) 592 #define EXTMEM_L1_IBUS_NXTLVL_CNT_V 0xFFFFFFFF 593 #define EXTMEM_L1_IBUS_NXTLVL_CNT_S 0 594 595 #define EXTMEM_L1_DBUS_ACS_HIT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1CC) 596 /* EXTMEM_L1_DBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 597 /*description: The register records the number of hits when bus1 accesses L1-Cache..*/ 598 #define EXTMEM_L1_DBUS_HIT_CNT 0xFFFFFFFF 599 #define EXTMEM_L1_DBUS_HIT_CNT_M ((EXTMEM_L1_DBUS_HIT_CNT_V)<<(EXTMEM_L1_DBUS_HIT_CNT_S)) 600 #define EXTMEM_L1_DBUS_HIT_CNT_V 0xFFFFFFFF 601 #define EXTMEM_L1_DBUS_HIT_CNT_S 0 602 603 #define EXTMEM_L1_DBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D0) 604 /* EXTMEM_L1_DBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 605 /*description: The register records the number of missing when bus1 accesses L1-Cache..*/ 606 #define EXTMEM_L1_DBUS_MISS_CNT 0xFFFFFFFF 607 #define EXTMEM_L1_DBUS_MISS_CNT_M ((EXTMEM_L1_DBUS_MISS_CNT_V)<<(EXTMEM_L1_DBUS_MISS_CNT_S)) 608 #define EXTMEM_L1_DBUS_MISS_CNT_V 0xFFFFFFFF 609 #define EXTMEM_L1_DBUS_MISS_CNT_S 0 610 611 #define EXTMEM_L1_DBUS_ACS_CONFLICT_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D4) 612 /* EXTMEM_L1_DBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 613 /*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/ 614 #define EXTMEM_L1_DBUS_CONFLICT_CNT 0xFFFFFFFF 615 #define EXTMEM_L1_DBUS_CONFLICT_CNT_M ((EXTMEM_L1_DBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_DBUS_CONFLICT_CNT_S)) 616 #define EXTMEM_L1_DBUS_CONFLICT_CNT_V 0xFFFFFFFF 617 #define EXTMEM_L1_DBUS_CONFLICT_CNT_S 0 618 619 #define EXTMEM_L1_DBUS_ACS_NXTLVL_CNT_REG (DR_REG_EXTMEM_BASE + 0x1D8) 620 /* EXTMEM_L1_DBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 621 /*description: The register records the number of times that L1-Cache accesses L2-Cache due to 622 bus1 accessing L1-Cache..*/ 623 #define EXTMEM_L1_DBUS_NXTLVL_CNT 0xFFFFFFFF 624 #define EXTMEM_L1_DBUS_NXTLVL_CNT_M ((EXTMEM_L1_DBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_DBUS_NXTLVL_CNT_S)) 625 #define EXTMEM_L1_DBUS_NXTLVL_CNT_V 0xFFFFFFFF 626 #define EXTMEM_L1_DBUS_NXTLVL_CNT_S 0 627 628 #define EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_EXTMEM_BASE + 0x21C) 629 /* EXTMEM_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */ 630 /*description: The register records the attribution of fail-access when cache accesses L1-Cache 631 ..*/ 632 #define EXTMEM_L1_CACHE_FAIL_ATTR 0x0000FFFF 633 #define EXTMEM_L1_CACHE_FAIL_ATTR_M ((EXTMEM_L1_CACHE_FAIL_ATTR_V)<<(EXTMEM_L1_CACHE_FAIL_ATTR_S)) 634 #define EXTMEM_L1_CACHE_FAIL_ATTR_V 0xFFFF 635 #define EXTMEM_L1_CACHE_FAIL_ATTR_S 16 636 /* EXTMEM_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 637 /*description: The register records the ID of fail-access when cache accesses L1-Cache..*/ 638 #define EXTMEM_L1_CACHE_FAIL_ID 0x0000FFFF 639 #define EXTMEM_L1_CACHE_FAIL_ID_M ((EXTMEM_L1_CACHE_FAIL_ID_V)<<(EXTMEM_L1_CACHE_FAIL_ID_S)) 640 #define EXTMEM_L1_CACHE_FAIL_ID_V 0xFFFF 641 #define EXTMEM_L1_CACHE_FAIL_ID_S 0 642 643 #define EXTMEM_L1_CACHE_ACS_FAIL_ADDR_REG (DR_REG_EXTMEM_BASE + 0x220) 644 /* EXTMEM_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 645 /*description: The register records the address of fail-access when cache accesses L1-Cache..*/ 646 #define EXTMEM_L1_CACHE_FAIL_ADDR 0xFFFFFFFF 647 #define EXTMEM_L1_CACHE_FAIL_ADDR_M ((EXTMEM_L1_CACHE_FAIL_ADDR_V)<<(EXTMEM_L1_CACHE_FAIL_ADDR_S)) 648 #define EXTMEM_L1_CACHE_FAIL_ADDR_V 0xFFFFFFFF 649 #define EXTMEM_L1_CACHE_FAIL_ADDR_S 0 650 651 #define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x224) 652 /* EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ 653 /*description: The bit is used to enable interrupt of Cache sync-operation error..*/ 654 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA (BIT(13)) 655 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_M (BIT(13)) 656 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_V 0x1 657 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_S 13 658 /* EXTMEM_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 659 /*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/ 660 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA (BIT(11)) 661 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_M (BIT(11)) 662 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_V 0x1 663 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_S 11 664 /* EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 665 /*description: The bit is used to enable interrupt of Cache sync-operation done..*/ 666 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA (BIT(6)) 667 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_M (BIT(6)) 668 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_V 0x1 669 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_S 6 670 /* EXTMEM_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 671 /*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op 672 eration is done, interrupt occurs..*/ 673 #define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA (BIT(4)) 674 #define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_M (BIT(4)) 675 #define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_V 0x1 676 #define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_S 4 677 678 #define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x228) 679 /* EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ 680 /*description: The bit is used to clear interrupt of Cache sync-operation error..*/ 681 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR (BIT(13)) 682 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_M (BIT(13)) 683 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_V 0x1 684 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_S 13 685 /* EXTMEM_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ 686 /*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/ 687 #define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR (BIT(11)) 688 #define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_M (BIT(11)) 689 #define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_V 0x1 690 #define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_S 11 691 /* EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ 692 /*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is 693 done..*/ 694 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR (BIT(6)) 695 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_M (BIT(6)) 696 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_V 0x1 697 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_S 6 698 /* EXTMEM_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ 699 /*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat 700 ion is done..*/ 701 #define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR (BIT(4)) 702 #define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_M (BIT(4)) 703 #define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_V 0x1 704 #define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_S 4 705 706 #define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_EXTMEM_BASE + 0x22C) 707 /* EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ 708 /*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc 709 curs..*/ 710 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW (BIT(13)) 711 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_M (BIT(13)) 712 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_V 0x1 713 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_S 13 714 /* EXTMEM_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ 715 /*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er 716 ror occurs..*/ 717 #define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW (BIT(11)) 718 #define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_M (BIT(11)) 719 #define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_V 0x1 720 #define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_S 11 721 /* EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ 722 /*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/ 723 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW (BIT(6)) 724 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_M (BIT(6)) 725 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_V 0x1 726 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_S 6 727 /* EXTMEM_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ 728 /*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is 729 done..*/ 730 #define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW (BIT(4)) 731 #define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_M (BIT(4)) 732 #define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_V 0x1 733 #define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_S 4 734 735 #define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x230) 736 /* EXTMEM_L1_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ 737 /*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/ 738 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST (BIT(13)) 739 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_M (BIT(13)) 740 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V 0x1 741 #define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S 13 742 /* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 743 /*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro 744 r..*/ 745 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ST (BIT(11)) 746 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M (BIT(11)) 747 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_V 0x1 748 #define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_S 11 749 /* EXTMEM_L1_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 750 /*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o 751 peration is done..*/ 752 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST (BIT(6)) 753 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_M (BIT(6)) 754 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_V 0x1 755 #define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_S 6 756 /* EXTMEM_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 757 /*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre 758 load-operation is done..*/ 759 #define EXTMEM_L1_CACHE_PLD_DONE_INT_ST (BIT(4)) 760 #define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_M (BIT(4)) 761 #define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_V 0x1 762 #define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_S 4 763 764 #define EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_EXTMEM_BASE + 0x234) 765 /* EXTMEM_L1_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */ 766 /*description: The values 0-2 are available which means sync map, command conflict and size are 767 error in Cache System..*/ 768 #define EXTMEM_L1_CACHE_SYNC_ERR_CODE 0x00000003 769 #define EXTMEM_L1_CACHE_SYNC_ERR_CODE_M ((EXTMEM_L1_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_L1_CACHE_SYNC_ERR_CODE_S)) 770 #define EXTMEM_L1_CACHE_SYNC_ERR_CODE_V 0x3 771 #define EXTMEM_L1_CACHE_SYNC_ERR_CODE_S 12 772 /* EXTMEM_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */ 773 /*description: The value 2 is Only available which means preload size is error in L1-Cache..*/ 774 #define EXTMEM_L1_CACHE_PLD_ERR_CODE 0x00000003 775 #define EXTMEM_L1_CACHE_PLD_ERR_CODE_M ((EXTMEM_L1_CACHE_PLD_ERR_CODE_V)<<(EXTMEM_L1_CACHE_PLD_ERR_CODE_S)) 776 #define EXTMEM_L1_CACHE_PLD_ERR_CODE_V 0x3 777 #define EXTMEM_L1_CACHE_PLD_ERR_CODE_S 8 778 779 #define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x238) 780 /* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 781 /*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl 782 y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/ 783 #define EXTMEM_L1_CACHE_SYNC_RST (BIT(4)) 784 #define EXTMEM_L1_CACHE_SYNC_RST_M (BIT(4)) 785 #define EXTMEM_L1_CACHE_SYNC_RST_V 0x1 786 #define EXTMEM_L1_CACHE_SYNC_RST_S 4 787 788 #define EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_EXTMEM_BASE + 0x23C) 789 /* EXTMEM_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 790 /*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should 791 only be used to initialize preload-logic when some fatal error of preload-logic 792 occurs..*/ 793 #define EXTMEM_L1_CACHE_PLD_RST (BIT(4)) 794 #define EXTMEM_L1_CACHE_PLD_RST_M (BIT(4)) 795 #define EXTMEM_L1_CACHE_PLD_RST_V 0x1 796 #define EXTMEM_L1_CACHE_PLD_RST_S 4 797 798 #define EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_EXTMEM_BASE + 0x240) 799 /* EXTMEM_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ 800 /*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au 801 toload will not work in L1-Cache. This bit should not be active when autoload wo 802 rks in L1-Cache..*/ 803 #define EXTMEM_L1_CACHE_ALD_BUF_CLR (BIT(4)) 804 #define EXTMEM_L1_CACHE_ALD_BUF_CLR_M (BIT(4)) 805 #define EXTMEM_L1_CACHE_ALD_BUF_CLR_V 0x1 806 #define EXTMEM_L1_CACHE_ALD_BUF_CLR_S 4 807 808 #define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_EXTMEM_BASE + 0x244) 809 /* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ 810 /*description: The bit is used to clear the unallocate request buffer of l1 cache where the una 811 llocate request is responsed but not completed..*/ 812 #define EXTMEM_L1_CACHE_UNALLOC_CLR (BIT(4)) 813 #define EXTMEM_L1_CACHE_UNALLOC_CLR_M (BIT(4)) 814 #define EXTMEM_L1_CACHE_UNALLOC_CLR_V 0x1 815 #define EXTMEM_L1_CACHE_UNALLOC_CLR_S 4 816 817 #define EXTMEM_L1_CACHE_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x248) 818 /* EXTMEM_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */ 819 /*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi 820 th the others fields inside this register..*/ 821 #define EXTMEM_L1_CACHE_MEM_OBJECT (BIT(10)) 822 #define EXTMEM_L1_CACHE_MEM_OBJECT_M (BIT(10)) 823 #define EXTMEM_L1_CACHE_MEM_OBJECT_V 0x1 824 #define EXTMEM_L1_CACHE_MEM_OBJECT_S 10 825 /* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */ 826 /*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit 827 h the others fields inside this register..*/ 828 #define EXTMEM_L1_CACHE_TAG_OBJECT (BIT(4)) 829 #define EXTMEM_L1_CACHE_TAG_OBJECT_M (BIT(4)) 830 #define EXTMEM_L1_CACHE_TAG_OBJECT_V 0x1 831 #define EXTMEM_L1_CACHE_TAG_OBJECT_S 4 832 833 #define EXTMEM_L1_CACHE_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x24C) 834 /* EXTMEM_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ 835 /*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1 836 : way1, 2: way2, 3: way3, ?, 7: way7..*/ 837 #define EXTMEM_L1_CACHE_WAY_OBJECT 0x00000007 838 #define EXTMEM_L1_CACHE_WAY_OBJECT_M ((EXTMEM_L1_CACHE_WAY_OBJECT_V)<<(EXTMEM_L1_CACHE_WAY_OBJECT_S)) 839 #define EXTMEM_L1_CACHE_WAY_OBJECT_V 0x7 840 #define EXTMEM_L1_CACHE_WAY_OBJECT_S 0 841 842 #define EXTMEM_L1_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x250) 843 /* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */ 844 /*description: Those bits stores the virtual address which will decide where inside the specifi 845 ed tag memory object will be accessed..*/ 846 #define EXTMEM_L1_CACHE_VADDR 0xFFFFFFFF 847 #define EXTMEM_L1_CACHE_VADDR_M ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S)) 848 #define EXTMEM_L1_CACHE_VADDR_V 0xFFFFFFFF 849 #define EXTMEM_L1_CACHE_VADDR_S 0 850 851 #define EXTMEM_L1_CACHE_DEBUG_BUS_REG (DR_REG_EXTMEM_BASE + 0x254) 852 /* EXTMEM_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */ 853 /*description: This is a constant place where we can write data to or read data from the tag/da 854 ta memory on the specified cache..*/ 855 #define EXTMEM_L1_CACHE_DEBUG_BUS 0xFFFFFFFF 856 #define EXTMEM_L1_CACHE_DEBUG_BUS_M ((EXTMEM_L1_CACHE_DEBUG_BUS_V)<<(EXTMEM_L1_CACHE_DEBUG_BUS_S)) 857 #define EXTMEM_L1_CACHE_DEBUG_BUS_V 0xFFFFFFFF 858 #define EXTMEM_L1_CACHE_DEBUG_BUS_S 0 859 860 #define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) 861 /* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */ 862 /*description: version control register. Note that this default value stored is the latest date 863 when the hardware logic was updated..*/ 864 #define EXTMEM_DATE 0x0FFFFFFF 865 #define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) 866 #define EXTMEM_DATE_V 0xFFFFFFF 867 #define EXTMEM_DATE_S 0 868 869 #ifdef __cplusplus 870 } 871 #endif 872
