1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_DPORT_REG_H_ 7 #define _SOC_DPORT_REG_H_ 8 9 #include "soc.h" 10 11 #ifndef __ASSEMBLER__ 12 #include "dport_access.h" 13 #endif 14 15 /* Registers defined in this header file must be accessed using special macros, 16 * prefixed with DPORT_. See soc/dport_access.h file for details. 17 */ 18 19 #define DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000) 20 /* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ 21 /*description: */ 22 #define DPORT_PRO_BOOT_REMAP (BIT(0)) 23 #define DPORT_PRO_BOOT_REMAP_M (BIT(0)) 24 #define DPORT_PRO_BOOT_REMAP_V 0x1 25 #define DPORT_PRO_BOOT_REMAP_S 0 26 27 #define DPORT_APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004) 28 /* DPORT_APP_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ 29 /*description: */ 30 #define DPORT_APP_BOOT_REMAP (BIT(0)) 31 #define DPORT_APP_BOOT_REMAP_M (BIT(0)) 32 #define DPORT_APP_BOOT_REMAP_V 0x1 33 #define DPORT_APP_BOOT_REMAP_S 0 34 35 #define DPORT_ACCESS_CHECK_REG (DR_REG_DPORT_BASE + 0x008) 36 /* DPORT_ACCESS_CHECK_APP : RO ;bitpos:[8] ;default: 1'b0 ; */ 37 /*description: */ 38 #define DPORT_ACCESS_CHECK_APP (BIT(8)) 39 #define DPORT_ACCESS_CHECK_APP_M (BIT(8)) 40 #define DPORT_ACCESS_CHECK_APP_V 0x1 41 #define DPORT_ACCESS_CHECK_APP_S 8 42 /* DPORT_ACCESS_CHECK_PRO : RO ;bitpos:[0] ;default: 1'b0 ; */ 43 /*description: */ 44 #define DPORT_ACCESS_CHECK_PRO (BIT(0)) 45 #define DPORT_ACCESS_CHECK_PRO_M (BIT(0)) 46 #define DPORT_ACCESS_CHECK_PRO_V 0x1 47 #define DPORT_ACCESS_CHECK_PRO_S 0 48 49 #define DPORT_PRO_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x00C) 50 /* DPORT_PRODPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 51 /*description: */ 52 #define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF 53 #define DPORT_PRODPORT_APB_MASK0_M ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S)) 54 #define DPORT_PRODPORT_APB_MASK0_V 0xFFFFFFFF 55 #define DPORT_PRODPORT_APB_MASK0_S 0 56 57 #define DPORT_PRO_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x010) 58 /* DPORT_PRODPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 59 /*description: */ 60 #define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF 61 #define DPORT_PRODPORT_APB_MASK1_M ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S)) 62 #define DPORT_PRODPORT_APB_MASK1_V 0xFFFFFFFF 63 #define DPORT_PRODPORT_APB_MASK1_S 0 64 65 #define DPORT_APP_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x014) 66 /* DPORT_APPDPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 67 /*description: */ 68 #define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF 69 #define DPORT_APPDPORT_APB_MASK0_M ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S)) 70 #define DPORT_APPDPORT_APB_MASK0_V 0xFFFFFFFF 71 #define DPORT_APPDPORT_APB_MASK0_S 0 72 73 #define DPORT_APP_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x018) 74 /* DPORT_APPDPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 75 /*description: */ 76 #define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF 77 #define DPORT_APPDPORT_APB_MASK1_M ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S)) 78 #define DPORT_APPDPORT_APB_MASK1_V 0xFFFFFFFF 79 #define DPORT_APPDPORT_APB_MASK1_S 0 80 81 #define DPORT_PERI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x01C) 82 /* DPORT_PERI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 83 /*description: */ 84 #define DPORT_PERI_CLK_EN 0xFFFFFFFF 85 #define DPORT_PERI_CLK_EN_M ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S)) 86 #define DPORT_PERI_CLK_EN_V 0xFFFFFFFF 87 #define DPORT_PERI_CLK_EN_S 0 88 89 #define DPORT_PERI_RST_EN_REG (DR_REG_DPORT_BASE + 0x020) 90 /* DPORT_PERI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 91 /*description: */ 92 #define DPORT_PERI_RST_EN 0xFFFFFFFF 93 #define DPORT_PERI_RST_EN_M ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S)) 94 #define DPORT_PERI_RST_EN_V 0xFFFFFFFF 95 #define DPORT_PERI_RST_EN_S 0 96 97 /* The following bits apply to DPORT_PERI_CLK_EN_REG, DPORT_PERI_RST_EN_REG 98 */ 99 #define DPORT_PERI_EN_AES (1<<0) 100 #define DPORT_PERI_EN_SHA (1<<1) 101 #define DPORT_PERI_EN_RSA (1<<2) 102 /* NB: Secure boot reset will hold SHA & AES in reset */ 103 #define DPORT_PERI_EN_SECUREBOOT (1<<3) 104 /* NB: Digital signature reset will hold AES & RSA in reset */ 105 #define DPORT_PERI_EN_DIGITAL_SIGNATURE (1<<4) 106 107 #define DPORT_WIFI_BB_CFG_REG (DR_REG_DPORT_BASE + 0x024) 108 /* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 109 /*description: */ 110 #define DPORT_WIFI_BB_CFG 0xFFFFFFFF 111 #define DPORT_WIFI_BB_CFG_M ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S)) 112 #define DPORT_WIFI_BB_CFG_V 0xFFFFFFFF 113 #define DPORT_WIFI_BB_CFG_S 0 114 115 #define DPORT_WIFI_BB_CFG_2_REG (DR_REG_DPORT_BASE + 0x028) 116 /* DPORT_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 117 /*description: */ 118 #define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF 119 #define DPORT_WIFI_BB_CFG_2_M ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S)) 120 #define DPORT_WIFI_BB_CFG_2_V 0xFFFFFFFF 121 #define DPORT_WIFI_BB_CFG_2_S 0 122 123 #define DPORT_APPCPU_CTRL_A_REG (DR_REG_DPORT_BASE + 0x02C) 124 /* DPORT_APPCPU_RESETTING : R/W ;bitpos:[0] ;default: 1'b1 ; */ 125 /*description: */ 126 #define DPORT_APPCPU_RESETTING (BIT(0)) 127 #define DPORT_APPCPU_RESETTING_M (BIT(0)) 128 #define DPORT_APPCPU_RESETTING_V 0x1 129 #define DPORT_APPCPU_RESETTING_S 0 130 131 #define DPORT_APPCPU_CTRL_B_REG (DR_REG_DPORT_BASE + 0x030) 132 /* DPORT_APPCPU_CLKGATE_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 133 /*description: */ 134 #define DPORT_APPCPU_CLKGATE_EN (BIT(0)) 135 #define DPORT_APPCPU_CLKGATE_EN_M (BIT(0)) 136 #define DPORT_APPCPU_CLKGATE_EN_V 0x1 137 #define DPORT_APPCPU_CLKGATE_EN_S 0 138 139 #define DPORT_APPCPU_CTRL_C_REG (DR_REG_DPORT_BASE + 0x034) 140 /* DPORT_APPCPU_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ 141 /*description: */ 142 #define DPORT_APPCPU_RUNSTALL (BIT(0)) 143 #define DPORT_APPCPU_RUNSTALL_M (BIT(0)) 144 #define DPORT_APPCPU_RUNSTALL_V 0x1 145 #define DPORT_APPCPU_RUNSTALL_S 0 146 147 #define DPORT_APPCPU_CTRL_D_REG (DR_REG_DPORT_BASE + 0x038) 148 /* DPORT_APPCPU_BOOT_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 149 /*description: */ 150 #define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF 151 #define DPORT_APPCPU_BOOT_ADDR_M ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S)) 152 #define DPORT_APPCPU_BOOT_ADDR_V 0xFFFFFFFF 153 #define DPORT_APPCPU_BOOT_ADDR_S 0 154 155 #define DPORT_CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C) 156 /* DPORT_FAST_CLK_RTC_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ 157 /*description: */ 158 #define DPORT_FAST_CLK_RTC_SEL (BIT(3)) 159 #define DPORT_FAST_CLK_RTC_SEL_M (BIT(3)) 160 #define DPORT_FAST_CLK_RTC_SEL_V 0x1 161 #define DPORT_FAST_CLK_RTC_SEL_S 3 162 /* DPORT_LOWSPEED_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ 163 /*description: */ 164 #define DPORT_LOWSPEED_CLK_SEL (BIT(2)) 165 #define DPORT_LOWSPEED_CLK_SEL_M (BIT(2)) 166 #define DPORT_LOWSPEED_CLK_SEL_V 0x1 167 #define DPORT_LOWSPEED_CLK_SEL_S 2 168 /* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 169 /*description: */ 170 #define DPORT_CPUPERIOD_SEL 0x00000003 171 #define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) 172 #define DPORT_CPUPERIOD_SEL_V 0x3 173 #define DPORT_CPUPERIOD_SEL_S 0 174 175 #define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) 176 /* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */ 177 /*description: */ 178 #define DPORT_PRO_DRAM_HL (BIT(16)) 179 #define DPORT_PRO_DRAM_HL_M (BIT(16)) 180 #define DPORT_PRO_DRAM_HL_V 0x1 181 #define DPORT_PRO_DRAM_HL_S 16 182 /* DPORT_SLAVE_REQ : RO ;bitpos:[15] ;default: 1'b0 ; */ 183 /*description: */ 184 #define DPORT_SLAVE_REQ (BIT(15)) 185 #define DPORT_SLAVE_REQ_M (BIT(15)) 186 #define DPORT_SLAVE_REQ_V 0x1 187 #define DPORT_SLAVE_REQ_S 15 188 /* DPORT_AHB_SPI_REQ : RO ;bitpos:[14] ;default: 1'b0 ; */ 189 /*description: */ 190 #define DPORT_AHB_SPI_REQ (BIT(14)) 191 #define DPORT_AHB_SPI_REQ_M (BIT(14)) 192 #define DPORT_AHB_SPI_REQ_V 0x1 193 #define DPORT_AHB_SPI_REQ_S 14 194 /* DPORT_PRO_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ 195 /*description: */ 196 #define DPORT_PRO_SLAVE_REQ (BIT(13)) 197 #define DPORT_PRO_SLAVE_REQ_M (BIT(13)) 198 #define DPORT_PRO_SLAVE_REQ_V 0x1 199 #define DPORT_PRO_SLAVE_REQ_S 13 200 /* DPORT_PRO_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ 201 /*description: */ 202 #define DPORT_PRO_AHB_SPI_REQ (BIT(12)) 203 #define DPORT_PRO_AHB_SPI_REQ_M (BIT(12)) 204 #define DPORT_PRO_AHB_SPI_REQ_V 0x1 205 #define DPORT_PRO_AHB_SPI_REQ_S 12 206 /* DPORT_PRO_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ 207 /*description: */ 208 #define DPORT_PRO_DRAM_SPLIT (BIT(11)) 209 #define DPORT_PRO_DRAM_SPLIT_M (BIT(11)) 210 #define DPORT_PRO_DRAM_SPLIT_V 0x1 211 #define DPORT_PRO_DRAM_SPLIT_S 11 212 /* DPORT_PRO_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 213 /*description: */ 214 #define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10)) 215 #define DPORT_PRO_SINGLE_IRAM_ENA_M (BIT(10)) 216 #define DPORT_PRO_SINGLE_IRAM_ENA_V 0x1 217 #define DPORT_PRO_SINGLE_IRAM_ENA_S 10 218 /* DPORT_PRO_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 219 /*description: */ 220 #define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9)) 221 #define DPORT_PRO_CACHE_LOCK_3_EN_M (BIT(9)) 222 #define DPORT_PRO_CACHE_LOCK_3_EN_V 0x1 223 #define DPORT_PRO_CACHE_LOCK_3_EN_S 9 224 /* DPORT_PRO_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 225 /*description: */ 226 #define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8)) 227 #define DPORT_PRO_CACHE_LOCK_2_EN_M (BIT(8)) 228 #define DPORT_PRO_CACHE_LOCK_2_EN_V 0x1 229 #define DPORT_PRO_CACHE_LOCK_2_EN_S 8 230 /* DPORT_PRO_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 231 /*description: */ 232 #define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7)) 233 #define DPORT_PRO_CACHE_LOCK_1_EN_M (BIT(7)) 234 #define DPORT_PRO_CACHE_LOCK_1_EN_V 0x1 235 #define DPORT_PRO_CACHE_LOCK_1_EN_S 7 236 /* DPORT_PRO_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 237 /*description: */ 238 #define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6)) 239 #define DPORT_PRO_CACHE_LOCK_0_EN_M (BIT(6)) 240 #define DPORT_PRO_CACHE_LOCK_0_EN_V 0x1 241 #define DPORT_PRO_CACHE_LOCK_0_EN_S 6 242 /* DPORT_PRO_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ 243 /*description: */ 244 #define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5)) 245 #define DPORT_PRO_CACHE_FLUSH_DONE_M (BIT(5)) 246 #define DPORT_PRO_CACHE_FLUSH_DONE_V 0x1 247 #define DPORT_PRO_CACHE_FLUSH_DONE_S 5 248 /* DPORT_PRO_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ 249 /*description: */ 250 #define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4)) 251 #define DPORT_PRO_CACHE_FLUSH_ENA_M (BIT(4)) 252 #define DPORT_PRO_CACHE_FLUSH_ENA_V 0x1 253 #define DPORT_PRO_CACHE_FLUSH_ENA_S 4 254 /* DPORT_PRO_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 255 /*description: */ 256 #define DPORT_PRO_CACHE_ENABLE (BIT(3)) 257 #define DPORT_PRO_CACHE_ENABLE_M (BIT(3)) 258 #define DPORT_PRO_CACHE_ENABLE_V 0x1 259 #define DPORT_PRO_CACHE_ENABLE_S 3 260 /* DPORT_PRO_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 261 /*description: */ 262 #define DPORT_PRO_CACHE_MODE (BIT(2)) 263 #define DPORT_PRO_CACHE_MODE_M (BIT(2)) 264 #define DPORT_PRO_CACHE_MODE_V 0x1 265 #define DPORT_PRO_CACHE_MODE_S 2 266 267 #define DPORT_PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044) 268 /* DPORT_PRO_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ 269 /*description: */ 270 #define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13)) 271 #define DPORT_PRO_CACHE_MMU_IA_CLR_M (BIT(13)) 272 #define DPORT_PRO_CACHE_MMU_IA_CLR_V 0x1 273 #define DPORT_PRO_CACHE_MMU_IA_CLR_S 13 274 /* DPORT_PRO_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 275 /*description: */ 276 #define DPORT_PRO_CMMU_PD (BIT(12)) 277 #define DPORT_PRO_CMMU_PD_M (BIT(12)) 278 #define DPORT_PRO_CMMU_PD_V 0x1 279 #define DPORT_PRO_CMMU_PD_S 12 280 /* DPORT_PRO_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ 281 /*description: */ 282 #define DPORT_PRO_CMMU_FORCE_ON (BIT(11)) 283 #define DPORT_PRO_CMMU_FORCE_ON_M (BIT(11)) 284 #define DPORT_PRO_CMMU_FORCE_ON_V 0x1 285 #define DPORT_PRO_CMMU_FORCE_ON_S 11 286 /* DPORT_PRO_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ 287 /*description: */ 288 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003 289 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_M ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S)) 290 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_V 0x3 291 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9 292 /* DPORT_PRO_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ 293 /*description: */ 294 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007 295 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_M ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S)) 296 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_V 0x7 297 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6 298 /* DPORT_PRO_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ 299 /*description: */ 300 #define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5)) 301 #define DPORT_PRO_CACHE_MASK_OPSDRAM_M (BIT(5)) 302 #define DPORT_PRO_CACHE_MASK_OPSDRAM_V 0x1 303 #define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5 304 /* DPORT_PRO_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ 305 /*description: */ 306 #define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4)) 307 #define DPORT_PRO_CACHE_MASK_DROM0_M (BIT(4)) 308 #define DPORT_PRO_CACHE_MASK_DROM0_V 0x1 309 #define DPORT_PRO_CACHE_MASK_DROM0_S 4 310 /* DPORT_PRO_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ 311 /*description: */ 312 #define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3)) 313 #define DPORT_PRO_CACHE_MASK_DRAM1_M (BIT(3)) 314 #define DPORT_PRO_CACHE_MASK_DRAM1_V 0x1 315 #define DPORT_PRO_CACHE_MASK_DRAM1_S 3 316 /* DPORT_PRO_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ 317 /*description: */ 318 #define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2)) 319 #define DPORT_PRO_CACHE_MASK_IROM0_M (BIT(2)) 320 #define DPORT_PRO_CACHE_MASK_IROM0_V 0x1 321 #define DPORT_PRO_CACHE_MASK_IROM0_S 2 322 /* DPORT_PRO_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ 323 /*description: */ 324 #define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1)) 325 #define DPORT_PRO_CACHE_MASK_IRAM1_M (BIT(1)) 326 #define DPORT_PRO_CACHE_MASK_IRAM1_V 0x1 327 #define DPORT_PRO_CACHE_MASK_IRAM1_S 1 328 /* DPORT_PRO_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ 329 /*description: */ 330 #define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0)) 331 #define DPORT_PRO_CACHE_MASK_IRAM0_M (BIT(0)) 332 #define DPORT_PRO_CACHE_MASK_IRAM0_V 0x1 333 #define DPORT_PRO_CACHE_MASK_IRAM0_S 0 334 335 #define DPORT_PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048) 336 /* DPORT_PRO_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 337 /*description: */ 338 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F 339 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S)) 340 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V 0xF 341 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18 342 /* DPORT_PRO_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 343 /*description: */ 344 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F 345 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S)) 346 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V 0xF 347 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14 348 /* DPORT_PRO_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 349 /*description: */ 350 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF 351 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S)) 352 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF 353 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0 354 355 #define DPORT_PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C) 356 /* DPORT_PRO_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 357 /*description: */ 358 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F 359 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S)) 360 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V 0xF 361 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18 362 /* DPORT_PRO_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 363 /*description: */ 364 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F 365 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S)) 366 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V 0xF 367 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14 368 /* DPORT_PRO_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 369 /*description: */ 370 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF 371 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S)) 372 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF 373 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0 374 375 #define DPORT_PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050) 376 /* DPORT_PRO_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 377 /*description: */ 378 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F 379 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S)) 380 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V 0xF 381 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18 382 /* DPORT_PRO_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 383 /*description: */ 384 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F 385 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S)) 386 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V 0xF 387 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14 388 /* DPORT_PRO_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 389 /*description: */ 390 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF 391 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S)) 392 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF 393 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0 394 395 #define DPORT_PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054) 396 /* DPORT_PRO_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 397 /*description: */ 398 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F 399 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S)) 400 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V 0xF 401 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18 402 /* DPORT_PRO_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 403 /*description: */ 404 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F 405 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S)) 406 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V 0xF 407 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14 408 /* DPORT_PRO_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 409 /*description: */ 410 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF 411 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S)) 412 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF 413 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0 414 415 #define DPORT_APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058) 416 /* DPORT_APP_DRAM_HL : R/W ;bitpos:[14] ;default: 1'b0 ; */ 417 /*description: */ 418 #define DPORT_APP_DRAM_HL (BIT(14)) 419 #define DPORT_APP_DRAM_HL_M (BIT(14)) 420 #define DPORT_APP_DRAM_HL_V 0x1 421 #define DPORT_APP_DRAM_HL_S 14 422 /* DPORT_APP_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ 423 /*description: */ 424 #define DPORT_APP_SLAVE_REQ (BIT(13)) 425 #define DPORT_APP_SLAVE_REQ_M (BIT(13)) 426 #define DPORT_APP_SLAVE_REQ_V 0x1 427 #define DPORT_APP_SLAVE_REQ_S 13 428 /* DPORT_APP_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ 429 /*description: */ 430 #define DPORT_APP_AHB_SPI_REQ (BIT(12)) 431 #define DPORT_APP_AHB_SPI_REQ_M (BIT(12)) 432 #define DPORT_APP_AHB_SPI_REQ_V 0x1 433 #define DPORT_APP_AHB_SPI_REQ_S 12 434 /* DPORT_APP_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ 435 /*description: */ 436 #define DPORT_APP_DRAM_SPLIT (BIT(11)) 437 #define DPORT_APP_DRAM_SPLIT_M (BIT(11)) 438 #define DPORT_APP_DRAM_SPLIT_V 0x1 439 #define DPORT_APP_DRAM_SPLIT_S 11 440 /* DPORT_APP_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 441 /*description: */ 442 #define DPORT_APP_SINGLE_IRAM_ENA (BIT(10)) 443 #define DPORT_APP_SINGLE_IRAM_ENA_M (BIT(10)) 444 #define DPORT_APP_SINGLE_IRAM_ENA_V 0x1 445 #define DPORT_APP_SINGLE_IRAM_ENA_S 10 446 /* DPORT_APP_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 447 /*description: */ 448 #define DPORT_APP_CACHE_LOCK_3_EN (BIT(9)) 449 #define DPORT_APP_CACHE_LOCK_3_EN_M (BIT(9)) 450 #define DPORT_APP_CACHE_LOCK_3_EN_V 0x1 451 #define DPORT_APP_CACHE_LOCK_3_EN_S 9 452 /* DPORT_APP_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 453 /*description: */ 454 #define DPORT_APP_CACHE_LOCK_2_EN (BIT(8)) 455 #define DPORT_APP_CACHE_LOCK_2_EN_M (BIT(8)) 456 #define DPORT_APP_CACHE_LOCK_2_EN_V 0x1 457 #define DPORT_APP_CACHE_LOCK_2_EN_S 8 458 /* DPORT_APP_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 459 /*description: */ 460 #define DPORT_APP_CACHE_LOCK_1_EN (BIT(7)) 461 #define DPORT_APP_CACHE_LOCK_1_EN_M (BIT(7)) 462 #define DPORT_APP_CACHE_LOCK_1_EN_V 0x1 463 #define DPORT_APP_CACHE_LOCK_1_EN_S 7 464 /* DPORT_APP_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 465 /*description: */ 466 #define DPORT_APP_CACHE_LOCK_0_EN (BIT(6)) 467 #define DPORT_APP_CACHE_LOCK_0_EN_M (BIT(6)) 468 #define DPORT_APP_CACHE_LOCK_0_EN_V 0x1 469 #define DPORT_APP_CACHE_LOCK_0_EN_S 6 470 /* DPORT_APP_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ 471 /*description: */ 472 #define DPORT_APP_CACHE_FLUSH_DONE (BIT(5)) 473 #define DPORT_APP_CACHE_FLUSH_DONE_M (BIT(5)) 474 #define DPORT_APP_CACHE_FLUSH_DONE_V 0x1 475 #define DPORT_APP_CACHE_FLUSH_DONE_S 5 476 /* DPORT_APP_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ 477 /*description: */ 478 #define DPORT_APP_CACHE_FLUSH_ENA (BIT(4)) 479 #define DPORT_APP_CACHE_FLUSH_ENA_M (BIT(4)) 480 #define DPORT_APP_CACHE_FLUSH_ENA_V 0x1 481 #define DPORT_APP_CACHE_FLUSH_ENA_S 4 482 /* DPORT_APP_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 483 /*description: */ 484 #define DPORT_APP_CACHE_ENABLE (BIT(3)) 485 #define DPORT_APP_CACHE_ENABLE_M (BIT(3)) 486 #define DPORT_APP_CACHE_ENABLE_V 0x1 487 #define DPORT_APP_CACHE_ENABLE_S 3 488 /* DPORT_APP_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 489 /*description: */ 490 #define DPORT_APP_CACHE_MODE (BIT(2)) 491 #define DPORT_APP_CACHE_MODE_M (BIT(2)) 492 #define DPORT_APP_CACHE_MODE_V 0x1 493 #define DPORT_APP_CACHE_MODE_S 2 494 495 #define DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C) 496 /* DPORT_APP_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ 497 /*description: */ 498 #define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13)) 499 #define DPORT_APP_CACHE_MMU_IA_CLR_M (BIT(13)) 500 #define DPORT_APP_CACHE_MMU_IA_CLR_V 0x1 501 #define DPORT_APP_CACHE_MMU_IA_CLR_S 13 502 /* DPORT_APP_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 503 /*description: */ 504 #define DPORT_APP_CMMU_PD (BIT(12)) 505 #define DPORT_APP_CMMU_PD_M (BIT(12)) 506 #define DPORT_APP_CMMU_PD_V 0x1 507 #define DPORT_APP_CMMU_PD_S 12 508 /* DPORT_APP_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ 509 /*description: */ 510 #define DPORT_APP_CMMU_FORCE_ON (BIT(11)) 511 #define DPORT_APP_CMMU_FORCE_ON_M (BIT(11)) 512 #define DPORT_APP_CMMU_FORCE_ON_V 0x1 513 #define DPORT_APP_CMMU_FORCE_ON_S 11 514 /* DPORT_APP_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ 515 /*description: */ 516 #define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003 517 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_M ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S)) 518 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_V 0x3 519 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9 520 /* DPORT_APP_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ 521 /*description: */ 522 #define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007 523 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_M ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S)) 524 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_V 0x7 525 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6 526 /* DPORT_APP_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ 527 /*description: */ 528 #define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5)) 529 #define DPORT_APP_CACHE_MASK_OPSDRAM_M (BIT(5)) 530 #define DPORT_APP_CACHE_MASK_OPSDRAM_V 0x1 531 #define DPORT_APP_CACHE_MASK_OPSDRAM_S 5 532 /* DPORT_APP_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ 533 /*description: */ 534 #define DPORT_APP_CACHE_MASK_DROM0 (BIT(4)) 535 #define DPORT_APP_CACHE_MASK_DROM0_M (BIT(4)) 536 #define DPORT_APP_CACHE_MASK_DROM0_V 0x1 537 #define DPORT_APP_CACHE_MASK_DROM0_S 4 538 /* DPORT_APP_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ 539 /*description: */ 540 #define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3)) 541 #define DPORT_APP_CACHE_MASK_DRAM1_M (BIT(3)) 542 #define DPORT_APP_CACHE_MASK_DRAM1_V 0x1 543 #define DPORT_APP_CACHE_MASK_DRAM1_S 3 544 /* DPORT_APP_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ 545 /*description: */ 546 #define DPORT_APP_CACHE_MASK_IROM0 (BIT(2)) 547 #define DPORT_APP_CACHE_MASK_IROM0_M (BIT(2)) 548 #define DPORT_APP_CACHE_MASK_IROM0_V 0x1 549 #define DPORT_APP_CACHE_MASK_IROM0_S 2 550 /* DPORT_APP_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ 551 /*description: */ 552 #define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1)) 553 #define DPORT_APP_CACHE_MASK_IRAM1_M (BIT(1)) 554 #define DPORT_APP_CACHE_MASK_IRAM1_V 0x1 555 #define DPORT_APP_CACHE_MASK_IRAM1_S 1 556 /* DPORT_APP_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ 557 /*description: */ 558 #define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0)) 559 #define DPORT_APP_CACHE_MASK_IRAM0_M (BIT(0)) 560 #define DPORT_APP_CACHE_MASK_IRAM0_V 0x1 561 #define DPORT_APP_CACHE_MASK_IRAM0_S 0 562 563 #define DPORT_APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060) 564 /* DPORT_APP_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 565 /*description: */ 566 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F 567 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S)) 568 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V 0xF 569 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18 570 /* DPORT_APP_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 571 /*description: */ 572 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F 573 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S)) 574 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V 0xF 575 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14 576 /* DPORT_APP_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 577 /*description: */ 578 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF 579 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S)) 580 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF 581 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0 582 583 #define DPORT_APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064) 584 /* DPORT_APP_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 585 /*description: */ 586 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F 587 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S)) 588 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V 0xF 589 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18 590 /* DPORT_APP_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 591 /*description: */ 592 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F 593 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S)) 594 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V 0xF 595 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14 596 /* DPORT_APP_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 597 /*description: */ 598 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF 599 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S)) 600 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF 601 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0 602 603 #define DPORT_APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068) 604 /* DPORT_APP_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 605 /*description: */ 606 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F 607 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S)) 608 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V 0xF 609 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18 610 /* DPORT_APP_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 611 /*description: */ 612 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F 613 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S)) 614 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V 0xF 615 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14 616 /* DPORT_APP_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 617 /*description: */ 618 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF 619 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S)) 620 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF 621 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0 622 623 #define DPORT_APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C) 624 /* DPORT_APP_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ 625 /*description: */ 626 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F 627 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S)) 628 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V 0xF 629 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18 630 /* DPORT_APP_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ 631 /*description: */ 632 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F 633 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S)) 634 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V 0xF 635 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14 636 /* DPORT_APP_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ 637 /*description: */ 638 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF 639 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S)) 640 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF 641 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0 642 643 #define DPORT_TRACEMEM_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x070) 644 /* DPORT_TRACEMEM_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 645 /*description: */ 646 #define DPORT_TRACEMEM_MUX_MODE 0x00000003 647 #define DPORT_TRACEMEM_MUX_MODE_M ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S)) 648 #define DPORT_TRACEMEM_MUX_MODE_V 0x3 649 #define DPORT_TRACEMEM_MUX_MODE_S 0 650 651 #define DPORT_PRO_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x074) 652 /* DPORT_PRO_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 653 /*description: */ 654 #define DPORT_PRO_TRACEMEM_ENA (BIT(0)) 655 #define DPORT_PRO_TRACEMEM_ENA_M (BIT(0)) 656 #define DPORT_PRO_TRACEMEM_ENA_V 0x1 657 #define DPORT_PRO_TRACEMEM_ENA_S 0 658 659 #define DPORT_APP_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x078) 660 /* DPORT_APP_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 661 /*description: */ 662 #define DPORT_APP_TRACEMEM_ENA (BIT(0)) 663 #define DPORT_APP_TRACEMEM_ENA_M (BIT(0)) 664 #define DPORT_APP_TRACEMEM_ENA_V 0x1 665 #define DPORT_APP_TRACEMEM_ENA_S 0 666 667 #define DPORT_CACHE_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x07C) 668 /* DPORT_CACHE_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 669 /*description: */ 670 #define DPORT_CACHE_MUX_MODE 0x00000003 671 #define DPORT_CACHE_MUX_MODE_M ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S)) 672 #define DPORT_CACHE_MUX_MODE_V 0x3 673 #define DPORT_CACHE_MUX_MODE_S 0 674 675 #define DPORT_IMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x080) 676 /* DPORT_IMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ 677 /*description: */ 678 #define DPORT_IMMU_PAGE_MODE 0x00000003 679 #define DPORT_IMMU_PAGE_MODE_M ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S)) 680 #define DPORT_IMMU_PAGE_MODE_V 0x3 681 #define DPORT_IMMU_PAGE_MODE_S 1 682 /* DPORT_INTERNAL_SRAM_IMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 683 /*description: */ 684 #define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0)) 685 #define DPORT_INTERNAL_SRAM_IMMU_ENA_M (BIT(0)) 686 #define DPORT_INTERNAL_SRAM_IMMU_ENA_V 0x1 687 #define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0 688 689 #define DPORT_DMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x084) 690 /* DPORT_DMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ 691 /*description: */ 692 #define DPORT_DMMU_PAGE_MODE 0x00000003 693 #define DPORT_DMMU_PAGE_MODE_M ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S)) 694 #define DPORT_DMMU_PAGE_MODE_V 0x3 695 #define DPORT_DMMU_PAGE_MODE_S 1 696 /* DPORT_INTERNAL_SRAM_DMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 697 /*description: */ 698 #define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0)) 699 #define DPORT_INTERNAL_SRAM_DMMU_ENA_M (BIT(0)) 700 #define DPORT_INTERNAL_SRAM_DMMU_ENA_V 0x1 701 #define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0 702 703 #define DPORT_ROM_MPU_ENA_REG (DR_REG_DPORT_BASE + 0x088) 704 /* DPORT_APP_ROM_MPU_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 705 /*description: */ 706 #define DPORT_APP_ROM_MPU_ENA (BIT(2)) 707 #define DPORT_APP_ROM_MPU_ENA_M (BIT(2)) 708 #define DPORT_APP_ROM_MPU_ENA_V 0x1 709 #define DPORT_APP_ROM_MPU_ENA_S 2 710 /* DPORT_PRO_ROM_MPU_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 711 /*description: */ 712 #define DPORT_PRO_ROM_MPU_ENA (BIT(1)) 713 #define DPORT_PRO_ROM_MPU_ENA_M (BIT(1)) 714 #define DPORT_PRO_ROM_MPU_ENA_V 0x1 715 #define DPORT_PRO_ROM_MPU_ENA_S 1 716 /* DPORT_SHARE_ROM_MPU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 717 /*description: */ 718 #define DPORT_SHARE_ROM_MPU_ENA (BIT(0)) 719 #define DPORT_SHARE_ROM_MPU_ENA_M (BIT(0)) 720 #define DPORT_SHARE_ROM_MPU_ENA_V 0x1 721 #define DPORT_SHARE_ROM_MPU_ENA_S 0 722 723 #define DPORT_MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C) 724 /* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ 725 /*description: */ 726 #define DPORT_LSLP_MEM_PD_MASK (BIT(0)) 727 #define DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) 728 #define DPORT_LSLP_MEM_PD_MASK_V 0x1 729 #define DPORT_LSLP_MEM_PD_MASK_S 0 730 731 #define DPORT_ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090) 732 /* DPORT_SHARE_ROM_PD : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ 733 /*description: */ 734 #define DPORT_SHARE_ROM_PD 0x0000003F 735 #define DPORT_SHARE_ROM_PD_M ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S)) 736 #define DPORT_SHARE_ROM_PD_V 0x3F 737 #define DPORT_SHARE_ROM_PD_S 2 738 /* DPORT_APP_ROM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */ 739 /*description: */ 740 #define DPORT_APP_ROM_PD (BIT(1)) 741 #define DPORT_APP_ROM_PD_M (BIT(1)) 742 #define DPORT_APP_ROM_PD_V 0x1 743 #define DPORT_APP_ROM_PD_S 1 744 /* DPORT_PRO_ROM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ 745 /*description: */ 746 #define DPORT_PRO_ROM_PD (BIT(0)) 747 #define DPORT_PRO_ROM_PD_M (BIT(0)) 748 #define DPORT_PRO_ROM_PD_V 0x1 749 #define DPORT_PRO_ROM_PD_S 0 750 751 #define DPORT_ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094) 752 /* DPORT_SHARE_ROM_FO : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ 753 /*description: */ 754 #define DPORT_SHARE_ROM_FO 0x0000003F 755 #define DPORT_SHARE_ROM_FO_M ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S)) 756 #define DPORT_SHARE_ROM_FO_V 0x3F 757 #define DPORT_SHARE_ROM_FO_S 2 758 /* DPORT_APP_ROM_FO : R/W ;bitpos:[1] ;default: 1'h1 ; */ 759 /*description: */ 760 #define DPORT_APP_ROM_FO (BIT(1)) 761 #define DPORT_APP_ROM_FO_M (BIT(1)) 762 #define DPORT_APP_ROM_FO_V 0x1 763 #define DPORT_APP_ROM_FO_S 1 764 /* DPORT_PRO_ROM_FO : R/W ;bitpos:[0] ;default: 1'h1 ; */ 765 /*description: */ 766 #define DPORT_PRO_ROM_FO (BIT(0)) 767 #define DPORT_PRO_ROM_FO_M (BIT(0)) 768 #define DPORT_PRO_ROM_FO_V 0x1 769 #define DPORT_PRO_ROM_FO_S 0 770 771 #define DPORT_SRAM_PD_CTRL_0_REG (DR_REG_DPORT_BASE + 0x098) 772 /* DPORT_SRAM_PD_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 773 /*description: */ 774 #define DPORT_SRAM_PD_0 0xFFFFFFFF 775 #define DPORT_SRAM_PD_0_M ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S)) 776 #define DPORT_SRAM_PD_0_V 0xFFFFFFFF 777 #define DPORT_SRAM_PD_0_S 0 778 779 #define DPORT_SRAM_PD_CTRL_1_REG (DR_REG_DPORT_BASE + 0x09C) 780 /* DPORT_SRAM_PD_1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ 781 /*description: */ 782 #define DPORT_SRAM_PD_1 (BIT(0)) 783 #define DPORT_SRAM_PD_1_M (BIT(0)) 784 #define DPORT_SRAM_PD_1_V 0x1 785 #define DPORT_SRAM_PD_1_S 0 786 787 #define DPORT_SRAM_FO_CTRL_0_REG (DR_REG_DPORT_BASE + 0x0A0) 788 /* DPORT_SRAM_FO_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ 789 /*description: */ 790 #define DPORT_SRAM_FO_0 0xFFFFFFFF 791 #define DPORT_SRAM_FO_0_M ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S)) 792 #define DPORT_SRAM_FO_0_V 0xFFFFFFFF 793 #define DPORT_SRAM_FO_0_S 0 794 795 #define DPORT_SRAM_FO_CTRL_1_REG (DR_REG_DPORT_BASE + 0x0A4) 796 /* DPORT_SRAM_FO_1 : R/W ;bitpos:[0] ;default: 1'h1 ; */ 797 /*description: */ 798 #define DPORT_SRAM_FO_1 (BIT(0)) 799 #define DPORT_SRAM_FO_1_M (BIT(0)) 800 #define DPORT_SRAM_FO_1_V 0x1 801 #define DPORT_SRAM_FO_1_S 0 802 803 #define DPORT_IRAM_DRAM_AHB_SEL_REG (DR_REG_DPORT_BASE + 0x0A8) 804 /* DPORT_MAC_DUMP_MODE : R/W ;bitpos:[6:5] ;default: 2'h0 ; */ 805 /*description: */ 806 #define DPORT_MAC_DUMP_MODE 0x00000003 807 #define DPORT_MAC_DUMP_MODE_M ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S)) 808 #define DPORT_MAC_DUMP_MODE_V 0x3 809 #define DPORT_MAC_DUMP_MODE_S 5 810 /* DPORT_MASK_AHB : R/W ;bitpos:[4] ;default: 1'b0 ; */ 811 /*description: */ 812 #define DPORT_MASK_AHB (BIT(4)) 813 #define DPORT_MASK_AHB_M (BIT(4)) 814 #define DPORT_MASK_AHB_V 0x1 815 #define DPORT_MASK_AHB_S 4 816 /* DPORT_MASK_APP_DRAM : R/W ;bitpos:[3] ;default: 1'b0 ; */ 817 /*description: */ 818 #define DPORT_MASK_APP_DRAM (BIT(3)) 819 #define DPORT_MASK_APP_DRAM_M (BIT(3)) 820 #define DPORT_MASK_APP_DRAM_V 0x1 821 #define DPORT_MASK_APP_DRAM_S 3 822 /* DPORT_MASK_PRO_DRAM : R/W ;bitpos:[2] ;default: 1'b0 ; */ 823 /*description: */ 824 #define DPORT_MASK_PRO_DRAM (BIT(2)) 825 #define DPORT_MASK_PRO_DRAM_M (BIT(2)) 826 #define DPORT_MASK_PRO_DRAM_V 0x1 827 #define DPORT_MASK_PRO_DRAM_S 2 828 /* DPORT_MASK_APP_IRAM : R/W ;bitpos:[1] ;default: 1'b0 ; */ 829 /*description: */ 830 #define DPORT_MASK_APP_IRAM (BIT(1)) 831 #define DPORT_MASK_APP_IRAM_M (BIT(1)) 832 #define DPORT_MASK_APP_IRAM_V 0x1 833 #define DPORT_MASK_APP_IRAM_S 1 834 /* DPORT_MASK_PRO_IRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */ 835 /*description: */ 836 #define DPORT_MASK_PRO_IRAM (BIT(0)) 837 #define DPORT_MASK_PRO_IRAM_M (BIT(0)) 838 #define DPORT_MASK_PRO_IRAM_V 0x1 839 #define DPORT_MASK_PRO_IRAM_S 0 840 841 #define DPORT_TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC) 842 /* DPORT_APP_CACHE_TAG_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ 843 /*description: */ 844 #define DPORT_APP_CACHE_TAG_PD (BIT(9)) 845 #define DPORT_APP_CACHE_TAG_PD_M (BIT(9)) 846 #define DPORT_APP_CACHE_TAG_PD_V 0x1 847 #define DPORT_APP_CACHE_TAG_PD_S 9 848 /* DPORT_APP_CACHE_TAG_FORCE_ON : R/W ;bitpos:[8] ;default: 1'b1 ; */ 849 /*description: */ 850 #define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8)) 851 #define DPORT_APP_CACHE_TAG_FORCE_ON_M (BIT(8)) 852 #define DPORT_APP_CACHE_TAG_FORCE_ON_V 0x1 853 #define DPORT_APP_CACHE_TAG_FORCE_ON_S 8 854 /* DPORT_PRO_CACHE_TAG_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 855 /*description: */ 856 #define DPORT_PRO_CACHE_TAG_PD (BIT(1)) 857 #define DPORT_PRO_CACHE_TAG_PD_M (BIT(1)) 858 #define DPORT_PRO_CACHE_TAG_PD_V 0x1 859 #define DPORT_PRO_CACHE_TAG_PD_S 1 860 /* DPORT_PRO_CACHE_TAG_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 861 /*description: */ 862 #define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0)) 863 #define DPORT_PRO_CACHE_TAG_FORCE_ON_M (BIT(0)) 864 #define DPORT_PRO_CACHE_TAG_FORCE_ON_V 0x1 865 #define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0 866 867 #define DPORT_AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0) 868 /* DPORT_AHB_LITE_SDHOST_PID_REG : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ 869 /*description: */ 870 #define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007 871 #define DPORT_AHB_LITE_SDHOST_PID_REG_M ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S)) 872 #define DPORT_AHB_LITE_SDHOST_PID_REG_V 0x7 873 #define DPORT_AHB_LITE_SDHOST_PID_REG_S 11 874 /* DPORT_AHB_LITE_MASK_APPDPORT : R/W ;bitpos:[10] ;default: 1'b0 ; */ 875 /*description: */ 876 #define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10)) 877 #define DPORT_AHB_LITE_MASK_APPDPORT_M (BIT(10)) 878 #define DPORT_AHB_LITE_MASK_APPDPORT_V 0x1 879 #define DPORT_AHB_LITE_MASK_APPDPORT_S 10 880 /* DPORT_AHB_LITE_MASK_PRODPORT : R/W ;bitpos:[9] ;default: 1'b0 ; */ 881 /*description: */ 882 #define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9)) 883 #define DPORT_AHB_LITE_MASK_PRODPORT_M (BIT(9)) 884 #define DPORT_AHB_LITE_MASK_PRODPORT_V 0x1 885 #define DPORT_AHB_LITE_MASK_PRODPORT_S 9 886 /* DPORT_AHB_LITE_MASK_SDIO : R/W ;bitpos:[8] ;default: 1'b0 ; */ 887 /*description: */ 888 #define DPORT_AHB_LITE_MASK_SDIO (BIT(8)) 889 #define DPORT_AHB_LITE_MASK_SDIO_M (BIT(8)) 890 #define DPORT_AHB_LITE_MASK_SDIO_V 0x1 891 #define DPORT_AHB_LITE_MASK_SDIO_S 8 892 /* DPORT_AHB_LITE_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ 893 /*description: */ 894 #define DPORT_AHB_LITE_MASK_APP (BIT(4)) 895 #define DPORT_AHB_LITE_MASK_APP_M (BIT(4)) 896 #define DPORT_AHB_LITE_MASK_APP_V 0x1 897 #define DPORT_AHB_LITE_MASK_APP_S 4 898 /* DPORT_AHB_LITE_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ 899 /*description: */ 900 #define DPORT_AHB_LITE_MASK_PRO (BIT(0)) 901 #define DPORT_AHB_LITE_MASK_PRO_M (BIT(0)) 902 #define DPORT_AHB_LITE_MASK_PRO_V 0x1 903 #define DPORT_AHB_LITE_MASK_PRO_S 0 904 905 #define DPORT_AHB_MPU_TABLE_0_REG (DR_REG_DPORT_BASE + 0x0B4) 906 /* DPORT_AHB_ACCESS_GRANT_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ 907 /*description: */ 908 #define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF 909 #define DPORT_AHB_ACCESS_GRANT_0_M ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S)) 910 #define DPORT_AHB_ACCESS_GRANT_0_V 0xFFFFFFFF 911 #define DPORT_AHB_ACCESS_GRANT_0_S 0 912 913 #define DPORT_AHB_MPU_TABLE_1_REG (DR_REG_DPORT_BASE + 0x0B8) 914 /* DPORT_AHB_ACCESS_GRANT_1 : R/W ;bitpos:[8:0] ;default: 9'h1ff ; */ 915 /*description: */ 916 #define DPORT_AHB_ACCESS_GRANT_1 0x000001FF 917 #define DPORT_AHB_ACCESS_GRANT_1_M ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S)) 918 #define DPORT_AHB_ACCESS_GRANT_1_V 0x1FF 919 #define DPORT_AHB_ACCESS_GRANT_1_S 0 920 921 #define DPORT_HOST_INF_SEL_REG (DR_REG_DPORT_BASE + 0x0BC) 922 /* DPORT_LINK_DEVICE_SEL : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ 923 /*description: */ 924 #define DPORT_LINK_DEVICE_SEL 0x000000FF 925 #define DPORT_LINK_DEVICE_SEL_M ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S)) 926 #define DPORT_LINK_DEVICE_SEL_V 0xFF 927 #define DPORT_LINK_DEVICE_SEL_S 8 928 /* DPORT_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 929 /*description: */ 930 #define DPORT_PERI_IO_SWAP 0x000000FF 931 #define DPORT_PERI_IO_SWAP_M ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S)) 932 #define DPORT_PERI_IO_SWAP_V 0xFF 933 #define DPORT_PERI_IO_SWAP_S 0 934 935 #define DPORT_PERIP_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0C0) 936 /* DPORT_PERIP_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hf9c1e06f ; */ 937 /*description: */ 938 #define DPORT_PERIP_CLK_EN 0xFFFFFFFF 939 #define DPORT_PERIP_CLK_EN_M ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S)) 940 #define DPORT_PERIP_CLK_EN_V 0xFFFFFFFF 941 #define DPORT_PERIP_CLK_EN_S 0 942 943 #define DPORT_PWM3_CLK_EN (BIT(26)) 944 #define DPORT_PWM2_CLK_EN (BIT(25)) 945 #define DPORT_UART_MEM_CLK_EN (BIT(24)) 946 #define DPORT_UART2_CLK_EN (BIT(23)) 947 #define DPORT_SPI_DMA_CLK_EN (BIT(22)) 948 #define DPORT_I2S1_CLK_EN (BIT(21)) 949 #define DPORT_PWM1_CLK_EN (BIT(20)) 950 #define DPORT_TWAI_CLK_EN (BIT(19)) 951 #define DPORT_CAN_CLK_EN DPORT_TWAI_CLK_EN 952 #define DPORT_I2C_EXT1_CLK_EN (BIT(18)) 953 #define DPORT_PWM0_CLK_EN (BIT(17)) 954 #define DPORT_SPI3_CLK_EN (BIT(16)) 955 #define DPORT_TIMERGROUP1_CLK_EN (BIT(15)) 956 #define DPORT_EFUSE_CLK_EN (BIT(14)) 957 #define DPORT_TIMERGROUP_CLK_EN (BIT(13)) 958 #define DPORT_UHCI1_CLK_EN (BIT(12)) 959 #define DPORT_LEDC_CLK_EN (BIT(11)) 960 #define DPORT_PCNT_CLK_EN (BIT(10)) 961 #define DPORT_RMT_CLK_EN (BIT(9)) 962 #define DPORT_UHCI0_CLK_EN (BIT(8)) 963 #define DPORT_I2C_EXT0_CLK_EN (BIT(7)) 964 #define DPORT_SPI2_CLK_EN (BIT(6)) 965 #define DPORT_UART1_CLK_EN (BIT(5)) 966 #define DPORT_I2S0_CLK_EN (BIT(4)) 967 #define DPORT_WDG_CLK_EN (BIT(3)) 968 #define DPORT_UART_CLK_EN (BIT(2)) 969 #define DPORT_SPI01_CLK_EN (BIT(1)) 970 #define DPORT_TIMERS_CLK_EN (BIT(0)) 971 #define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4) 972 /* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 973 /*description: */ 974 #define DPORT_PERIP_RST 0xFFFFFFFF 975 #define DPORT_PERIP_RST_M ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S)) 976 #define DPORT_PERIP_RST_V 0xFFFFFFFF 977 #define DPORT_PERIP_RST_S 0 978 #define DPORT_PWM3_RST (BIT(26)) 979 #define DPORT_PWM2_RST (BIT(25)) 980 #define DPORT_UART_MEM_RST (BIT(24)) 981 #define DPORT_UART2_RST (BIT(23)) 982 #define DPORT_SPI_DMA_RST (BIT(22)) 983 #define DPORT_I2S1_RST (BIT(21)) 984 #define DPORT_PWM1_RST (BIT(20)) 985 #define DPORT_TWAI_RST (BIT(19)) 986 #define DPORT_CAN_RST DPORT_TWAI_RST 987 #define DPORT_I2C_EXT1_RST (BIT(18)) 988 #define DPORT_PWM0_RST (BIT(17)) 989 #define DPORT_SPI3_RST (BIT(16)) 990 #define DPORT_TIMERGROUP1_RST (BIT(15)) 991 #define DPORT_EFUSE_RST (BIT(14)) 992 #define DPORT_TIMERGROUP_RST (BIT(13)) 993 #define DPORT_UHCI1_RST (BIT(12)) 994 #define DPORT_LEDC_RST (BIT(11)) 995 #define DPORT_PCNT_RST (BIT(10)) 996 #define DPORT_RMT_RST (BIT(9)) 997 #define DPORT_UHCI0_RST (BIT(8)) 998 #define DPORT_I2C_EXT0_RST (BIT(7)) 999 #define DPORT_SPI2_RST (BIT(6)) 1000 #define DPORT_UART1_RST (BIT(5)) 1001 #define DPORT_I2S0_RST (BIT(4)) 1002 #define DPORT_WDG_RST (BIT(3)) 1003 #define DPORT_UART_RST (BIT(2)) 1004 #define DPORT_SPI01_RST (BIT(1)) 1005 #define DPORT_TIMERS_RST (BIT(0)) 1006 #define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8) 1007 /* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1008 /*description: */ 1009 #define DPORT_SPI_DECRYPT_ENABLE (BIT(12)) 1010 #define DPORT_SPI_DECRYPT_ENABLE_M (BIT(12)) 1011 #define DPORT_SPI_DECRYPT_ENABLE_V 0x1 1012 #define DPORT_SPI_DECRYPT_ENABLE_S 12 1013 /* DPORT_SPI_ENCRYPT_ENABLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1014 /*description: */ 1015 #define DPORT_SPI_ENCRYPT_ENABLE (BIT(8)) 1016 #define DPORT_SPI_ENCRYPT_ENABLE_M (BIT(8)) 1017 #define DPORT_SPI_ENCRYPT_ENABLE_V 0x1 1018 #define DPORT_SPI_ENCRYPT_ENABLE_S 8 1019 /* DPORT_SLAVE_SPI_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1020 /*description: */ 1021 #define DPORT_SLAVE_SPI_MASK_APP (BIT(4)) 1022 #define DPORT_SLAVE_SPI_MASK_APP_M (BIT(4)) 1023 #define DPORT_SLAVE_SPI_MASK_APP_V 0x1 1024 #define DPORT_SLAVE_SPI_MASK_APP_S 4 1025 /* DPORT_SLAVE_SPI_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1026 /*description: */ 1027 #define DPORT_SLAVE_SPI_MASK_PRO (BIT(0)) 1028 #define DPORT_SLAVE_SPI_MASK_PRO_M (BIT(0)) 1029 #define DPORT_SLAVE_SPI_MASK_PRO_V 0x1 1030 #define DPORT_SLAVE_SPI_MASK_PRO_S 0 1031 1032 #define DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC) 1033 /* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 1034 /*description: */ 1035 #define DPORT_WIFI_CLK_EN 0xFFFFFFFF 1036 #define DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S)) 1037 #define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF 1038 #define DPORT_WIFI_CLK_EN_S 0 1039 1040 /* Mask for all Wifi clock bits - 1, 2, 10 */ 1041 #define DPORT_WIFI_CLK_WIFI_EN 0x00000406 1042 #define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S)) 1043 #define DPORT_WIFI_CLK_WIFI_EN_V 0x406 1044 #define DPORT_WIFI_CLK_WIFI_EN_S 0 1045 /* Mask for all Bluetooth clock bits - 11, 16, 17 */ 1046 #define DPORT_WIFI_CLK_BT_EN 0x61 1047 #define DPORT_WIFI_CLK_BT_EN_M ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S)) 1048 #define DPORT_WIFI_CLK_BT_EN_V 0x61 1049 #define DPORT_WIFI_CLK_BT_EN_S 11 1050 /* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */ 1051 #define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9 1052 //bluetooth baseband bit11 1053 #define DPORT_BT_BASEBAND_EN BIT(11) 1054 //bluetooth LC bit16 and bit17 1055 #define DPORT_BT_LC_EN (BIT(16)|BIT(17)) 1056 1057 /* Remaining single bit clock masks */ 1058 #define DPORT_WIFI_CLK_SDIOSLAVE_EN BIT(4) 1059 #define DPORT_WIFI_CLK_UNUSED_BIT5 BIT(5) 1060 #define DPORT_WIFI_CLK_UNUSED_BIT12 BIT(12) 1061 #define DPORT_WIFI_CLK_SDIO_HOST_EN BIT(13) 1062 #define DPORT_WIFI_CLK_EMAC_EN BIT(14) 1063 #define DPORT_WIFI_CLK_RNG_EN BIT(15) 1064 1065 #define DPORT_CORE_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0) 1066 /* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1067 /*description: */ 1068 #define DPORT_WIFIBB_RST BIT(0) 1069 #define DPORT_FE_RST BIT(1) 1070 #define DPORT_WIFIMAC_RST BIT(2) 1071 #define DPORT_BTBB_RST BIT(3) 1072 #define DPORT_BTMAC_RST BIT(4) 1073 #define DPORT_SDIO_RST BIT(5) 1074 #define DPORT_SDIO_HOST_RST BIT(6) 1075 #define DPORT_EMAC_RST BIT(7) 1076 #define DPORT_MACPWR_RST BIT(8) 1077 #define DPORT_RW_BTMAC_RST BIT(9) 1078 #define DPORT_RW_BTLP_RST BIT(10) 1079 1080 #define MODEM_RESET_FIELD_WHEN_PU (DPORT_WIFIBB_RST | \ 1081 DPORT_FE_RST | \ 1082 DPORT_WIFIMAC_RST | \ 1083 DPORT_BTBB_RST | \ 1084 DPORT_BTMAC_RST | \ 1085 DPORT_RW_BTMAC_RST) 1086 1087 #define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4) 1088 /* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1089 /*description: */ 1090 #define DPORT_BTEXTWAKEUP_REQ (BIT(12)) 1091 #define DPORT_BTEXTWAKEUP_REQ_M (BIT(12)) 1092 #define DPORT_BTEXTWAKEUP_REQ_V 0x1 1093 #define DPORT_BTEXTWAKEUP_REQ_S 12 1094 /* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ 1095 /*description: */ 1096 #define DPORT_BT_LPCK_DIV_NUM 0x00000FFF 1097 #define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) 1098 #define DPORT_BT_LPCK_DIV_NUM_V 0xFFF 1099 #define DPORT_BT_LPCK_DIV_NUM_S 0 1100 1101 #define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_DPORT_BASE + 0x0D8) 1102 /* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ 1103 /*description: */ 1104 #define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) 1105 #define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) 1106 #define DPORT_LPCLK_SEL_XTAL32K_V 0x1 1107 #define DPORT_LPCLK_SEL_XTAL32K_S 27 1108 /* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ 1109 /*description: */ 1110 #define DPORT_LPCLK_SEL_XTAL (BIT(26)) 1111 #define DPORT_LPCLK_SEL_XTAL_M (BIT(26)) 1112 #define DPORT_LPCLK_SEL_XTAL_V 0x1 1113 #define DPORT_LPCLK_SEL_XTAL_S 26 1114 /* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ 1115 /*description: */ 1116 #define DPORT_LPCLK_SEL_8M (BIT(25)) 1117 #define DPORT_LPCLK_SEL_8M_M (BIT(25)) 1118 #define DPORT_LPCLK_SEL_8M_V 0x1 1119 #define DPORT_LPCLK_SEL_8M_S 25 1120 /* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ 1121 /*description: */ 1122 #define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) 1123 #define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) 1124 #define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 1125 #define DPORT_LPCLK_SEL_RTC_SLOW_S 24 1126 /* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ 1127 /*description: */ 1128 #define DPORT_BT_LPCK_DIV_A 0x00000FFF 1129 #define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) 1130 #define DPORT_BT_LPCK_DIV_A_V 0xFFF 1131 #define DPORT_BT_LPCK_DIV_A_S 12 1132 /* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ 1133 /*description: */ 1134 #define DPORT_BT_LPCK_DIV_B 0x00000FFF 1135 #define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) 1136 #define DPORT_BT_LPCK_DIV_B_V 0xFFF 1137 #define DPORT_BT_LPCK_DIV_B_S 0 1138 1139 #define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC) 1140 /* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1141 /*description: */ 1142 #define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) 1143 #define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) 1144 #define DPORT_CPU_INTR_FROM_CPU_0_V 0x1 1145 #define DPORT_CPU_INTR_FROM_CPU_0_S 0 1146 1147 #define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0) 1148 /* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1149 /*description: */ 1150 #define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) 1151 #define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) 1152 #define DPORT_CPU_INTR_FROM_CPU_1_V 0x1 1153 #define DPORT_CPU_INTR_FROM_CPU_1_S 0 1154 1155 #define SYSTEM_CPU_INTR_FROM_CPU_2_REG DPORT_CPU_INTR_FROM_CPU_2_REG 1156 #define SYSTEM_CPU_INTR_FROM_CPU_2 DPORT_CPU_INTR_FROM_CPU_2 1157 #define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4) 1158 /* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1159 /*description: */ 1160 #define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) 1161 #define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) 1162 #define DPORT_CPU_INTR_FROM_CPU_2_V 0x1 1163 #define DPORT_CPU_INTR_FROM_CPU_2_S 0 1164 1165 #define SYSTEM_CPU_INTR_FROM_CPU_3_REG DPORT_CPU_INTR_FROM_CPU_3_REG 1166 #define SYSTEM_CPU_INTR_FROM_CPU_3 DPORT_CPU_INTR_FROM_CPU_3 1167 #define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8) 1168 /* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1169 /*description: */ 1170 #define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) 1171 #define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) 1172 #define DPORT_CPU_INTR_FROM_CPU_3_V 0x1 1173 #define DPORT_CPU_INTR_FROM_CPU_3_S 0 1174 1175 #define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0EC) 1176 /* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1177 /*description: */ 1178 #define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF 1179 #define DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S)) 1180 #define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF 1181 #define DPORT_PRO_INTR_STATUS_0_S 0 1182 1183 #define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0F0) 1184 /* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1185 /*description: */ 1186 #define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF 1187 #define DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S)) 1188 #define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF 1189 #define DPORT_PRO_INTR_STATUS_1_S 0 1190 1191 #define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x0F4) 1192 /* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1193 /*description: */ 1194 #define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF 1195 #define DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S)) 1196 #define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF 1197 #define DPORT_PRO_INTR_STATUS_2_S 0 1198 1199 #define DPORT_APP_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0F8) 1200 /* DPORT_APP_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1201 /*description: */ 1202 #define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF 1203 #define DPORT_APP_INTR_STATUS_0_M ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S)) 1204 #define DPORT_APP_INTR_STATUS_0_V 0xFFFFFFFF 1205 #define DPORT_APP_INTR_STATUS_0_S 0 1206 1207 #define DPORT_APP_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0FC) 1208 /* DPORT_APP_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1209 /*description: */ 1210 #define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF 1211 #define DPORT_APP_INTR_STATUS_1_M ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S)) 1212 #define DPORT_APP_INTR_STATUS_1_V 0xFFFFFFFF 1213 #define DPORT_APP_INTR_STATUS_1_S 0 1214 1215 #define DPORT_APP_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x100) 1216 /* DPORT_APP_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1217 /*description: */ 1218 #define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF 1219 #define DPORT_APP_INTR_STATUS_2_M ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S)) 1220 #define DPORT_APP_INTR_STATUS_2_V 0xFFFFFFFF 1221 #define DPORT_APP_INTR_STATUS_2_S 0 1222 1223 #define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104) 1224 /* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1225 /*description: */ 1226 #define DPORT_PRO_MAC_INTR_MAP 0x0000001F 1227 #define DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S)) 1228 #define DPORT_PRO_MAC_INTR_MAP_V 0x1F 1229 #define DPORT_PRO_MAC_INTR_MAP_S 0 1230 1231 #define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108) 1232 /* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1233 /*description: */ 1234 #define DPORT_PRO_MAC_NMI_MAP 0x0000001F 1235 #define DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S)) 1236 #define DPORT_PRO_MAC_NMI_MAP_V 0x1F 1237 #define DPORT_PRO_MAC_NMI_MAP_S 0 1238 1239 #define DPORT_PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C) 1240 /* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1241 /*description: */ 1242 #define DPORT_PRO_BB_INT_MAP 0x0000001F 1243 #define DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S)) 1244 #define DPORT_PRO_BB_INT_MAP_V 0x1F 1245 #define DPORT_PRO_BB_INT_MAP_S 0 1246 1247 #define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110) 1248 /* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1249 /*description: */ 1250 #define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F 1251 #define DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S)) 1252 #define DPORT_PRO_BT_MAC_INT_MAP_V 0x1F 1253 #define DPORT_PRO_BT_MAC_INT_MAP_S 0 1254 1255 #define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114) 1256 /* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1257 /*description: */ 1258 #define DPORT_PRO_BT_BB_INT_MAP 0x0000001F 1259 #define DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S)) 1260 #define DPORT_PRO_BT_BB_INT_MAP_V 0x1F 1261 #define DPORT_PRO_BT_BB_INT_MAP_S 0 1262 1263 #define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118) 1264 /* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1265 /*description: */ 1266 #define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F 1267 #define DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S)) 1268 #define DPORT_PRO_BT_BB_NMI_MAP_V 0x1F 1269 #define DPORT_PRO_BT_BB_NMI_MAP_S 0 1270 1271 #define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C) 1272 /* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1273 /*description: */ 1274 #define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F 1275 #define DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S)) 1276 #define DPORT_PRO_RWBT_IRQ_MAP_V 0x1F 1277 #define DPORT_PRO_RWBT_IRQ_MAP_S 0 1278 1279 #define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120) 1280 /* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1281 /*description: */ 1282 #define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F 1283 #define DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S)) 1284 #define DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F 1285 #define DPORT_PRO_RWBLE_IRQ_MAP_S 0 1286 1287 #define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124) 1288 /* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1289 /*description: */ 1290 #define DPORT_PRO_RWBT_NMI_MAP 0x0000001F 1291 #define DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S)) 1292 #define DPORT_PRO_RWBT_NMI_MAP_V 0x1F 1293 #define DPORT_PRO_RWBT_NMI_MAP_S 0 1294 1295 #define DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128) 1296 /* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1297 /*description: */ 1298 #define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F 1299 #define DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S)) 1300 #define DPORT_PRO_RWBLE_NMI_MAP_V 0x1F 1301 #define DPORT_PRO_RWBLE_NMI_MAP_S 0 1302 1303 #define DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C) 1304 /* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1305 /*description: */ 1306 #define DPORT_PRO_SLC0_INTR_MAP 0x0000001F 1307 #define DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S)) 1308 #define DPORT_PRO_SLC0_INTR_MAP_V 0x1F 1309 #define DPORT_PRO_SLC0_INTR_MAP_S 0 1310 1311 #define DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130) 1312 /* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1313 /*description: */ 1314 #define DPORT_PRO_SLC1_INTR_MAP 0x0000001F 1315 #define DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S)) 1316 #define DPORT_PRO_SLC1_INTR_MAP_V 0x1F 1317 #define DPORT_PRO_SLC1_INTR_MAP_S 0 1318 1319 #define DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134) 1320 /* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1321 /*description: */ 1322 #define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F 1323 #define DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S)) 1324 #define DPORT_PRO_UHCI0_INTR_MAP_V 0x1F 1325 #define DPORT_PRO_UHCI0_INTR_MAP_S 0 1326 1327 #define DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138) 1328 /* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1329 /*description: */ 1330 #define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F 1331 #define DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S)) 1332 #define DPORT_PRO_UHCI1_INTR_MAP_V 0x1F 1333 #define DPORT_PRO_UHCI1_INTR_MAP_S 0 1334 1335 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C) 1336 /* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1337 /*description: */ 1338 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F 1339 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S)) 1340 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F 1341 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0 1342 1343 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140) 1344 /* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1345 /*description: */ 1346 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F 1347 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S)) 1348 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F 1349 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0 1350 1351 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144) 1352 /* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1353 /*description: */ 1354 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F 1355 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S)) 1356 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F 1357 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 1358 1359 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148) 1360 /* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1361 /*description: */ 1362 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F 1363 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S)) 1364 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F 1365 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 1366 1367 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C) 1368 /* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1369 /*description: */ 1370 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F 1371 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S)) 1372 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F 1373 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 1374 1375 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150) 1376 /* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1377 /*description: */ 1378 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F 1379 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S)) 1380 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F 1381 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 1382 1383 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154) 1384 /* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1385 /*description: */ 1386 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F 1387 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S)) 1388 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F 1389 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 1390 1391 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158) 1392 /* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1393 /*description: */ 1394 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F 1395 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S)) 1396 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F 1397 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 1398 1399 #define DPORT_PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C) 1400 /* DPORT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1401 /*description: */ 1402 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F 1403 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S)) 1404 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x1F 1405 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 1406 1407 #define DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160) 1408 /* DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1409 /*description: */ 1410 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F 1411 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S)) 1412 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F 1413 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 1414 1415 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164) 1416 /* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1417 /*description: */ 1418 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F 1419 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S)) 1420 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F 1421 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 1422 1423 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168) 1424 /* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1425 /*description: */ 1426 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F 1427 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S)) 1428 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F 1429 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 1430 1431 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C) 1432 /* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1433 /*description: */ 1434 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F 1435 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S)) 1436 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F 1437 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 1438 1439 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170) 1440 /* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1441 /*description: */ 1442 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F 1443 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S)) 1444 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F 1445 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 1446 1447 #define DPORT_PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174) 1448 /* DPORT_PRO_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1449 /*description: */ 1450 #define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F 1451 #define DPORT_PRO_SPI_INTR_0_MAP_M ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S)) 1452 #define DPORT_PRO_SPI_INTR_0_MAP_V 0x1F 1453 #define DPORT_PRO_SPI_INTR_0_MAP_S 0 1454 1455 #define DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178) 1456 /* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1457 /*description: */ 1458 #define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F 1459 #define DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S)) 1460 #define DPORT_PRO_SPI_INTR_1_MAP_V 0x1F 1461 #define DPORT_PRO_SPI_INTR_1_MAP_S 0 1462 1463 #define DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C) 1464 /* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1465 /*description: */ 1466 #define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F 1467 #define DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S)) 1468 #define DPORT_PRO_SPI_INTR_2_MAP_V 0x1F 1469 #define DPORT_PRO_SPI_INTR_2_MAP_S 0 1470 1471 #define DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180) 1472 /* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1473 /*description: */ 1474 #define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F 1475 #define DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S)) 1476 #define DPORT_PRO_SPI_INTR_3_MAP_V 0x1F 1477 #define DPORT_PRO_SPI_INTR_3_MAP_S 0 1478 1479 #define DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184) 1480 /* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1481 /*description: */ 1482 #define DPORT_PRO_I2S0_INT_MAP 0x0000001F 1483 #define DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S)) 1484 #define DPORT_PRO_I2S0_INT_MAP_V 0x1F 1485 #define DPORT_PRO_I2S0_INT_MAP_S 0 1486 1487 #define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188) 1488 /* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1489 /*description: */ 1490 #define DPORT_PRO_I2S1_INT_MAP 0x0000001F 1491 #define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S)) 1492 #define DPORT_PRO_I2S1_INT_MAP_V 0x1F 1493 #define DPORT_PRO_I2S1_INT_MAP_S 0 1494 1495 #define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C) 1496 /* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1497 /*description: */ 1498 #define DPORT_PRO_UART_INTR_MAP 0x0000001F 1499 #define DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S)) 1500 #define DPORT_PRO_UART_INTR_MAP_V 0x1F 1501 #define DPORT_PRO_UART_INTR_MAP_S 0 1502 1503 #define DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190) 1504 /* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1505 /*description: */ 1506 #define DPORT_PRO_UART1_INTR_MAP 0x0000001F 1507 #define DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S)) 1508 #define DPORT_PRO_UART1_INTR_MAP_V 0x1F 1509 #define DPORT_PRO_UART1_INTR_MAP_S 0 1510 1511 #define DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194) 1512 /* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1513 /*description: */ 1514 #define DPORT_PRO_UART2_INTR_MAP 0x0000001F 1515 #define DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S)) 1516 #define DPORT_PRO_UART2_INTR_MAP_V 0x1F 1517 #define DPORT_PRO_UART2_INTR_MAP_S 0 1518 1519 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198) 1520 /* DPORT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1521 /*description: */ 1522 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F 1523 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S)) 1524 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x1F 1525 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 1526 1527 #define DPORT_PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C) 1528 /* DPORT_PRO_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1529 /*description: */ 1530 #define DPORT_PRO_EMAC_INT_MAP 0x0000001F 1531 #define DPORT_PRO_EMAC_INT_MAP_M ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S)) 1532 #define DPORT_PRO_EMAC_INT_MAP_V 0x1F 1533 #define DPORT_PRO_EMAC_INT_MAP_S 0 1534 1535 #define DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0) 1536 /* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1537 /*description: */ 1538 #define DPORT_PRO_PWM0_INTR_MAP 0x0000001F 1539 #define DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S)) 1540 #define DPORT_PRO_PWM0_INTR_MAP_V 0x1F 1541 #define DPORT_PRO_PWM0_INTR_MAP_S 0 1542 1543 #define DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4) 1544 /* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1545 /*description: */ 1546 #define DPORT_PRO_PWM1_INTR_MAP 0x0000001F 1547 #define DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S)) 1548 #define DPORT_PRO_PWM1_INTR_MAP_V 0x1F 1549 #define DPORT_PRO_PWM1_INTR_MAP_S 0 1550 1551 #define DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8) 1552 /* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1553 /*description: */ 1554 #define DPORT_PRO_PWM2_INTR_MAP 0x0000001F 1555 #define DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S)) 1556 #define DPORT_PRO_PWM2_INTR_MAP_V 0x1F 1557 #define DPORT_PRO_PWM2_INTR_MAP_S 0 1558 1559 #define DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC) 1560 /* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1561 /*description: */ 1562 #define DPORT_PRO_PWM3_INTR_MAP 0x0000001F 1563 #define DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S)) 1564 #define DPORT_PRO_PWM3_INTR_MAP_V 0x1F 1565 #define DPORT_PRO_PWM3_INTR_MAP_S 0 1566 1567 #define DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0) 1568 /* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1569 /*description: */ 1570 #define DPORT_PRO_LEDC_INT_MAP 0x0000001F 1571 #define DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S)) 1572 #define DPORT_PRO_LEDC_INT_MAP_V 0x1F 1573 #define DPORT_PRO_LEDC_INT_MAP_S 0 1574 1575 #define DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4) 1576 /* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1577 /*description: */ 1578 #define DPORT_PRO_EFUSE_INT_MAP 0x0000001F 1579 #define DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S)) 1580 #define DPORT_PRO_EFUSE_INT_MAP_V 0x1F 1581 #define DPORT_PRO_EFUSE_INT_MAP_S 0 1582 1583 #define DPORT_PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8) 1584 /* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1585 /*description: */ 1586 #define DPORT_PRO_CAN_INT_MAP 0x0000001F 1587 #define DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S)) 1588 #define DPORT_PRO_CAN_INT_MAP_V 0x1F 1589 #define DPORT_PRO_CAN_INT_MAP_S 0 1590 1591 #define DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC) 1592 /* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1593 /*description: */ 1594 #define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F 1595 #define DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S)) 1596 #define DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F 1597 #define DPORT_PRO_RTC_CORE_INTR_MAP_S 0 1598 1599 #define DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0) 1600 /* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1601 /*description: */ 1602 #define DPORT_PRO_RMT_INTR_MAP 0x0000001F 1603 #define DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S)) 1604 #define DPORT_PRO_RMT_INTR_MAP_V 0x1F 1605 #define DPORT_PRO_RMT_INTR_MAP_S 0 1606 1607 #define DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4) 1608 /* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1609 /*description: */ 1610 #define DPORT_PRO_PCNT_INTR_MAP 0x0000001F 1611 #define DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S)) 1612 #define DPORT_PRO_PCNT_INTR_MAP_V 0x1F 1613 #define DPORT_PRO_PCNT_INTR_MAP_S 0 1614 1615 #define DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8) 1616 /* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1617 /*description: */ 1618 #define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F 1619 #define DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S)) 1620 #define DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F 1621 #define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0 1622 1623 #define DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC) 1624 /* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1625 /*description: */ 1626 #define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F 1627 #define DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S)) 1628 #define DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F 1629 #define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0 1630 1631 #define DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0) 1632 /* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1633 /*description: */ 1634 #define DPORT_PRO_RSA_INTR_MAP 0x0000001F 1635 #define DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S)) 1636 #define DPORT_PRO_RSA_INTR_MAP_V 0x1F 1637 #define DPORT_PRO_RSA_INTR_MAP_S 0 1638 1639 #define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4) 1640 /* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1641 /*description: */ 1642 #define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F 1643 #define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S)) 1644 #define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F 1645 #define DPORT_PRO_SPI1_DMA_INT_MAP_S 0 1646 1647 #define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8) 1648 /* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1649 /*description: */ 1650 #define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F 1651 #define DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S)) 1652 #define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F 1653 #define DPORT_PRO_SPI2_DMA_INT_MAP_S 0 1654 1655 #define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC) 1656 /* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1657 /*description: */ 1658 #define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F 1659 #define DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S)) 1660 #define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F 1661 #define DPORT_PRO_SPI3_DMA_INT_MAP_S 0 1662 1663 #define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0) 1664 /* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1665 /*description: */ 1666 #define DPORT_PRO_WDG_INT_MAP 0x0000001F 1667 #define DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S)) 1668 #define DPORT_PRO_WDG_INT_MAP_V 0x1F 1669 #define DPORT_PRO_WDG_INT_MAP_S 0 1670 1671 #define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4) 1672 /* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1673 /*description: */ 1674 #define DPORT_PRO_TIMER_INT1_MAP 0x0000001F 1675 #define DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S)) 1676 #define DPORT_PRO_TIMER_INT1_MAP_V 0x1F 1677 #define DPORT_PRO_TIMER_INT1_MAP_S 0 1678 1679 #define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8) 1680 /* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1681 /*description: */ 1682 #define DPORT_PRO_TIMER_INT2_MAP 0x0000001F 1683 #define DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S)) 1684 #define DPORT_PRO_TIMER_INT2_MAP_V 0x1F 1685 #define DPORT_PRO_TIMER_INT2_MAP_S 0 1686 1687 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC) 1688 /* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1689 /*description: */ 1690 #define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F 1691 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S)) 1692 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F 1693 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0 1694 1695 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0) 1696 /* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1697 /*description: */ 1698 #define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F 1699 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S)) 1700 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F 1701 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0 1702 1703 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4) 1704 /* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1705 /*description: */ 1706 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F 1707 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S)) 1708 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F 1709 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0 1710 1711 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8) 1712 /* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1713 /*description: */ 1714 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F 1715 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S)) 1716 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F 1717 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0 1718 1719 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC) 1720 /* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1721 /*description: */ 1722 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F 1723 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S)) 1724 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F 1725 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0 1726 1727 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200) 1728 /* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1729 /*description: */ 1730 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F 1731 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S)) 1732 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F 1733 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0 1734 1735 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204) 1736 /* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1737 /*description: */ 1738 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F 1739 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S)) 1740 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F 1741 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 1742 1743 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208) 1744 /* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1745 /*description: */ 1746 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F 1747 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S)) 1748 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F 1749 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 1750 1751 #define DPORT_PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C) 1752 /* DPORT_PRO_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1753 /*description: */ 1754 #define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F 1755 #define DPORT_PRO_MMU_IA_INT_MAP_M ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S)) 1756 #define DPORT_PRO_MMU_IA_INT_MAP_V 0x1F 1757 #define DPORT_PRO_MMU_IA_INT_MAP_S 0 1758 1759 #define DPORT_PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210) 1760 /* DPORT_PRO_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1761 /*description: */ 1762 #define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F 1763 #define DPORT_PRO_MPU_IA_INT_MAP_M ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S)) 1764 #define DPORT_PRO_MPU_IA_INT_MAP_V 0x1F 1765 #define DPORT_PRO_MPU_IA_INT_MAP_S 0 1766 1767 #define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214) 1768 /* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1769 /*description: */ 1770 #define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F 1771 #define DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S)) 1772 #define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F 1773 #define DPORT_PRO_CACHE_IA_INT_MAP_S 0 1774 1775 #define DPORT_APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218) 1776 /* DPORT_APP_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1777 /*description: */ 1778 #define DPORT_APP_MAC_INTR_MAP 0x0000001F 1779 #define DPORT_APP_MAC_INTR_MAP_M ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S)) 1780 #define DPORT_APP_MAC_INTR_MAP_V 0x1F 1781 #define DPORT_APP_MAC_INTR_MAP_S 0 1782 1783 #define DPORT_APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C) 1784 /* DPORT_APP_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1785 /*description: */ 1786 #define DPORT_APP_MAC_NMI_MAP 0x0000001F 1787 #define DPORT_APP_MAC_NMI_MAP_M ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S)) 1788 #define DPORT_APP_MAC_NMI_MAP_V 0x1F 1789 #define DPORT_APP_MAC_NMI_MAP_S 0 1790 1791 #define DPORT_APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220) 1792 /* DPORT_APP_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1793 /*description: */ 1794 #define DPORT_APP_BB_INT_MAP 0x0000001F 1795 #define DPORT_APP_BB_INT_MAP_M ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S)) 1796 #define DPORT_APP_BB_INT_MAP_V 0x1F 1797 #define DPORT_APP_BB_INT_MAP_S 0 1798 1799 #define DPORT_APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224) 1800 /* DPORT_APP_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1801 /*description: */ 1802 #define DPORT_APP_BT_MAC_INT_MAP 0x0000001F 1803 #define DPORT_APP_BT_MAC_INT_MAP_M ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S)) 1804 #define DPORT_APP_BT_MAC_INT_MAP_V 0x1F 1805 #define DPORT_APP_BT_MAC_INT_MAP_S 0 1806 1807 #define DPORT_APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228) 1808 /* DPORT_APP_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1809 /*description: */ 1810 #define DPORT_APP_BT_BB_INT_MAP 0x0000001F 1811 #define DPORT_APP_BT_BB_INT_MAP_M ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S)) 1812 #define DPORT_APP_BT_BB_INT_MAP_V 0x1F 1813 #define DPORT_APP_BT_BB_INT_MAP_S 0 1814 1815 #define DPORT_APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C) 1816 /* DPORT_APP_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1817 /*description: */ 1818 #define DPORT_APP_BT_BB_NMI_MAP 0x0000001F 1819 #define DPORT_APP_BT_BB_NMI_MAP_M ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S)) 1820 #define DPORT_APP_BT_BB_NMI_MAP_V 0x1F 1821 #define DPORT_APP_BT_BB_NMI_MAP_S 0 1822 1823 #define DPORT_APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230) 1824 /* DPORT_APP_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1825 /*description: */ 1826 #define DPORT_APP_RWBT_IRQ_MAP 0x0000001F 1827 #define DPORT_APP_RWBT_IRQ_MAP_M ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S)) 1828 #define DPORT_APP_RWBT_IRQ_MAP_V 0x1F 1829 #define DPORT_APP_RWBT_IRQ_MAP_S 0 1830 1831 #define DPORT_APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234) 1832 /* DPORT_APP_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1833 /*description: */ 1834 #define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F 1835 #define DPORT_APP_RWBLE_IRQ_MAP_M ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S)) 1836 #define DPORT_APP_RWBLE_IRQ_MAP_V 0x1F 1837 #define DPORT_APP_RWBLE_IRQ_MAP_S 0 1838 1839 #define DPORT_APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238) 1840 /* DPORT_APP_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1841 /*description: */ 1842 #define DPORT_APP_RWBT_NMI_MAP 0x0000001F 1843 #define DPORT_APP_RWBT_NMI_MAP_M ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S)) 1844 #define DPORT_APP_RWBT_NMI_MAP_V 0x1F 1845 #define DPORT_APP_RWBT_NMI_MAP_S 0 1846 1847 #define DPORT_APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C) 1848 /* DPORT_APP_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1849 /*description: */ 1850 #define DPORT_APP_RWBLE_NMI_MAP 0x0000001F 1851 #define DPORT_APP_RWBLE_NMI_MAP_M ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S)) 1852 #define DPORT_APP_RWBLE_NMI_MAP_V 0x1F 1853 #define DPORT_APP_RWBLE_NMI_MAP_S 0 1854 1855 #define DPORT_APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240) 1856 /* DPORT_APP_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1857 /*description: */ 1858 #define DPORT_APP_SLC0_INTR_MAP 0x0000001F 1859 #define DPORT_APP_SLC0_INTR_MAP_M ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S)) 1860 #define DPORT_APP_SLC0_INTR_MAP_V 0x1F 1861 #define DPORT_APP_SLC0_INTR_MAP_S 0 1862 1863 #define DPORT_APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244) 1864 /* DPORT_APP_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1865 /*description: */ 1866 #define DPORT_APP_SLC1_INTR_MAP 0x0000001F 1867 #define DPORT_APP_SLC1_INTR_MAP_M ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S)) 1868 #define DPORT_APP_SLC1_INTR_MAP_V 0x1F 1869 #define DPORT_APP_SLC1_INTR_MAP_S 0 1870 1871 #define DPORT_APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248) 1872 /* DPORT_APP_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1873 /*description: */ 1874 #define DPORT_APP_UHCI0_INTR_MAP 0x0000001F 1875 #define DPORT_APP_UHCI0_INTR_MAP_M ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S)) 1876 #define DPORT_APP_UHCI0_INTR_MAP_V 0x1F 1877 #define DPORT_APP_UHCI0_INTR_MAP_S 0 1878 1879 #define DPORT_APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C) 1880 /* DPORT_APP_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1881 /*description: */ 1882 #define DPORT_APP_UHCI1_INTR_MAP 0x0000001F 1883 #define DPORT_APP_UHCI1_INTR_MAP_M ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S)) 1884 #define DPORT_APP_UHCI1_INTR_MAP_V 0x1F 1885 #define DPORT_APP_UHCI1_INTR_MAP_S 0 1886 1887 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250) 1888 /* DPORT_APP_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1889 /*description: */ 1890 #define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F 1891 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S)) 1892 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_V 0x1F 1893 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0 1894 1895 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254) 1896 /* DPORT_APP_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1897 /*description: */ 1898 #define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F 1899 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S)) 1900 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_V 0x1F 1901 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0 1902 1903 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258) 1904 /* DPORT_APP_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1905 /*description: */ 1906 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F 1907 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S)) 1908 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_V 0x1F 1909 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0 1910 1911 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C) 1912 /* DPORT_APP_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1913 /*description: */ 1914 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F 1915 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S)) 1916 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_V 0x1F 1917 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0 1918 1919 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260) 1920 /* DPORT_APP_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1921 /*description: */ 1922 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F 1923 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S)) 1924 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_V 0x1F 1925 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0 1926 1927 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264) 1928 /* DPORT_APP_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1929 /*description: */ 1930 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F 1931 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S)) 1932 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_V 0x1F 1933 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0 1934 1935 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268) 1936 /* DPORT_APP_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1937 /*description: */ 1938 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F 1939 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S)) 1940 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V 0x1F 1941 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0 1942 1943 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C) 1944 /* DPORT_APP_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1945 /*description: */ 1946 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F 1947 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S)) 1948 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V 0x1F 1949 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0 1950 1951 #define DPORT_APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270) 1952 /* DPORT_APP_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1953 /*description: */ 1954 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F 1955 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S)) 1956 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_V 0x1F 1957 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0 1958 1959 #define DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274) 1960 /* DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1961 /*description: */ 1962 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F 1963 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S)) 1964 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F 1965 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0 1966 1967 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278) 1968 /* DPORT_APP_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1969 /*description: */ 1970 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F 1971 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S)) 1972 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V 0x1F 1973 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0 1974 1975 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C) 1976 /* DPORT_APP_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1977 /*description: */ 1978 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F 1979 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S)) 1980 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V 0x1F 1981 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0 1982 1983 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280) 1984 /* DPORT_APP_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1985 /*description: */ 1986 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F 1987 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S)) 1988 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V 0x1F 1989 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0 1990 1991 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284) 1992 /* DPORT_APP_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 1993 /*description: */ 1994 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F 1995 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S)) 1996 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V 0x1F 1997 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0 1998 1999 #define DPORT_APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288) 2000 /* DPORT_APP_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2001 /*description: */ 2002 #define DPORT_APP_SPI_INTR_0_MAP 0x0000001F 2003 #define DPORT_APP_SPI_INTR_0_MAP_M ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S)) 2004 #define DPORT_APP_SPI_INTR_0_MAP_V 0x1F 2005 #define DPORT_APP_SPI_INTR_0_MAP_S 0 2006 2007 #define DPORT_APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C) 2008 /* DPORT_APP_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2009 /*description: */ 2010 #define DPORT_APP_SPI_INTR_1_MAP 0x0000001F 2011 #define DPORT_APP_SPI_INTR_1_MAP_M ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S)) 2012 #define DPORT_APP_SPI_INTR_1_MAP_V 0x1F 2013 #define DPORT_APP_SPI_INTR_1_MAP_S 0 2014 2015 #define DPORT_APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290) 2016 /* DPORT_APP_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2017 /*description: */ 2018 #define DPORT_APP_SPI_INTR_2_MAP 0x0000001F 2019 #define DPORT_APP_SPI_INTR_2_MAP_M ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S)) 2020 #define DPORT_APP_SPI_INTR_2_MAP_V 0x1F 2021 #define DPORT_APP_SPI_INTR_2_MAP_S 0 2022 2023 #define DPORT_APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294) 2024 /* DPORT_APP_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2025 /*description: */ 2026 #define DPORT_APP_SPI_INTR_3_MAP 0x0000001F 2027 #define DPORT_APP_SPI_INTR_3_MAP_M ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S)) 2028 #define DPORT_APP_SPI_INTR_3_MAP_V 0x1F 2029 #define DPORT_APP_SPI_INTR_3_MAP_S 0 2030 2031 #define DPORT_APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298) 2032 /* DPORT_APP_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2033 /*description: */ 2034 #define DPORT_APP_I2S0_INT_MAP 0x0000001F 2035 #define DPORT_APP_I2S0_INT_MAP_M ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S)) 2036 #define DPORT_APP_I2S0_INT_MAP_V 0x1F 2037 #define DPORT_APP_I2S0_INT_MAP_S 0 2038 2039 #define DPORT_APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C) 2040 /* DPORT_APP_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2041 /*description: */ 2042 #define DPORT_APP_I2S1_INT_MAP 0x0000001F 2043 #define DPORT_APP_I2S1_INT_MAP_M ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S)) 2044 #define DPORT_APP_I2S1_INT_MAP_V 0x1F 2045 #define DPORT_APP_I2S1_INT_MAP_S 0 2046 2047 #define DPORT_APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0) 2048 /* DPORT_APP_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2049 /*description: */ 2050 #define DPORT_APP_UART_INTR_MAP 0x0000001F 2051 #define DPORT_APP_UART_INTR_MAP_M ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S)) 2052 #define DPORT_APP_UART_INTR_MAP_V 0x1F 2053 #define DPORT_APP_UART_INTR_MAP_S 0 2054 2055 #define DPORT_APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4) 2056 /* DPORT_APP_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2057 /*description: */ 2058 #define DPORT_APP_UART1_INTR_MAP 0x0000001F 2059 #define DPORT_APP_UART1_INTR_MAP_M ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S)) 2060 #define DPORT_APP_UART1_INTR_MAP_V 0x1F 2061 #define DPORT_APP_UART1_INTR_MAP_S 0 2062 2063 #define DPORT_APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8) 2064 /* DPORT_APP_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2065 /*description: */ 2066 #define DPORT_APP_UART2_INTR_MAP 0x0000001F 2067 #define DPORT_APP_UART2_INTR_MAP_M ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S)) 2068 #define DPORT_APP_UART2_INTR_MAP_V 0x1F 2069 #define DPORT_APP_UART2_INTR_MAP_S 0 2070 2071 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC) 2072 /* DPORT_APP_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2073 /*description: */ 2074 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F 2075 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S)) 2076 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V 0x1F 2077 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0 2078 2079 #define DPORT_APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0) 2080 /* DPORT_APP_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2081 /*description: */ 2082 #define DPORT_APP_EMAC_INT_MAP 0x0000001F 2083 #define DPORT_APP_EMAC_INT_MAP_M ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S)) 2084 #define DPORT_APP_EMAC_INT_MAP_V 0x1F 2085 #define DPORT_APP_EMAC_INT_MAP_S 0 2086 2087 #define DPORT_APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4) 2088 /* DPORT_APP_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2089 /*description: */ 2090 #define DPORT_APP_PWM0_INTR_MAP 0x0000001F 2091 #define DPORT_APP_PWM0_INTR_MAP_M ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S)) 2092 #define DPORT_APP_PWM0_INTR_MAP_V 0x1F 2093 #define DPORT_APP_PWM0_INTR_MAP_S 0 2094 2095 #define DPORT_APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8) 2096 /* DPORT_APP_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2097 /*description: */ 2098 #define DPORT_APP_PWM1_INTR_MAP 0x0000001F 2099 #define DPORT_APP_PWM1_INTR_MAP_M ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S)) 2100 #define DPORT_APP_PWM1_INTR_MAP_V 0x1F 2101 #define DPORT_APP_PWM1_INTR_MAP_S 0 2102 2103 #define DPORT_APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC) 2104 /* DPORT_APP_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2105 /*description: */ 2106 #define DPORT_APP_PWM2_INTR_MAP 0x0000001F 2107 #define DPORT_APP_PWM2_INTR_MAP_M ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S)) 2108 #define DPORT_APP_PWM2_INTR_MAP_V 0x1F 2109 #define DPORT_APP_PWM2_INTR_MAP_S 0 2110 2111 #define DPORT_APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0) 2112 /* DPORT_APP_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2113 /*description: */ 2114 #define DPORT_APP_PWM3_INTR_MAP 0x0000001F 2115 #define DPORT_APP_PWM3_INTR_MAP_M ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S)) 2116 #define DPORT_APP_PWM3_INTR_MAP_V 0x1F 2117 #define DPORT_APP_PWM3_INTR_MAP_S 0 2118 2119 #define DPORT_APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4) 2120 /* DPORT_APP_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2121 /*description: */ 2122 #define DPORT_APP_LEDC_INT_MAP 0x0000001F 2123 #define DPORT_APP_LEDC_INT_MAP_M ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S)) 2124 #define DPORT_APP_LEDC_INT_MAP_V 0x1F 2125 #define DPORT_APP_LEDC_INT_MAP_S 0 2126 2127 #define DPORT_APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8) 2128 /* DPORT_APP_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2129 /*description: */ 2130 #define DPORT_APP_EFUSE_INT_MAP 0x0000001F 2131 #define DPORT_APP_EFUSE_INT_MAP_M ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S)) 2132 #define DPORT_APP_EFUSE_INT_MAP_V 0x1F 2133 #define DPORT_APP_EFUSE_INT_MAP_S 0 2134 2135 #define DPORT_APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC) 2136 /* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2137 /*description: */ 2138 #define DPORT_APP_CAN_INT_MAP 0x0000001F 2139 #define DPORT_APP_CAN_INT_MAP_M ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S)) 2140 #define DPORT_APP_CAN_INT_MAP_V 0x1F 2141 #define DPORT_APP_CAN_INT_MAP_S 0 2142 2143 #define DPORT_APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0) 2144 /* DPORT_APP_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2145 /*description: */ 2146 #define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F 2147 #define DPORT_APP_RTC_CORE_INTR_MAP_M ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S)) 2148 #define DPORT_APP_RTC_CORE_INTR_MAP_V 0x1F 2149 #define DPORT_APP_RTC_CORE_INTR_MAP_S 0 2150 2151 #define DPORT_APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4) 2152 /* DPORT_APP_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2153 /*description: */ 2154 #define DPORT_APP_RMT_INTR_MAP 0x0000001F 2155 #define DPORT_APP_RMT_INTR_MAP_M ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S)) 2156 #define DPORT_APP_RMT_INTR_MAP_V 0x1F 2157 #define DPORT_APP_RMT_INTR_MAP_S 0 2158 2159 #define DPORT_APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8) 2160 /* DPORT_APP_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2161 /*description: */ 2162 #define DPORT_APP_PCNT_INTR_MAP 0x0000001F 2163 #define DPORT_APP_PCNT_INTR_MAP_M ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S)) 2164 #define DPORT_APP_PCNT_INTR_MAP_V 0x1F 2165 #define DPORT_APP_PCNT_INTR_MAP_S 0 2166 2167 #define DPORT_APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC) 2168 /* DPORT_APP_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2169 /*description: */ 2170 #define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F 2171 #define DPORT_APP_I2C_EXT0_INTR_MAP_M ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S)) 2172 #define DPORT_APP_I2C_EXT0_INTR_MAP_V 0x1F 2173 #define DPORT_APP_I2C_EXT0_INTR_MAP_S 0 2174 2175 #define DPORT_APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0) 2176 /* DPORT_APP_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2177 /*description: */ 2178 #define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F 2179 #define DPORT_APP_I2C_EXT1_INTR_MAP_M ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S)) 2180 #define DPORT_APP_I2C_EXT1_INTR_MAP_V 0x1F 2181 #define DPORT_APP_I2C_EXT1_INTR_MAP_S 0 2182 2183 #define DPORT_APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4) 2184 /* DPORT_APP_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2185 /*description: */ 2186 #define DPORT_APP_RSA_INTR_MAP 0x0000001F 2187 #define DPORT_APP_RSA_INTR_MAP_M ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S)) 2188 #define DPORT_APP_RSA_INTR_MAP_V 0x1F 2189 #define DPORT_APP_RSA_INTR_MAP_S 0 2190 2191 #define DPORT_APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8) 2192 /* DPORT_APP_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2193 /*description: */ 2194 #define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F 2195 #define DPORT_APP_SPI1_DMA_INT_MAP_M ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S)) 2196 #define DPORT_APP_SPI1_DMA_INT_MAP_V 0x1F 2197 #define DPORT_APP_SPI1_DMA_INT_MAP_S 0 2198 2199 #define DPORT_APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC) 2200 /* DPORT_APP_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2201 /*description: */ 2202 #define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F 2203 #define DPORT_APP_SPI2_DMA_INT_MAP_M ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S)) 2204 #define DPORT_APP_SPI2_DMA_INT_MAP_V 0x1F 2205 #define DPORT_APP_SPI2_DMA_INT_MAP_S 0 2206 2207 #define DPORT_APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0) 2208 /* DPORT_APP_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2209 /*description: */ 2210 #define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F 2211 #define DPORT_APP_SPI3_DMA_INT_MAP_M ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S)) 2212 #define DPORT_APP_SPI3_DMA_INT_MAP_V 0x1F 2213 #define DPORT_APP_SPI3_DMA_INT_MAP_S 0 2214 2215 #define DPORT_APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4) 2216 /* DPORT_APP_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2217 /*description: */ 2218 #define DPORT_APP_WDG_INT_MAP 0x0000001F 2219 #define DPORT_APP_WDG_INT_MAP_M ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S)) 2220 #define DPORT_APP_WDG_INT_MAP_V 0x1F 2221 #define DPORT_APP_WDG_INT_MAP_S 0 2222 2223 #define DPORT_APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8) 2224 /* DPORT_APP_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2225 /*description: */ 2226 #define DPORT_APP_TIMER_INT1_MAP 0x0000001F 2227 #define DPORT_APP_TIMER_INT1_MAP_M ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S)) 2228 #define DPORT_APP_TIMER_INT1_MAP_V 0x1F 2229 #define DPORT_APP_TIMER_INT1_MAP_S 0 2230 2231 #define DPORT_APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC) 2232 /* DPORT_APP_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2233 /*description: */ 2234 #define DPORT_APP_TIMER_INT2_MAP 0x0000001F 2235 #define DPORT_APP_TIMER_INT2_MAP_M ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S)) 2236 #define DPORT_APP_TIMER_INT2_MAP_V 0x1F 2237 #define DPORT_APP_TIMER_INT2_MAP_S 0 2238 2239 #define DPORT_APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300) 2240 /* DPORT_APP_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2241 /*description: */ 2242 #define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F 2243 #define DPORT_APP_TG_T0_EDGE_INT_MAP_M ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S)) 2244 #define DPORT_APP_TG_T0_EDGE_INT_MAP_V 0x1F 2245 #define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0 2246 2247 #define DPORT_APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304) 2248 /* DPORT_APP_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2249 /*description: */ 2250 #define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F 2251 #define DPORT_APP_TG_T1_EDGE_INT_MAP_M ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S)) 2252 #define DPORT_APP_TG_T1_EDGE_INT_MAP_V 0x1F 2253 #define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0 2254 2255 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308) 2256 /* DPORT_APP_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2257 /*description: */ 2258 #define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F 2259 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S)) 2260 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_V 0x1F 2261 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0 2262 2263 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C) 2264 /* DPORT_APP_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2265 /*description: */ 2266 #define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F 2267 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S)) 2268 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_V 0x1F 2269 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0 2270 2271 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310) 2272 /* DPORT_APP_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2273 /*description: */ 2274 #define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F 2275 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_M ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S)) 2276 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_V 0x1F 2277 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0 2278 2279 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314) 2280 /* DPORT_APP_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2281 /*description: */ 2282 #define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F 2283 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_M ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S)) 2284 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_V 0x1F 2285 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0 2286 2287 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318) 2288 /* DPORT_APP_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2289 /*description: */ 2290 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F 2291 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S)) 2292 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_V 0x1F 2293 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0 2294 2295 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C) 2296 /* DPORT_APP_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2297 /*description: */ 2298 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F 2299 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S)) 2300 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_V 0x1F 2301 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0 2302 2303 #define DPORT_APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320) 2304 /* DPORT_APP_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2305 /*description: */ 2306 #define DPORT_APP_MMU_IA_INT_MAP 0x0000001F 2307 #define DPORT_APP_MMU_IA_INT_MAP_M ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S)) 2308 #define DPORT_APP_MMU_IA_INT_MAP_V 0x1F 2309 #define DPORT_APP_MMU_IA_INT_MAP_S 0 2310 2311 #define DPORT_APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324) 2312 /* DPORT_APP_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2313 /*description: */ 2314 #define DPORT_APP_MPU_IA_INT_MAP 0x0000001F 2315 #define DPORT_APP_MPU_IA_INT_MAP_M ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S)) 2316 #define DPORT_APP_MPU_IA_INT_MAP_V 0x1F 2317 #define DPORT_APP_MPU_IA_INT_MAP_S 0 2318 2319 #define DPORT_APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328) 2320 /* DPORT_APP_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ 2321 /*description: */ 2322 #define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F 2323 #define DPORT_APP_CACHE_IA_INT_MAP_M ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S)) 2324 #define DPORT_APP_CACHE_IA_INT_MAP_V 0x1F 2325 #define DPORT_APP_CACHE_IA_INT_MAP_S 0 2326 2327 #define DPORT_AHBLITE_MPU_TABLE_UART_REG (DR_REG_DPORT_BASE + 0x32C) 2328 /* DPORT_UART_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2329 /*description: */ 2330 #define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F 2331 #define DPORT_UART_ACCESS_GRANT_CONFIG_M ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S)) 2332 #define DPORT_UART_ACCESS_GRANT_CONFIG_V 0x3F 2333 #define DPORT_UART_ACCESS_GRANT_CONFIG_S 0 2334 2335 #define DPORT_AHBLITE_MPU_TABLE_SPI1_REG (DR_REG_DPORT_BASE + 0x330) 2336 /* DPORT_SPI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2337 /*description: */ 2338 #define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F 2339 #define DPORT_SPI1_ACCESS_GRANT_CONFIG_M ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S)) 2340 #define DPORT_SPI1_ACCESS_GRANT_CONFIG_V 0x3F 2341 #define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0 2342 2343 #define DPORT_AHBLITE_MPU_TABLE_SPI0_REG (DR_REG_DPORT_BASE + 0x334) 2344 /* DPORT_SPI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2345 /*description: */ 2346 #define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F 2347 #define DPORT_SPI0_ACCESS_GRANT_CONFIG_M ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S)) 2348 #define DPORT_SPI0_ACCESS_GRANT_CONFIG_V 0x3F 2349 #define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0 2350 2351 #define DPORT_AHBLITE_MPU_TABLE_GPIO_REG (DR_REG_DPORT_BASE + 0x338) 2352 /* DPORT_GPIO_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2353 /*description: */ 2354 #define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F 2355 #define DPORT_GPIO_ACCESS_GRANT_CONFIG_M ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S)) 2356 #define DPORT_GPIO_ACCESS_GRANT_CONFIG_V 0x3F 2357 #define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0 2358 2359 #define DPORT_AHBLITE_MPU_TABLE_FE2_REG (DR_REG_DPORT_BASE + 0x33C) 2360 /* DPORT_FE2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2361 /*description: */ 2362 #define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F 2363 #define DPORT_FE2_ACCESS_GRANT_CONFIG_M ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S)) 2364 #define DPORT_FE2_ACCESS_GRANT_CONFIG_V 0x3F 2365 #define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0 2366 2367 #define DPORT_AHBLITE_MPU_TABLE_FE_REG (DR_REG_DPORT_BASE + 0x340) 2368 /* DPORT_FE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2369 /*description: */ 2370 #define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F 2371 #define DPORT_FE_ACCESS_GRANT_CONFIG_M ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S)) 2372 #define DPORT_FE_ACCESS_GRANT_CONFIG_V 0x3F 2373 #define DPORT_FE_ACCESS_GRANT_CONFIG_S 0 2374 2375 #define DPORT_AHBLITE_MPU_TABLE_TIMER_REG (DR_REG_DPORT_BASE + 0x344) 2376 /* DPORT_TIMER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2377 /*description: */ 2378 #define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F 2379 #define DPORT_TIMER_ACCESS_GRANT_CONFIG_M ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S)) 2380 #define DPORT_TIMER_ACCESS_GRANT_CONFIG_V 0x3F 2381 #define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0 2382 2383 #define DPORT_AHBLITE_MPU_TABLE_RTC_REG (DR_REG_DPORT_BASE + 0x348) 2384 /* DPORT_RTC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2385 /*description: */ 2386 #define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F 2387 #define DPORT_RTC_ACCESS_GRANT_CONFIG_M ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S)) 2388 #define DPORT_RTC_ACCESS_GRANT_CONFIG_V 0x3F 2389 #define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0 2390 2391 #define DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (DR_REG_DPORT_BASE + 0x34C) 2392 /* DPORT_IOMUX_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2393 /*description: */ 2394 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F 2395 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_M ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S)) 2396 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_V 0x3F 2397 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0 2398 2399 #define DPORT_AHBLITE_MPU_TABLE_WDG_REG (DR_REG_DPORT_BASE + 0x350) 2400 /* DPORT_WDG_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2401 /*description: */ 2402 #define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F 2403 #define DPORT_WDG_ACCESS_GRANT_CONFIG_M ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S)) 2404 #define DPORT_WDG_ACCESS_GRANT_CONFIG_V 0x3F 2405 #define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0 2406 2407 #define DPORT_AHBLITE_MPU_TABLE_HINF_REG (DR_REG_DPORT_BASE + 0x354) 2408 /* DPORT_HINF_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2409 /*description: */ 2410 #define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F 2411 #define DPORT_HINF_ACCESS_GRANT_CONFIG_M ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S)) 2412 #define DPORT_HINF_ACCESS_GRANT_CONFIG_V 0x3F 2413 #define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0 2414 2415 #define DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (DR_REG_DPORT_BASE + 0x358) 2416 /* DPORT_UHCI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2417 /*description: */ 2418 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F 2419 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S)) 2420 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_V 0x3F 2421 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0 2422 2423 #define DPORT_AHBLITE_MPU_TABLE_MISC_REG (DR_REG_DPORT_BASE + 0x35C) 2424 /* DPORT_MISC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2425 /*description: */ 2426 #define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F 2427 #define DPORT_MISC_ACCESS_GRANT_CONFIG_M ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S)) 2428 #define DPORT_MISC_ACCESS_GRANT_CONFIG_V 0x3F 2429 #define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0 2430 2431 #define DPORT_AHBLITE_MPU_TABLE_I2C_REG (DR_REG_DPORT_BASE + 0x360) 2432 /* DPORT_I2C_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2433 /*description: */ 2434 #define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F 2435 #define DPORT_I2C_ACCESS_GRANT_CONFIG_M ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S)) 2436 #define DPORT_I2C_ACCESS_GRANT_CONFIG_V 0x3F 2437 #define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0 2438 2439 #define DPORT_AHBLITE_MPU_TABLE_I2S0_REG (DR_REG_DPORT_BASE + 0x364) 2440 /* DPORT_I2S0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2441 /*description: */ 2442 #define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F 2443 #define DPORT_I2S0_ACCESS_GRANT_CONFIG_M ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S)) 2444 #define DPORT_I2S0_ACCESS_GRANT_CONFIG_V 0x3F 2445 #define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0 2446 2447 #define DPORT_AHBLITE_MPU_TABLE_UART1_REG (DR_REG_DPORT_BASE + 0x368) 2448 /* DPORT_UART1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2449 /*description: */ 2450 #define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F 2451 #define DPORT_UART1_ACCESS_GRANT_CONFIG_M ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S)) 2452 #define DPORT_UART1_ACCESS_GRANT_CONFIG_V 0x3F 2453 #define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0 2454 2455 #define DPORT_AHBLITE_MPU_TABLE_BT_REG (DR_REG_DPORT_BASE + 0x36C) 2456 /* DPORT_BT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2457 /*description: */ 2458 #define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F 2459 #define DPORT_BT_ACCESS_GRANT_CONFIG_M ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S)) 2460 #define DPORT_BT_ACCESS_GRANT_CONFIG_V 0x3F 2461 #define DPORT_BT_ACCESS_GRANT_CONFIG_S 0 2462 2463 #define DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG (DR_REG_DPORT_BASE + 0x370) 2464 /* DPORT_BTBUFFER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2465 /*description: */ 2466 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F 2467 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S)) 2468 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V 0x3F 2469 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0 2470 2471 #define DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (DR_REG_DPORT_BASE + 0x374) 2472 /* DPORT_I2CEXT0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2473 /*description: */ 2474 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F 2475 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S)) 2476 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V 0x3F 2477 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0 2478 2479 #define DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (DR_REG_DPORT_BASE + 0x378) 2480 /* DPORT_UHCI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2481 /*description: */ 2482 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F 2483 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S)) 2484 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_V 0x3F 2485 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0 2486 2487 #define DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (DR_REG_DPORT_BASE + 0x37C) 2488 /* DPORT_SLCHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2489 /*description: */ 2490 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F 2491 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S)) 2492 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V 0x3F 2493 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0 2494 2495 #define DPORT_AHBLITE_MPU_TABLE_RMT_REG (DR_REG_DPORT_BASE + 0x380) 2496 /* DPORT_RMT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2497 /*description: */ 2498 #define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F 2499 #define DPORT_RMT_ACCESS_GRANT_CONFIG_M ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S)) 2500 #define DPORT_RMT_ACCESS_GRANT_CONFIG_V 0x3F 2501 #define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0 2502 2503 #define DPORT_AHBLITE_MPU_TABLE_PCNT_REG (DR_REG_DPORT_BASE + 0x384) 2504 /* DPORT_PCNT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2505 /*description: */ 2506 #define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F 2507 #define DPORT_PCNT_ACCESS_GRANT_CONFIG_M ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S)) 2508 #define DPORT_PCNT_ACCESS_GRANT_CONFIG_V 0x3F 2509 #define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0 2510 2511 #define DPORT_AHBLITE_MPU_TABLE_SLC_REG (DR_REG_DPORT_BASE + 0x388) 2512 /* DPORT_SLC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2513 /*description: */ 2514 #define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F 2515 #define DPORT_SLC_ACCESS_GRANT_CONFIG_M ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S)) 2516 #define DPORT_SLC_ACCESS_GRANT_CONFIG_V 0x3F 2517 #define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0 2518 2519 #define DPORT_AHBLITE_MPU_TABLE_LEDC_REG (DR_REG_DPORT_BASE + 0x38C) 2520 /* DPORT_LEDC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2521 /*description: */ 2522 #define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F 2523 #define DPORT_LEDC_ACCESS_GRANT_CONFIG_M ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S)) 2524 #define DPORT_LEDC_ACCESS_GRANT_CONFIG_V 0x3F 2525 #define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0 2526 2527 #define DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (DR_REG_DPORT_BASE + 0x390) 2528 /* DPORT_EFUSE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2529 /*description: */ 2530 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F 2531 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_M ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S)) 2532 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_V 0x3F 2533 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0 2534 2535 #define DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (DR_REG_DPORT_BASE + 0x394) 2536 /* DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2537 /*description: */ 2538 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F 2539 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S)) 2540 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V 0x3F 2541 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0 2542 2543 #define DPORT_AHBLITE_MPU_TABLE_BB_REG (DR_REG_DPORT_BASE + 0x398) 2544 /* DPORT_BB_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2545 /*description: */ 2546 #define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F 2547 #define DPORT_BB_ACCESS_GRANT_CONFIG_M ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S)) 2548 #define DPORT_BB_ACCESS_GRANT_CONFIG_V 0x3F 2549 #define DPORT_BB_ACCESS_GRANT_CONFIG_S 0 2550 2551 #define DPORT_AHBLITE_MPU_TABLE_PWM0_REG (DR_REG_DPORT_BASE + 0x39C) 2552 /* DPORT_PWM0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2553 /*description: */ 2554 #define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F 2555 #define DPORT_PWM0_ACCESS_GRANT_CONFIG_M ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S)) 2556 #define DPORT_PWM0_ACCESS_GRANT_CONFIG_V 0x3F 2557 #define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0 2558 2559 #define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (DR_REG_DPORT_BASE + 0x3A0) 2560 /* DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2561 /*description: */ 2562 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F 2563 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S)) 2564 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V 0x3F 2565 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0 2566 2567 #define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (DR_REG_DPORT_BASE + 0x3A4) 2568 /* DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2569 /*description: */ 2570 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F 2571 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S)) 2572 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V 0x3F 2573 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0 2574 2575 #define DPORT_AHBLITE_MPU_TABLE_SPI2_REG (DR_REG_DPORT_BASE + 0x3A8) 2576 /* DPORT_SPI2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2577 /*description: */ 2578 #define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F 2579 #define DPORT_SPI2_ACCESS_GRANT_CONFIG_M ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S)) 2580 #define DPORT_SPI2_ACCESS_GRANT_CONFIG_V 0x3F 2581 #define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0 2582 2583 #define DPORT_AHBLITE_MPU_TABLE_SPI3_REG (DR_REG_DPORT_BASE + 0x3AC) 2584 /* DPORT_SPI3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2585 /*description: */ 2586 #define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F 2587 #define DPORT_SPI3_ACCESS_GRANT_CONFIG_M ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S)) 2588 #define DPORT_SPI3_ACCESS_GRANT_CONFIG_V 0x3F 2589 #define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0 2590 2591 #define DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG (DR_REG_DPORT_BASE + 0x3B0) 2592 /* DPORT_APBCTRL_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2593 /*description: */ 2594 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F 2595 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S)) 2596 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V 0x3F 2597 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0 2598 2599 #define DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (DR_REG_DPORT_BASE + 0x3B4) 2600 /* DPORT_I2CEXT1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2601 /*description: */ 2602 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F 2603 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S)) 2604 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V 0x3F 2605 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0 2606 2607 #define DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (DR_REG_DPORT_BASE + 0x3B8) 2608 /* DPORT_SDIOHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2609 /*description: */ 2610 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F 2611 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S)) 2612 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V 0x3F 2613 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0 2614 2615 #define DPORT_AHBLITE_MPU_TABLE_EMAC_REG (DR_REG_DPORT_BASE + 0x3BC) 2616 /* DPORT_EMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2617 /*description: */ 2618 #define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F 2619 #define DPORT_EMAC_ACCESS_GRANT_CONFIG_M ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S)) 2620 #define DPORT_EMAC_ACCESS_GRANT_CONFIG_V 0x3F 2621 #define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0 2622 2623 #define DPORT_AHBLITE_MPU_TABLE_CAN_REG (DR_REG_DPORT_BASE + 0x3C0) 2624 /* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2625 /*description: */ 2626 #define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F 2627 #define DPORT_CAN_ACCESS_GRANT_CONFIG_M ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S)) 2628 #define DPORT_CAN_ACCESS_GRANT_CONFIG_V 0x3F 2629 #define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0 2630 2631 #define DPORT_AHBLITE_MPU_TABLE_PWM1_REG (DR_REG_DPORT_BASE + 0x3C4) 2632 /* DPORT_PWM1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2633 /*description: */ 2634 #define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F 2635 #define DPORT_PWM1_ACCESS_GRANT_CONFIG_M ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S)) 2636 #define DPORT_PWM1_ACCESS_GRANT_CONFIG_V 0x3F 2637 #define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0 2638 2639 #define DPORT_AHBLITE_MPU_TABLE_I2S1_REG (DR_REG_DPORT_BASE + 0x3C8) 2640 /* DPORT_I2S1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2641 /*description: */ 2642 #define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F 2643 #define DPORT_I2S1_ACCESS_GRANT_CONFIG_M ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S)) 2644 #define DPORT_I2S1_ACCESS_GRANT_CONFIG_V 0x3F 2645 #define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0 2646 2647 #define DPORT_AHBLITE_MPU_TABLE_UART2_REG (DR_REG_DPORT_BASE + 0x3CC) 2648 /* DPORT_UART2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2649 /*description: */ 2650 #define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F 2651 #define DPORT_UART2_ACCESS_GRANT_CONFIG_M ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S)) 2652 #define DPORT_UART2_ACCESS_GRANT_CONFIG_V 0x3F 2653 #define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0 2654 2655 #define DPORT_AHBLITE_MPU_TABLE_PWM2_REG (DR_REG_DPORT_BASE + 0x3D0) 2656 /* DPORT_PWM2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2657 /*description: */ 2658 #define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F 2659 #define DPORT_PWM2_ACCESS_GRANT_CONFIG_M ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S)) 2660 #define DPORT_PWM2_ACCESS_GRANT_CONFIG_V 0x3F 2661 #define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0 2662 2663 #define DPORT_AHBLITE_MPU_TABLE_PWM3_REG (DR_REG_DPORT_BASE + 0x3D4) 2664 /* DPORT_PWM3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2665 /*description: */ 2666 #define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F 2667 #define DPORT_PWM3_ACCESS_GRANT_CONFIG_M ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S)) 2668 #define DPORT_PWM3_ACCESS_GRANT_CONFIG_V 0x3F 2669 #define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0 2670 2671 #define DPORT_AHBLITE_MPU_TABLE_RWBT_REG (DR_REG_DPORT_BASE + 0x3D8) 2672 /* DPORT_RWBT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2673 /*description: */ 2674 #define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F 2675 #define DPORT_RWBT_ACCESS_GRANT_CONFIG_M ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S)) 2676 #define DPORT_RWBT_ACCESS_GRANT_CONFIG_V 0x3F 2677 #define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0 2678 2679 #define DPORT_AHBLITE_MPU_TABLE_BTMAC_REG (DR_REG_DPORT_BASE + 0x3DC) 2680 /* DPORT_BTMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2681 /*description: */ 2682 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F 2683 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_M ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S)) 2684 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_V 0x3F 2685 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0 2686 2687 #define DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG (DR_REG_DPORT_BASE + 0x3E0) 2688 /* DPORT_WIFIMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2689 /*description: */ 2690 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F 2691 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S)) 2692 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V 0x3F 2693 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0 2694 2695 #define DPORT_AHBLITE_MPU_TABLE_PWR_REG (DR_REG_DPORT_BASE + 0x3E4) 2696 /* DPORT_PWR_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 2697 /*description: */ 2698 #define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F 2699 #define DPORT_PWR_ACCESS_GRANT_CONFIG_M ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S)) 2700 #define DPORT_PWR_ACCESS_GRANT_CONFIG_V 0x3F 2701 #define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0 2702 2703 #define DPORT_MEM_ACCESS_DBUG0_REG (DR_REG_DPORT_BASE + 0x3E8) 2704 /* DPORT_INTERNAL_SRAM_MMU_MULTI_HIT : RO ;bitpos:[29:26] ;default: 4'b0 ; */ 2705 /*description: */ 2706 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F 2707 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S)) 2708 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V 0xF 2709 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26 2710 /* DPORT_INTERNAL_SRAM_IA : RO ;bitpos:[25:14] ;default: 12'b0 ; */ 2711 /*description: */ 2712 #define DPORT_INTERNAL_SRAM_IA 0x00000FFF 2713 #define DPORT_INTERNAL_SRAM_IA_M ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S)) 2714 #define DPORT_INTERNAL_SRAM_IA_V 0xFFF 2715 #define DPORT_INTERNAL_SRAM_IA_S 14 2716 /* DPORT_INTERNAL_SRAM_MMU_AD : RO ;bitpos:[13:10] ;default: 4'b0 ; */ 2717 /*description: */ 2718 #define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F 2719 #define DPORT_INTERNAL_SRAM_MMU_AD_M ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S)) 2720 #define DPORT_INTERNAL_SRAM_MMU_AD_V 0xF 2721 #define DPORT_INTERNAL_SRAM_MMU_AD_S 10 2722 /* DPORT_SHARE_ROM_IA : RO ;bitpos:[9:6] ;default: 4'b0 ; */ 2723 /*description: */ 2724 #define DPORT_SHARE_ROM_IA 0x0000000F 2725 #define DPORT_SHARE_ROM_IA_M ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S)) 2726 #define DPORT_SHARE_ROM_IA_V 0xF 2727 #define DPORT_SHARE_ROM_IA_S 6 2728 /* DPORT_SHARE_ROM_MPU_AD : RO ;bitpos:[5:4] ;default: 2'b0 ; */ 2729 /*description: */ 2730 #define DPORT_SHARE_ROM_MPU_AD 0x00000003 2731 #define DPORT_SHARE_ROM_MPU_AD_M ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S)) 2732 #define DPORT_SHARE_ROM_MPU_AD_V 0x3 2733 #define DPORT_SHARE_ROM_MPU_AD_S 4 2734 /* DPORT_APP_ROM_IA : RO ;bitpos:[3] ;default: 1'b0 ; */ 2735 /*description: */ 2736 #define DPORT_APP_ROM_IA (BIT(3)) 2737 #define DPORT_APP_ROM_IA_M (BIT(3)) 2738 #define DPORT_APP_ROM_IA_V 0x1 2739 #define DPORT_APP_ROM_IA_S 3 2740 /* DPORT_APP_ROM_MPU_AD : RO ;bitpos:[2] ;default: 1'b0 ; */ 2741 /*description: */ 2742 #define DPORT_APP_ROM_MPU_AD (BIT(2)) 2743 #define DPORT_APP_ROM_MPU_AD_M (BIT(2)) 2744 #define DPORT_APP_ROM_MPU_AD_V 0x1 2745 #define DPORT_APP_ROM_MPU_AD_S 2 2746 /* DPORT_PRO_ROM_IA : RO ;bitpos:[1] ;default: 1'b0 ; */ 2747 /*description: */ 2748 #define DPORT_PRO_ROM_IA (BIT(1)) 2749 #define DPORT_PRO_ROM_IA_M (BIT(1)) 2750 #define DPORT_PRO_ROM_IA_V 0x1 2751 #define DPORT_PRO_ROM_IA_S 1 2752 /* DPORT_PRO_ROM_MPU_AD : RO ;bitpos:[0] ;default: 1'b0 ; */ 2753 /*description: */ 2754 #define DPORT_PRO_ROM_MPU_AD (BIT(0)) 2755 #define DPORT_PRO_ROM_MPU_AD_M (BIT(0)) 2756 #define DPORT_PRO_ROM_MPU_AD_V 0x1 2757 #define DPORT_PRO_ROM_MPU_AD_S 0 2758 2759 #define DPORT_MEM_ACCESS_DBUG1_REG (DR_REG_DPORT_BASE + 0x3EC) 2760 /* DPORT_AHBLITE_IA : RO ;bitpos:[10] ;default: 1'b0 ; */ 2761 /*description: */ 2762 #define DPORT_AHBLITE_IA (BIT(10)) 2763 #define DPORT_AHBLITE_IA_M (BIT(10)) 2764 #define DPORT_AHBLITE_IA_V 0x1 2765 #define DPORT_AHBLITE_IA_S 10 2766 /* DPORT_AHBLITE_ACCESS_DENY : RO ;bitpos:[9] ;default: 1'b0 ; */ 2767 /*description: */ 2768 #define DPORT_AHBLITE_ACCESS_DENY (BIT(9)) 2769 #define DPORT_AHBLITE_ACCESS_DENY_M (BIT(9)) 2770 #define DPORT_AHBLITE_ACCESS_DENY_V 0x1 2771 #define DPORT_AHBLITE_ACCESS_DENY_S 9 2772 /* DPORT_AHB_ACCESS_DENY : RO ;bitpos:[8] ;default: 1'b0 ; */ 2773 /*description: */ 2774 #define DPORT_AHB_ACCESS_DENY (BIT(8)) 2775 #define DPORT_AHB_ACCESS_DENY_M (BIT(8)) 2776 #define DPORT_AHB_ACCESS_DENY_V 0x1 2777 #define DPORT_AHB_ACCESS_DENY_S 8 2778 /* DPORT_PIDGEN_IA : RO ;bitpos:[7:6] ;default: 2'b0 ; */ 2779 /*description: */ 2780 #define DPORT_PIDGEN_IA 0x00000003 2781 #define DPORT_PIDGEN_IA_M ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S)) 2782 #define DPORT_PIDGEN_IA_V 0x3 2783 #define DPORT_PIDGEN_IA_S 6 2784 /* DPORT_ARB_IA : RO ;bitpos:[5:4] ;default: 2'b0 ; */ 2785 /*description: */ 2786 #define DPORT_ARB_IA 0x00000003 2787 #define DPORT_ARB_IA_M ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S)) 2788 #define DPORT_ARB_IA_V 0x3 2789 #define DPORT_ARB_IA_S 4 2790 /* DPORT_INTERNAL_SRAM_MMU_MISS : RO ;bitpos:[3:0] ;default: 4'b0 ; */ 2791 /*description: */ 2792 #define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F 2793 #define DPORT_INTERNAL_SRAM_MMU_MISS_M ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S)) 2794 #define DPORT_INTERNAL_SRAM_MMU_MISS_V 0xF 2795 #define DPORT_INTERNAL_SRAM_MMU_MISS_S 0 2796 2797 #define DPORT_PRO_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x3F0) 2798 /* DPORT_PRO_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ 2799 /*description: */ 2800 #define DPORT_PRO_RX_END (BIT(23)) 2801 #define DPORT_PRO_RX_END_M (BIT(23)) 2802 #define DPORT_PRO_RX_END_V 0x1 2803 #define DPORT_PRO_RX_END_S 23 2804 /* DPORT_PRO_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ 2805 /*description: */ 2806 #define DPORT_PRO_SLAVE_WDATA_V (BIT(22)) 2807 #define DPORT_PRO_SLAVE_WDATA_V_M (BIT(22)) 2808 #define DPORT_PRO_SLAVE_WDATA_V_V 0x1 2809 #define DPORT_PRO_SLAVE_WDATA_V_S 22 2810 /* DPORT_PRO_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ 2811 /*description: */ 2812 #define DPORT_PRO_SLAVE_WR (BIT(21)) 2813 #define DPORT_PRO_SLAVE_WR_M (BIT(21)) 2814 #define DPORT_PRO_SLAVE_WR_V 0x1 2815 #define DPORT_PRO_SLAVE_WR_S 21 2816 /* DPORT_PRO_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ 2817 /*description: */ 2818 #define DPORT_PRO_TX_END (BIT(20)) 2819 #define DPORT_PRO_TX_END_M (BIT(20)) 2820 #define DPORT_PRO_TX_END_V 0x1 2821 #define DPORT_PRO_TX_END_S 20 2822 /* DPORT_PRO_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ 2823 /*description: */ 2824 #define DPORT_PRO_WR_BAK_TO_READ (BIT(19)) 2825 #define DPORT_PRO_WR_BAK_TO_READ_M (BIT(19)) 2826 #define DPORT_PRO_WR_BAK_TO_READ_V 0x1 2827 #define DPORT_PRO_WR_BAK_TO_READ_S 19 2828 /* DPORT_PRO_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ 2829 /*description: */ 2830 #define DPORT_PRO_CACHE_STATE 0x00000FFF 2831 #define DPORT_PRO_CACHE_STATE_M ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S)) 2832 #define DPORT_PRO_CACHE_STATE_V 0xFFF 2833 #define DPORT_PRO_CACHE_STATE_S 7 2834 /* DPORT_PRO_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ 2835 /*description: */ 2836 #define DPORT_PRO_CACHE_IA 0x0000003F 2837 #define DPORT_PRO_CACHE_IA_M ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S)) 2838 #define DPORT_PRO_CACHE_IA_V 0x3F 2839 #define DPORT_PRO_CACHE_IA_S 1 2840 /* DPORT_PRO_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ 2841 /*description: */ 2842 #define DPORT_PRO_CACHE_MMU_IA (BIT(0)) 2843 #define DPORT_PRO_CACHE_MMU_IA_M (BIT(0)) 2844 #define DPORT_PRO_CACHE_MMU_IA_V 0x1 2845 #define DPORT_PRO_CACHE_MMU_IA_S 0 2846 2847 #define DPORT_PRO_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x3F4) 2848 /* DPORT_PRO_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 2849 /*description: */ 2850 #define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF 2851 #define DPORT_PRO_CTAG_RAM_RDATA_M ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S)) 2852 #define DPORT_PRO_CTAG_RAM_RDATA_V 0xFFFFFFFF 2853 #define DPORT_PRO_CTAG_RAM_RDATA_S 0 2854 2855 #define DPORT_PRO_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x3F8) 2856 /* DPORT_PRO_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ 2857 /*description: */ 2858 #define DPORT_PRO_CACHE_VADDR 0x07FFFFFF 2859 #define DPORT_PRO_CACHE_VADDR_M ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S)) 2860 #define DPORT_PRO_CACHE_VADDR_V 0x7FFFFFF 2861 #define DPORT_PRO_CACHE_VADDR_S 0 2862 2863 #define DPORT_PRO_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x3FC) 2864 /* DPORT_PRO_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ 2865 /*description: */ 2866 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15)) 2867 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_M (BIT(15)) 2868 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_V 0x1 2869 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15 2870 /* DPORT_PRO_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ 2871 /*description: */ 2872 #define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F 2873 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_M ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S)) 2874 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_V 0x3F 2875 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9 2876 /* This is the contents of DPORT_PRO_CPU_DISABLED_CACHE_IA field expanded */ 2877 /* The following bits will be set upon invalid access for different memory 2878 * regions: */ 2879 /* Port of the APP CPU cache when cache is used in high/low or odd/even mode */ 2880 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE BIT(9) 2881 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9) 2882 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1 2883 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9 2884 /* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */ 2885 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 BIT(10) 2886 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_M BIT(10) 2887 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_V 1 2888 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_S 10 2889 /* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ 2890 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0 BIT(11) 2891 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_M BIT(11) 2892 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_V 1 2893 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_S 11 2894 /* IRAM1: 0x4040_0000 ~ 0x407F_FFFF(RO) */ 2895 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1 BIT(12) 2896 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_M BIT(12) 2897 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_V 1 2898 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_S 12 2899 /* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ 2900 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0 BIT(13) 2901 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_M BIT(13) 2902 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_V 1 2903 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_S 13 2904 /* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */ 2905 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 BIT(14) 2906 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_M BIT(14) 2907 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_V 1 2908 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_S 14 2909 2910 /* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ 2911 /*description: */ 2912 #define DPORT_PRO_MMU_RDATA 0x000001FF 2913 #define DPORT_PRO_MMU_RDATA_M ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S)) 2914 #define DPORT_PRO_MMU_RDATA_V 0x1FF 2915 #define DPORT_PRO_MMU_RDATA_S 0 2916 2917 #define DPORT_PRO_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x400) 2918 /* DPORT_PRO_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2919 /*description: */ 2920 #define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF 2921 #define DPORT_PRO_DRAM1ADDR0_IA_M ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S)) 2922 #define DPORT_PRO_DRAM1ADDR0_IA_V 0xFFFFF 2923 #define DPORT_PRO_DRAM1ADDR0_IA_S 0 2924 2925 #define DPORT_PRO_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x404) 2926 /* DPORT_PRO_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2927 /*description: */ 2928 #define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF 2929 #define DPORT_PRO_DROM0ADDR0_IA_M ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S)) 2930 #define DPORT_PRO_DROM0ADDR0_IA_V 0xFFFFF 2931 #define DPORT_PRO_DROM0ADDR0_IA_S 0 2932 2933 #define DPORT_PRO_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x408) 2934 /* DPORT_PRO_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2935 /*description: */ 2936 #define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF 2937 #define DPORT_PRO_IRAM0ADDR_IA_M ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S)) 2938 #define DPORT_PRO_IRAM0ADDR_IA_V 0xFFFFF 2939 #define DPORT_PRO_IRAM0ADDR_IA_S 0 2940 2941 #define DPORT_PRO_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x40C) 2942 /* DPORT_PRO_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2943 /*description: */ 2944 #define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF 2945 #define DPORT_PRO_IRAM1ADDR_IA_M ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S)) 2946 #define DPORT_PRO_IRAM1ADDR_IA_V 0xFFFFF 2947 #define DPORT_PRO_IRAM1ADDR_IA_S 0 2948 2949 #define DPORT_PRO_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x410) 2950 /* DPORT_PRO_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2951 /*description: */ 2952 #define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF 2953 #define DPORT_PRO_IROM0ADDR_IA_M ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S)) 2954 #define DPORT_PRO_IROM0ADDR_IA_V 0xFFFFF 2955 #define DPORT_PRO_IROM0ADDR_IA_S 0 2956 2957 #define DPORT_PRO_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x414) 2958 /* DPORT_PRO_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 2959 /*description: */ 2960 #define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF 2961 #define DPORT_PRO_OPSDRAMADDR_IA_M ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S)) 2962 #define DPORT_PRO_OPSDRAMADDR_IA_V 0xFFFFF 2963 #define DPORT_PRO_OPSDRAMADDR_IA_S 0 2964 2965 #define DPORT_APP_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x418) 2966 /* DPORT_APP_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ 2967 /*description: */ 2968 #define DPORT_APP_RX_END (BIT(23)) 2969 #define DPORT_APP_RX_END_M (BIT(23)) 2970 #define DPORT_APP_RX_END_V 0x1 2971 #define DPORT_APP_RX_END_S 23 2972 /* DPORT_APP_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ 2973 /*description: */ 2974 #define DPORT_APP_SLAVE_WDATA_V (BIT(22)) 2975 #define DPORT_APP_SLAVE_WDATA_V_M (BIT(22)) 2976 #define DPORT_APP_SLAVE_WDATA_V_V 0x1 2977 #define DPORT_APP_SLAVE_WDATA_V_S 22 2978 /* DPORT_APP_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ 2979 /*description: */ 2980 #define DPORT_APP_SLAVE_WR (BIT(21)) 2981 #define DPORT_APP_SLAVE_WR_M (BIT(21)) 2982 #define DPORT_APP_SLAVE_WR_V 0x1 2983 #define DPORT_APP_SLAVE_WR_S 21 2984 /* DPORT_APP_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ 2985 /*description: */ 2986 #define DPORT_APP_TX_END (BIT(20)) 2987 #define DPORT_APP_TX_END_M (BIT(20)) 2988 #define DPORT_APP_TX_END_V 0x1 2989 #define DPORT_APP_TX_END_S 20 2990 /* DPORT_APP_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ 2991 /*description: */ 2992 #define DPORT_APP_WR_BAK_TO_READ (BIT(19)) 2993 #define DPORT_APP_WR_BAK_TO_READ_M (BIT(19)) 2994 #define DPORT_APP_WR_BAK_TO_READ_V 0x1 2995 #define DPORT_APP_WR_BAK_TO_READ_S 19 2996 /* DPORT_APP_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ 2997 /*description: */ 2998 #define DPORT_APP_CACHE_STATE 0x00000FFF 2999 #define DPORT_APP_CACHE_STATE_M ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S)) 3000 #define DPORT_APP_CACHE_STATE_V 0xFFF 3001 #define DPORT_APP_CACHE_STATE_S 7 3002 /* DPORT_APP_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ 3003 /*description: */ 3004 #define DPORT_APP_CACHE_IA 0x0000003F 3005 #define DPORT_APP_CACHE_IA_M ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S)) 3006 #define DPORT_APP_CACHE_IA_V 0x3F 3007 #define DPORT_APP_CACHE_IA_S 1 3008 /* DPORT_APP_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ 3009 /*description: */ 3010 #define DPORT_APP_CACHE_MMU_IA (BIT(0)) 3011 #define DPORT_APP_CACHE_MMU_IA_M (BIT(0)) 3012 #define DPORT_APP_CACHE_MMU_IA_V 0x1 3013 #define DPORT_APP_CACHE_MMU_IA_S 0 3014 3015 #define DPORT_APP_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x41C) 3016 /* DPORT_APP_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3017 /*description: */ 3018 #define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF 3019 #define DPORT_APP_CTAG_RAM_RDATA_M ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S)) 3020 #define DPORT_APP_CTAG_RAM_RDATA_V 0xFFFFFFFF 3021 #define DPORT_APP_CTAG_RAM_RDATA_S 0 3022 3023 #define DPORT_APP_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x420) 3024 /* DPORT_APP_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ 3025 /*description: */ 3026 #define DPORT_APP_CACHE_VADDR 0x07FFFFFF 3027 #define DPORT_APP_CACHE_VADDR_M ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S)) 3028 #define DPORT_APP_CACHE_VADDR_V 0x7FFFFFF 3029 #define DPORT_APP_CACHE_VADDR_S 0 3030 3031 #define DPORT_APP_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x424) 3032 /* DPORT_APP_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ 3033 /*description: */ 3034 #define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15)) 3035 #define DPORT_APP_CACHE_IRAM0_PID_ERROR_M (BIT(15)) 3036 #define DPORT_APP_CACHE_IRAM0_PID_ERROR_V 0x1 3037 #define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15 3038 /* DPORT_APP_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ 3039 /*description: */ 3040 #define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F 3041 #define DPORT_APP_CPU_DISABLED_CACHE_IA_M ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S)) 3042 #define DPORT_APP_CPU_DISABLED_CACHE_IA_V 0x3F 3043 #define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9 3044 /* This is the contents of DPORT_APP_CPU_DISABLED_CACHE_IA field expanded */ 3045 /* The following bits will be set upon invalid access for different memory 3046 * regions: */ 3047 /* Port of the PRO CPU cache when cache is used in high/low or odd/even mode */ 3048 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE BIT(9) 3049 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9) 3050 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1 3051 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9 3052 /* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */ 3053 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 BIT(10) 3054 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_M BIT(10) 3055 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_V 1 3056 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_S 10 3057 /* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ 3058 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0 BIT(11) 3059 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_M BIT(11) 3060 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_V 1 3061 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_S 11 3062 /* IRAM1: 0x4040_0000 ~ 0x407F_FFFF(RO) */ 3063 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1 BIT(12) 3064 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_M BIT(12) 3065 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_V 1 3066 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_S 12 3067 /* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */ 3068 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0 BIT(13) 3069 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_M BIT(13) 3070 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_V 1 3071 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_S 13 3072 /* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */ 3073 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0 BIT(14) 3074 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_M BIT(14) 3075 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_V 1 3076 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_S 14 3077 3078 /* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ 3079 /*description: */ 3080 #define DPORT_APP_MMU_RDATA 0x000001FF 3081 #define DPORT_APP_MMU_RDATA_M ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S)) 3082 #define DPORT_APP_MMU_RDATA_V 0x1FF 3083 #define DPORT_APP_MMU_RDATA_S 0 3084 3085 #define DPORT_APP_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x428) 3086 /* DPORT_APP_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3087 /*description: */ 3088 #define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF 3089 #define DPORT_APP_DRAM1ADDR0_IA_M ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S)) 3090 #define DPORT_APP_DRAM1ADDR0_IA_V 0xFFFFF 3091 #define DPORT_APP_DRAM1ADDR0_IA_S 0 3092 3093 #define DPORT_APP_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x42C) 3094 /* DPORT_APP_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3095 /*description: */ 3096 #define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF 3097 #define DPORT_APP_DROM0ADDR0_IA_M ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S)) 3098 #define DPORT_APP_DROM0ADDR0_IA_V 0xFFFFF 3099 #define DPORT_APP_DROM0ADDR0_IA_S 0 3100 3101 #define DPORT_APP_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x430) 3102 /* DPORT_APP_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3103 /*description: */ 3104 #define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF 3105 #define DPORT_APP_IRAM0ADDR_IA_M ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S)) 3106 #define DPORT_APP_IRAM0ADDR_IA_V 0xFFFFF 3107 #define DPORT_APP_IRAM0ADDR_IA_S 0 3108 3109 #define DPORT_APP_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x434) 3110 /* DPORT_APP_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3111 /*description: */ 3112 #define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF 3113 #define DPORT_APP_IRAM1ADDR_IA_M ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S)) 3114 #define DPORT_APP_IRAM1ADDR_IA_V 0xFFFFF 3115 #define DPORT_APP_IRAM1ADDR_IA_S 0 3116 3117 #define DPORT_APP_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x438) 3118 /* DPORT_APP_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3119 /*description: */ 3120 #define DPORT_APP_IROM0ADDR_IA 0x000FFFFF 3121 #define DPORT_APP_IROM0ADDR_IA_M ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S)) 3122 #define DPORT_APP_IROM0ADDR_IA_V 0xFFFFF 3123 #define DPORT_APP_IROM0ADDR_IA_S 0 3124 3125 #define DPORT_APP_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x43C) 3126 /* DPORT_APP_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ 3127 /*description: */ 3128 #define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF 3129 #define DPORT_APP_OPSDRAMADDR_IA_M ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S)) 3130 #define DPORT_APP_OPSDRAMADDR_IA_V 0xFFFFF 3131 #define DPORT_APP_OPSDRAMADDR_IA_S 0 3132 3133 #define DPORT_PRO_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x440) 3134 /* DPORT_PRO_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ 3135 /*description: */ 3136 #define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8)) 3137 #define DPORT_PRO_CPU_PDEBUG_ENABLE_M (BIT(8)) 3138 #define DPORT_PRO_CPU_PDEBUG_ENABLE_V 0x1 3139 #define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8 3140 /* DPORT_PRO_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 3141 /*description: */ 3142 #define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4)) 3143 #define DPORT_PRO_CPU_RECORD_DISABLE_M (BIT(4)) 3144 #define DPORT_PRO_CPU_RECORD_DISABLE_V 0x1 3145 #define DPORT_PRO_CPU_RECORD_DISABLE_S 4 3146 /* DPORT_PRO_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 3147 /*description: */ 3148 #define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0)) 3149 #define DPORT_PRO_CPU_RECORD_ENABLE_M (BIT(0)) 3150 #define DPORT_PRO_CPU_RECORD_ENABLE_V 0x1 3151 #define DPORT_PRO_CPU_RECORD_ENABLE_S 0 3152 3153 #define DPORT_PRO_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x444) 3154 /* DPORT_PRO_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ 3155 /*description: */ 3156 #define DPORT_PRO_CPU_RECORDING (BIT(0)) 3157 #define DPORT_PRO_CPU_RECORDING_M (BIT(0)) 3158 #define DPORT_PRO_CPU_RECORDING_V 0x1 3159 #define DPORT_PRO_CPU_RECORDING_S 0 3160 3161 #define DPORT_PRO_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x448) 3162 /* DPORT_RECORD_PRO_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ 3163 /*description: */ 3164 #define DPORT_RECORD_PRO_PID 0x00000007 3165 #define DPORT_RECORD_PRO_PID_M ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S)) 3166 #define DPORT_RECORD_PRO_PID_V 0x7 3167 #define DPORT_RECORD_PRO_PID_S 0 3168 3169 #define DPORT_PRO_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x44C) 3170 /* DPORT_RECORD_PRO_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3171 /*description: */ 3172 #define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF 3173 #define DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S)) 3174 #define DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF 3175 #define DPORT_RECORD_PRO_PDEBUGINST_S 0 3176 /* register layout: 3177 * SIZE [7..0] : Instructions normally complete in the W stage. The size of the instruction in the W is given 3178 * by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing 3179 * instruction. This is also known as a bubble cycle. Also see DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG. 3180 * ISRC [14..12] : Instruction source. 3181 ** LOOP [23..20] : Loopback status. 3182 ** CINTLEVEL [27..24]: CINTLEVEL. 3183 */ 3184 #define DPORT_RECORD_PDEBUGINST_SZ_M ((DPORT_RECORD_PDEBUGINST_SZ_V)<<(DPORT_RECORD_PDEBUGINST_SZ_S)) 3185 #define DPORT_RECORD_PDEBUGINST_SZ_V 0xFF 3186 #define DPORT_RECORD_PDEBUGINST_SZ_S 0 3187 #define DPORT_RECORD_PDEBUGINST_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V) 3188 #define DPORT_RECORD_PDEBUGINST_ISRC_M ((DPORT_RECORD_PDEBUGINST_ISRC_V)<<(DPORT_RECORD_PDEBUGINST_ISRC_S)) 3189 #define DPORT_RECORD_PDEBUGINST_ISRC_V 0x07 3190 #define DPORT_RECORD_PDEBUGINST_ISRC_S 12 3191 #define DPORT_RECORD_PDEBUGINST_ISRC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_ISRC_S) & DPORT_RECORD_PDEBUGINST_ISRC_V) 3192 // #define DPORT_RECORD_PDEBUGINST_LOOP_M ((DPORT_RECORD_PDEBUGINST_LOOP_V)<<(DPORT_RECORD_PDEBUGINST_LOOP_S)) 3193 // #define DPORT_RECORD_PDEBUGINST_LOOP_V 0x0F 3194 // #define DPORT_RECORD_PDEBUGINST_LOOP_S 20 3195 // #define DPORT_RECORD_PDEBUGINST_LOOP(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_LOOP_S) & DPORT_RECORD_PDEBUGINST_LOOP_V) 3196 #define DPORT_RECORD_PDEBUGINST_LOOP_REP (BIT(20)) /* loopback will occur */ 3197 #define DPORT_RECORD_PDEBUGINST_LOOP (BIT(21)) /* last inst of loop */ 3198 #define DPORT_RECORD_PDEBUGINST_CINTL_M ((DPORT_RECORD_PDEBUGINST_CINTL_V)<<(DPORT_RECORD_PDEBUGINST_CINTL_S)) 3199 #define DPORT_RECORD_PDEBUGINST_CINTL_V 0x0F 3200 #define DPORT_RECORD_PDEBUGINST_CINTL_S 24 3201 #define DPORT_RECORD_PDEBUGINST_CINTL(_r_) (((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V) 3202 3203 #define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450) 3204 /* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ 3205 /*description: */ 3206 #define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF 3207 #define DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S)) 3208 #define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF 3209 #define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0 3210 /* register layout: 3211 * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0 3212 * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0 3213 */ 3214 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S)) 3215 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V 0x3F 3216 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S 0 3217 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S) & DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V) 3218 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO 0x00 /* Power shut off */ 3219 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP 0x02 /* Register dependency or resource conflict. See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */ 3220 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL 0x04 /* Control transfer bubble */ 3221 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM 0x08 /* I-cache miss (incl uncached miss) */ 3222 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM 0x0C /* D-cache miss (excl uncached miss) */ 3223 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0 0x10 /* Exception or interrupt (W stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. 3224 The virtual address of the instruction that was killed appears on DPORT_PRO_CPU_RECORD_PDEBUGPC_REG[31:0] */ 3225 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1 0x11 /* Exception or interrupt (W+1 stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */ 3226 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL 0x14 /* Instruction replay (other). DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG has the PC of the replaying instruction. */ 3227 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB 0x18 /* HW ITLB refill. The refill address and data are available on 3228 DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */ 3229 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM 0x1A /* ITLB miss */ 3230 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB 0x1C /* HW DTLB refill. The refill address and data are available on 3231 DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */ 3232 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM 0x1E /* DTLB miss */ 3233 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL 0x20 /* Stall . The cause of the global stall is further classified in the DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG. */ 3234 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC 0x24 /* HW-corrected memory error */ 3235 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI 0x28 /* WAITI mode */ 3236 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER 0x3C /* all other bubbles */ 3237 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_M ((DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)<<(DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S)) 3238 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V 0x3F 3239 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S 0 3240 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S) & DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V) 3241 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX 0x00 /* JX */ 3242 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX 0x04 /* CALLX */ 3243 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET 0x08 /* All call returns */ 3244 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET 0x0C /* All exception returns */ 3245 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B 0x10 /* Branch taken or loop not taken */ 3246 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J 0x14 /* J */ 3247 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL 0x18 /* CALL */ 3248 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN 0x1C /* Branch not taken */ 3249 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP 0x20 /* Loop instruction (taken) */ 3250 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I 0x24 /* S32C1I. The address and load data (before the conditional store) are available on the LS signals*/ 3251 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB 0x28 /* WSR/XSR to LBEGIN */ 3252 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID 0x2C /* WSR to MMID */ 3253 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR 0x30 /* RSR or WSR (except MMID and LBEGIN) or XSR (except LBEGIN) */ 3254 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER 0x34 /* RER or WER */ 3255 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF 0x3C /* Default */ 3256 3257 #define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454) 3258 /* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3259 /*description: */ 3260 #define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF 3261 #define DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S)) 3262 #define DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF 3263 #define DPORT_RECORD_PRO_PDEBUGDATA_S 0 3264 /* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP: 3265 * 3266 * HALT [17]: HALT instruction (TX only) 3267 * MEMW [16]: MEMW, EXTW or EXCW instruction dependency 3268 * REG [12]: register dependencies or resource (e.g.TIE ports) conflicts 3269 * STR [11]: store release (instruction) dependency 3270 * LSU [8] : various LSU dependencies (MHT access, prefetch, cache access insts, s32c1i, etc) 3271 * OTHER[0] : all other hold dependencies resulting from data or resource dependencies 3272 */ 3273 #define DPORT_RECORD_PDEBUGDATA_DEP_HALT (BIT(17)) 3274 #define DPORT_RECORD_PDEBUGDATA_DEP_MEMW (BIT(16)) 3275 #define DPORT_RECORD_PDEBUGDATA_DEP_REG (BIT(12)) 3276 #define DPORT_RECORD_PDEBUGDATA_DEP_STR (BIT(11)) 3277 #define DPORT_RECORD_PDEBUGDATA_DEP_LSU (BIT(8)) 3278 #define DPORT_RECORD_PDEBUGDATA_DEP_OTHER (BIT(0)) 3279 /* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXCn: 3280 * 3281 * EXCCAUSE[21..16]: Processor exception cause 3282 * EXCVEC [4..0] : Encoded Exception Vector 3283 */ 3284 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_M ((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S)) 3285 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V 0x3F 3286 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S 16 3287 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V) 3288 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_M ((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S)) 3289 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_V 0x1F 3290 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_S 0 3291 #define DPORT_RECORD_PDEBUGDATA_EXCVEC(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V) 3292 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_NONE 0x00 /* no vector */ 3293 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_RST 0x01 /* Reset */ 3294 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBG 0x02 /* Debug (repl corresp level “n”) */ 3295 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_NMI 0x03 /* NMI (repl corresp level “n”) */ 3296 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_USR 0x04 /* User */ 3297 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_KRNL 0x05 /* Kernel */ 3298 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBL 0x06 /* Double */ 3299 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_EMEM 0x07 /* Memory Error */ 3300 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF4 0x0A /* Window Overflow 4 */ 3301 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF4 0x0B /* Window Underflow 4 */ 3302 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF8 0x0C /* Window Overflow 8 */ 3303 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF8 0x0D /* Window Underflow 8 */ 3304 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF12 0x0E /* Window Overflow 12 */ 3305 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF12 0x0F /* Window Underflow 12 */ 3306 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT2 0x10 /* Int Level 2 (n/a if debug/NMI) */ 3307 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT3 0x11 /* Int Level 3 (n/a if debug/NMI) */ 3308 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT4 0x12 /* Int Level 4 (n/a if debug/NMI) */ 3309 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT5 0x13 /* Int Level 5 (n/a if debug/NMI) */ 3310 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT6 0x14 /* Int Level 6 (n/a if debug/NMI) */ 3311 /* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL: 3312 * 3313 * ITERDIV[19] : Iterative divide stall. 3314 * ITERMUL[18] : Iterative multiply stall. 3315 * BANKCONFL[16]: Bank-conflict stall. 3316 * BPLOAD[15] : Bypass load stall. 3317 * LSPROC[14] : Load/store miss-processing stall. 3318 * L32R[13] : FastL32R stall. 3319 * BPIFETCH[12] : Bypass I fetch stall. 3320 * RUNSTALL[10] : RunStall. 3321 * TIE[9] : TIE port stall. 3322 * IPIF[8] : Instruction RAM inbound-PIF stall. 3323 * IRAMBUSY[7] : Instruction RAM/ROM busy stall. 3324 * ICM[6] : I-cache-miss stall. 3325 * LSU[4] : The LSU will stall the pipeline under various local memory access conflict situations. 3326 * DCM[3] : D-cache-miss stall. 3327 * BUFFCONFL[2] : Store buffer conflict stall. 3328 * BUFF[1] : Store buffer full stall. 3329 */ 3330 #define DPORT_RECORD_PDEBUGDATA_STALL_ITERDIV (BIT(19)) 3331 #define DPORT_RECORD_PDEBUGDATA_STALL_ITERMUL (BIT(18)) 3332 #define DPORT_RECORD_PDEBUGDATA_STALL_BANKCONFL (BIT(16)) 3333 #define DPORT_RECORD_PDEBUGDATA_STALL_BPLOAD (BIT(15)) 3334 #define DPORT_RECORD_PDEBUGDATA_STALL_LSPROC (BIT(14)) 3335 #define DPORT_RECORD_PDEBUGDATA_STALL_L32R (BIT(13)) 3336 #define DPORT_RECORD_PDEBUGDATA_STALL_BPIFETCH (BIT(12)) 3337 #define DPORT_RECORD_PDEBUGDATA_STALL_RUN (BIT(10)) 3338 #define DPORT_RECORD_PDEBUGDATA_STALL_TIE (BIT(9)) 3339 #define DPORT_RECORD_PDEBUGDATA_STALL_IPIF (BIT(8)) 3340 #define DPORT_RECORD_PDEBUGDATA_STALL_IRAMBUSY (BIT(7)) 3341 #define DPORT_RECORD_PDEBUGDATA_STALL_ICM (BIT(6)) 3342 #define DPORT_RECORD_PDEBUGDATA_STALL_LSU (BIT(4)) 3343 #define DPORT_RECORD_PDEBUGDATA_STALL_DCM (BIT(3)) 3344 #define DPORT_RECORD_PDEBUGDATA_STALL_BUFFCONFL (BIT(2)) 3345 #define DPORT_RECORD_PDEBUGDATA_STALL_BUFF (BIT(1)) 3346 /* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR: 3347 * 3348 * XSR[10] : XSR Instruction 3349 * WSR[9] : WSR Instruction 3350 * RSR[8] : RSR Instruction 3351 * SR[7..0] : Special Register Number 3352 */ 3353 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_XSR (BIT(10)) 3354 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WSR (BIT(9)) 3355 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RSR (BIT(8)) 3356 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_M ((DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S)) 3357 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V 0xFF 3358 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S 0 3359 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V) 3360 /* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER: 3361 * 3362 * ER[13..2]: ER Address 3363 * WER[1] : WER Instruction 3364 * RER[0] : RER Instruction 3365 */ 3366 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_M ((DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S)) 3367 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V 0xFFF 3368 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S 2 3369 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER(_r_) (((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V) 3370 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WER (BIT(1)) 3371 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RER (BIT(0)) 3372 3373 3374 #define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458) 3375 /* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3376 /*description: */ 3377 #define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF 3378 #define DPORT_RECORD_PRO_PDEBUGPC_M ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S)) 3379 #define DPORT_RECORD_PRO_PDEBUGPC_V 0xFFFFFFFF 3380 #define DPORT_RECORD_PRO_PDEBUGPC_S 0 3381 3382 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x45C) 3383 /* DPORT_RECORD_PRO_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3384 /*description: */ 3385 #define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF 3386 #define DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S)) 3387 #define DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF 3388 #define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0 3389 /* register layout: 3390 * TYPE [3..0] : Type of instruction in LS. 3391 * SZ [7..4] : Operand size. 3392 * DTLBM [8] : Data TLB miss. 3393 * DCM [9] : D-cache miss. 3394 * DCH [10] : D-cache hit. 3395 * UC [12] : Uncached. 3396 * WB [13] : Writeback. 3397 * COH [16] : Coherency. 3398 * STCOH [18..17]: Coherent state. 3399 * TGT [23..20] : Local target. 3400 */ 3401 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_M ((DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TYPE_S)) 3402 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_V 0x0F 3403 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S 0 3404 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TYPE_S) & DPORT_RECORD_PDEBUGLS0STAT_TYPE_V) 3405 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_NONE 0x00 /* neither */ 3406 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_ITLBR 0x01 /* hw itlb refill */ 3407 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_DTLBR 0x02 /* hw dtlb refill */ 3408 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_LD 0x05 /* load */ 3409 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_STR 0x06 /* store */ 3410 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_L32R 0x08 /* l32r */ 3411 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S32CLI1 0x0A /* s32ci1 */ 3412 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_CTI 0x0C /* cache test inst */ 3413 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWXSR 0x0E /* rsr/wsr/xsr */ 3414 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWER 0x0F /* rer/wer */ 3415 #define DPORT_RECORD_PDEBUGLS0STAT_SZ_M ((DPORT_RECORD_PDEBUGLS0STAT_SZ_V)<<(DPORT_RECORD_PDEBUGLS0STAT_SZ_S)) 3416 #define DPORT_RECORD_PDEBUGLS0STAT_SZ_V 0x0F 3417 #define DPORT_RECORD_PDEBUGLS0STAT_SZ_S 4 3418 #define DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_SZ_S) & DPORT_RECORD_PDEBUGLS0STAT_SZ_V) 3419 #define DPORT_RECORD_PDEBUGLS0STAT_SZB(_r_) ((8<<DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_))/8) // in bytes 3420 #define DPORT_RECORD_PDEBUGLS0STAT_DTLBM (BIT(8)) 3421 #define DPORT_RECORD_PDEBUGLS0STAT_DCM (BIT(9)) 3422 #define DPORT_RECORD_PDEBUGLS0STAT_DCH (BIT(10)) 3423 #define DPORT_RECORD_PDEBUGLS0STAT_UC (BIT(12)) 3424 #define DPORT_RECORD_PDEBUGLS0STAT_WB (BIT(13)) 3425 #define DPORT_RECORD_PDEBUGLS0STAT_COH (BIT(16)) 3426 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_M ((DPORT_RECORD_PDEBUGLS0STAT_STCOH_V)<<(DPORT_RECORD_PDEBUGLS0STAT_STCOH_S)) 3427 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_V 0x03 3428 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_S 17 3429 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_STCOH_S) & DPORT_RECORD_PDEBUGLS0STAT_STCOH_V) 3430 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_NONE 0x0 /* neither shared nor exclusive nor modified */ 3431 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_SHARED 0x1 /* shared */ 3432 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_EXCL 0x2 /* exclusive */ 3433 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_MOD 0x3 /* modified */ 3434 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_M ((DPORT_RECORD_PDEBUGLS0STAT_TGT_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TGT_S)) 3435 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_V 0x0F 3436 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_S 20 3437 #define DPORT_RECORD_PDEBUGLS0STAT_TGT(_r_) (((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TGT_S) & DPORT_RECORD_PDEBUGLS0STAT_TGT_V) 3438 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_EXT 0x0 /* not to local memory */ 3439 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM0 0x2 /* 001x: InstRAM (0/1) */ 3440 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM1 0x3 /* 001x: InstRAM (0/1) */ 3441 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM0 0x4 /* 010x: InstROM (0/1) */ 3442 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM1 0x5 /* 010x: InstROM (0/1) */ 3443 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM0 0x0A /* 101x: DataRAM (0/1) */ 3444 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM1 0x0B /* 101x: DataRAM (0/1) */ 3445 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM0 0xE /* 111x: DataROM (0/1) */ 3446 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM1 0xF /* 111x: DataROM (0/1) */ 3447 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM(_t_) (((_t_)&0xE)=0x2) /* 001x: InstRAM (0/1) */ 3448 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM(_t_) (((_t_)&0xE)=0x4) /* 010x: InstROM (0/1) */ 3449 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM(_t_) (((_t_)&0xE)=0x2) /* 101x: DataRAM (0/1) */ 3450 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM(_t_) (((_t_)&0xE)=0x2) /* 111x: DataROM (0/1) */ 3451 3452 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460) 3453 /* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3454 /*description: */ 3455 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF 3456 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_M ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S)) 3457 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_V 0xFFFFFFFF 3458 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0 3459 3460 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x464) 3461 /* DPORT_RECORD_PRO_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3462 /*description: */ 3463 #define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF 3464 #define DPORT_RECORD_PRO_PDEBUGLS0DATA_M ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S)) 3465 #define DPORT_RECORD_PRO_PDEBUGLS0DATA_V 0xFFFFFFFF 3466 #define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0 3467 3468 #define DPORT_APP_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x468) 3469 /* DPORT_APP_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ 3470 /*description: */ 3471 #define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8)) 3472 #define DPORT_APP_CPU_PDEBUG_ENABLE_M (BIT(8)) 3473 #define DPORT_APP_CPU_PDEBUG_ENABLE_V 0x1 3474 #define DPORT_APP_CPU_PDEBUG_ENABLE_S 8 3475 /* DPORT_APP_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 3476 /*description: */ 3477 #define DPORT_APP_CPU_RECORD_DISABLE (BIT(4)) 3478 #define DPORT_APP_CPU_RECORD_DISABLE_M (BIT(4)) 3479 #define DPORT_APP_CPU_RECORD_DISABLE_V 0x1 3480 #define DPORT_APP_CPU_RECORD_DISABLE_S 4 3481 /* DPORT_APP_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 3482 /*description: */ 3483 #define DPORT_APP_CPU_RECORD_ENABLE (BIT(0)) 3484 #define DPORT_APP_CPU_RECORD_ENABLE_M (BIT(0)) 3485 #define DPORT_APP_CPU_RECORD_ENABLE_V 0x1 3486 #define DPORT_APP_CPU_RECORD_ENABLE_S 0 3487 3488 #define DPORT_APP_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x46C) 3489 /* DPORT_APP_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ 3490 /*description: */ 3491 #define DPORT_APP_CPU_RECORDING (BIT(0)) 3492 #define DPORT_APP_CPU_RECORDING_M (BIT(0)) 3493 #define DPORT_APP_CPU_RECORDING_V 0x1 3494 #define DPORT_APP_CPU_RECORDING_S 0 3495 3496 #define DPORT_APP_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x470) 3497 /* DPORT_RECORD_APP_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ 3498 /*description: */ 3499 #define DPORT_RECORD_APP_PID 0x00000007 3500 #define DPORT_RECORD_APP_PID_M ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S)) 3501 #define DPORT_RECORD_APP_PID_V 0x7 3502 #define DPORT_RECORD_APP_PID_S 0 3503 3504 #define DPORT_APP_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x474) 3505 /* DPORT_RECORD_APP_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3506 /*description: */ 3507 #define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF 3508 #define DPORT_RECORD_APP_PDEBUGINST_M ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S)) 3509 #define DPORT_RECORD_APP_PDEBUGINST_V 0xFFFFFFFF 3510 #define DPORT_RECORD_APP_PDEBUGINST_S 0 3511 3512 #define DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x478) 3513 /* DPORT_RECORD_APP_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ 3514 /*description: */ 3515 #define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF 3516 #define DPORT_RECORD_APP_PDEBUGSTATUS_M ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S)) 3517 #define DPORT_RECORD_APP_PDEBUGSTATUS_V 0xFF 3518 #define DPORT_RECORD_APP_PDEBUGSTATUS_S 0 3519 3520 #define DPORT_APP_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x47C) 3521 /* DPORT_RECORD_APP_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3522 /*description: */ 3523 #define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF 3524 #define DPORT_RECORD_APP_PDEBUGDATA_M ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S)) 3525 #define DPORT_RECORD_APP_PDEBUGDATA_V 0xFFFFFFFF 3526 #define DPORT_RECORD_APP_PDEBUGDATA_S 0 3527 3528 #define DPORT_APP_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x480) 3529 /* DPORT_RECORD_APP_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3530 /*description: */ 3531 #define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF 3532 #define DPORT_RECORD_APP_PDEBUGPC_M ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S)) 3533 #define DPORT_RECORD_APP_PDEBUGPC_V 0xFFFFFFFF 3534 #define DPORT_RECORD_APP_PDEBUGPC_S 0 3535 3536 #define DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x484) 3537 /* DPORT_RECORD_APP_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3538 /*description: */ 3539 #define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF 3540 #define DPORT_RECORD_APP_PDEBUGLS0STAT_M ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S)) 3541 #define DPORT_RECORD_APP_PDEBUGLS0STAT_V 0xFFFFFFFF 3542 #define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0 3543 3544 #define DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x488) 3545 /* DPORT_RECORD_APP_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3546 /*description: */ 3547 #define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF 3548 #define DPORT_RECORD_APP_PDEBUGLS0ADDR_M ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S)) 3549 #define DPORT_RECORD_APP_PDEBUGLS0ADDR_V 0xFFFFFFFF 3550 #define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0 3551 3552 #define DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x48C) 3553 /* DPORT_RECORD_APP_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 3554 /*description: */ 3555 #define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF 3556 #define DPORT_RECORD_APP_PDEBUGLS0DATA_M ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S)) 3557 #define DPORT_RECORD_APP_PDEBUGLS0DATA_V 0xFFFFFFFF 3558 #define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0 3559 3560 #define DPORT_RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490) 3561 /* DPORT_RSA_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ 3562 /*description: */ 3563 #define DPORT_RSA_PD (BIT(0)) 3564 #define DPORT_RSA_PD_M (BIT(0)) 3565 #define DPORT_RSA_PD_V 0x1 3566 #define DPORT_RSA_PD_S 0 3567 3568 #define DPORT_ROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x494) 3569 /* DPORT_ROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3570 /*description: */ 3571 #define DPORT_ROM_MPU_TABLE0 0x00000003 3572 #define DPORT_ROM_MPU_TABLE0_M ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S)) 3573 #define DPORT_ROM_MPU_TABLE0_V 0x3 3574 #define DPORT_ROM_MPU_TABLE0_S 0 3575 3576 #define DPORT_ROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x498) 3577 /* DPORT_ROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3578 /*description: */ 3579 #define DPORT_ROM_MPU_TABLE1 0x00000003 3580 #define DPORT_ROM_MPU_TABLE1_M ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S)) 3581 #define DPORT_ROM_MPU_TABLE1_V 0x3 3582 #define DPORT_ROM_MPU_TABLE1_S 0 3583 3584 #define DPORT_ROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x49C) 3585 /* DPORT_ROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3586 /*description: */ 3587 #define DPORT_ROM_MPU_TABLE2 0x00000003 3588 #define DPORT_ROM_MPU_TABLE2_M ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S)) 3589 #define DPORT_ROM_MPU_TABLE2_V 0x3 3590 #define DPORT_ROM_MPU_TABLE2_S 0 3591 3592 #define DPORT_ROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4A0) 3593 /* DPORT_ROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3594 /*description: */ 3595 #define DPORT_ROM_MPU_TABLE3 0x00000003 3596 #define DPORT_ROM_MPU_TABLE3_M ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S)) 3597 #define DPORT_ROM_MPU_TABLE3_V 0x3 3598 #define DPORT_ROM_MPU_TABLE3_S 0 3599 3600 #define DPORT_SHROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x4A4) 3601 /* DPORT_SHROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3602 /*description: */ 3603 #define DPORT_SHROM_MPU_TABLE0 0x00000003 3604 #define DPORT_SHROM_MPU_TABLE0_M ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S)) 3605 #define DPORT_SHROM_MPU_TABLE0_V 0x3 3606 #define DPORT_SHROM_MPU_TABLE0_S 0 3607 3608 #define DPORT_SHROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x4A8) 3609 /* DPORT_SHROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3610 /*description: */ 3611 #define DPORT_SHROM_MPU_TABLE1 0x00000003 3612 #define DPORT_SHROM_MPU_TABLE1_M ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S)) 3613 #define DPORT_SHROM_MPU_TABLE1_V 0x3 3614 #define DPORT_SHROM_MPU_TABLE1_S 0 3615 3616 #define DPORT_SHROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x4AC) 3617 /* DPORT_SHROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3618 /*description: */ 3619 #define DPORT_SHROM_MPU_TABLE2 0x00000003 3620 #define DPORT_SHROM_MPU_TABLE2_M ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S)) 3621 #define DPORT_SHROM_MPU_TABLE2_V 0x3 3622 #define DPORT_SHROM_MPU_TABLE2_S 0 3623 3624 #define DPORT_SHROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4B0) 3625 /* DPORT_SHROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3626 /*description: */ 3627 #define DPORT_SHROM_MPU_TABLE3 0x00000003 3628 #define DPORT_SHROM_MPU_TABLE3_M ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S)) 3629 #define DPORT_SHROM_MPU_TABLE3_V 0x3 3630 #define DPORT_SHROM_MPU_TABLE3_S 0 3631 3632 #define DPORT_SHROM_MPU_TABLE4_REG (DR_REG_DPORT_BASE + 0x4B4) 3633 /* DPORT_SHROM_MPU_TABLE4 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3634 /*description: */ 3635 #define DPORT_SHROM_MPU_TABLE4 0x00000003 3636 #define DPORT_SHROM_MPU_TABLE4_M ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S)) 3637 #define DPORT_SHROM_MPU_TABLE4_V 0x3 3638 #define DPORT_SHROM_MPU_TABLE4_S 0 3639 3640 #define DPORT_SHROM_MPU_TABLE5_REG (DR_REG_DPORT_BASE + 0x4B8) 3641 /* DPORT_SHROM_MPU_TABLE5 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3642 /*description: */ 3643 #define DPORT_SHROM_MPU_TABLE5 0x00000003 3644 #define DPORT_SHROM_MPU_TABLE5_M ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S)) 3645 #define DPORT_SHROM_MPU_TABLE5_V 0x3 3646 #define DPORT_SHROM_MPU_TABLE5_S 0 3647 3648 #define DPORT_SHROM_MPU_TABLE6_REG (DR_REG_DPORT_BASE + 0x4BC) 3649 /* DPORT_SHROM_MPU_TABLE6 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3650 /*description: */ 3651 #define DPORT_SHROM_MPU_TABLE6 0x00000003 3652 #define DPORT_SHROM_MPU_TABLE6_M ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S)) 3653 #define DPORT_SHROM_MPU_TABLE6_V 0x3 3654 #define DPORT_SHROM_MPU_TABLE6_S 0 3655 3656 #define DPORT_SHROM_MPU_TABLE7_REG (DR_REG_DPORT_BASE + 0x4C0) 3657 /* DPORT_SHROM_MPU_TABLE7 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3658 /*description: */ 3659 #define DPORT_SHROM_MPU_TABLE7 0x00000003 3660 #define DPORT_SHROM_MPU_TABLE7_M ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S)) 3661 #define DPORT_SHROM_MPU_TABLE7_V 0x3 3662 #define DPORT_SHROM_MPU_TABLE7_S 0 3663 3664 #define DPORT_SHROM_MPU_TABLE8_REG (DR_REG_DPORT_BASE + 0x4C4) 3665 /* DPORT_SHROM_MPU_TABLE8 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3666 /*description: */ 3667 #define DPORT_SHROM_MPU_TABLE8 0x00000003 3668 #define DPORT_SHROM_MPU_TABLE8_M ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S)) 3669 #define DPORT_SHROM_MPU_TABLE8_V 0x3 3670 #define DPORT_SHROM_MPU_TABLE8_S 0 3671 3672 #define DPORT_SHROM_MPU_TABLE9_REG (DR_REG_DPORT_BASE + 0x4C8) 3673 /* DPORT_SHROM_MPU_TABLE9 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3674 /*description: */ 3675 #define DPORT_SHROM_MPU_TABLE9 0x00000003 3676 #define DPORT_SHROM_MPU_TABLE9_M ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S)) 3677 #define DPORT_SHROM_MPU_TABLE9_V 0x3 3678 #define DPORT_SHROM_MPU_TABLE9_S 0 3679 3680 #define DPORT_SHROM_MPU_TABLE10_REG (DR_REG_DPORT_BASE + 0x4CC) 3681 /* DPORT_SHROM_MPU_TABLE10 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3682 /*description: */ 3683 #define DPORT_SHROM_MPU_TABLE10 0x00000003 3684 #define DPORT_SHROM_MPU_TABLE10_M ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S)) 3685 #define DPORT_SHROM_MPU_TABLE10_V 0x3 3686 #define DPORT_SHROM_MPU_TABLE10_S 0 3687 3688 #define DPORT_SHROM_MPU_TABLE11_REG (DR_REG_DPORT_BASE + 0x4D0) 3689 /* DPORT_SHROM_MPU_TABLE11 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3690 /*description: */ 3691 #define DPORT_SHROM_MPU_TABLE11 0x00000003 3692 #define DPORT_SHROM_MPU_TABLE11_M ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S)) 3693 #define DPORT_SHROM_MPU_TABLE11_V 0x3 3694 #define DPORT_SHROM_MPU_TABLE11_S 0 3695 3696 #define DPORT_SHROM_MPU_TABLE12_REG (DR_REG_DPORT_BASE + 0x4D4) 3697 /* DPORT_SHROM_MPU_TABLE12 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3698 /*description: */ 3699 #define DPORT_SHROM_MPU_TABLE12 0x00000003 3700 #define DPORT_SHROM_MPU_TABLE12_M ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S)) 3701 #define DPORT_SHROM_MPU_TABLE12_V 0x3 3702 #define DPORT_SHROM_MPU_TABLE12_S 0 3703 3704 #define DPORT_SHROM_MPU_TABLE13_REG (DR_REG_DPORT_BASE + 0x4D8) 3705 /* DPORT_SHROM_MPU_TABLE13 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3706 /*description: */ 3707 #define DPORT_SHROM_MPU_TABLE13 0x00000003 3708 #define DPORT_SHROM_MPU_TABLE13_M ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S)) 3709 #define DPORT_SHROM_MPU_TABLE13_V 0x3 3710 #define DPORT_SHROM_MPU_TABLE13_S 0 3711 3712 #define DPORT_SHROM_MPU_TABLE14_REG (DR_REG_DPORT_BASE + 0x4DC) 3713 /* DPORT_SHROM_MPU_TABLE14 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3714 /*description: */ 3715 #define DPORT_SHROM_MPU_TABLE14 0x00000003 3716 #define DPORT_SHROM_MPU_TABLE14_M ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S)) 3717 #define DPORT_SHROM_MPU_TABLE14_V 0x3 3718 #define DPORT_SHROM_MPU_TABLE14_S 0 3719 3720 #define DPORT_SHROM_MPU_TABLE15_REG (DR_REG_DPORT_BASE + 0x4E0) 3721 /* DPORT_SHROM_MPU_TABLE15 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3722 /*description: */ 3723 #define DPORT_SHROM_MPU_TABLE15 0x00000003 3724 #define DPORT_SHROM_MPU_TABLE15_M ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S)) 3725 #define DPORT_SHROM_MPU_TABLE15_V 0x3 3726 #define DPORT_SHROM_MPU_TABLE15_S 0 3727 3728 #define DPORT_SHROM_MPU_TABLE16_REG (DR_REG_DPORT_BASE + 0x4E4) 3729 /* DPORT_SHROM_MPU_TABLE16 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3730 /*description: */ 3731 #define DPORT_SHROM_MPU_TABLE16 0x00000003 3732 #define DPORT_SHROM_MPU_TABLE16_M ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S)) 3733 #define DPORT_SHROM_MPU_TABLE16_V 0x3 3734 #define DPORT_SHROM_MPU_TABLE16_S 0 3735 3736 #define DPORT_SHROM_MPU_TABLE17_REG (DR_REG_DPORT_BASE + 0x4E8) 3737 /* DPORT_SHROM_MPU_TABLE17 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3738 /*description: */ 3739 #define DPORT_SHROM_MPU_TABLE17 0x00000003 3740 #define DPORT_SHROM_MPU_TABLE17_M ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S)) 3741 #define DPORT_SHROM_MPU_TABLE17_V 0x3 3742 #define DPORT_SHROM_MPU_TABLE17_S 0 3743 3744 #define DPORT_SHROM_MPU_TABLE18_REG (DR_REG_DPORT_BASE + 0x4EC) 3745 /* DPORT_SHROM_MPU_TABLE18 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3746 /*description: */ 3747 #define DPORT_SHROM_MPU_TABLE18 0x00000003 3748 #define DPORT_SHROM_MPU_TABLE18_M ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S)) 3749 #define DPORT_SHROM_MPU_TABLE18_V 0x3 3750 #define DPORT_SHROM_MPU_TABLE18_S 0 3751 3752 #define DPORT_SHROM_MPU_TABLE19_REG (DR_REG_DPORT_BASE + 0x4F0) 3753 /* DPORT_SHROM_MPU_TABLE19 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3754 /*description: */ 3755 #define DPORT_SHROM_MPU_TABLE19 0x00000003 3756 #define DPORT_SHROM_MPU_TABLE19_M ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S)) 3757 #define DPORT_SHROM_MPU_TABLE19_V 0x3 3758 #define DPORT_SHROM_MPU_TABLE19_S 0 3759 3760 #define DPORT_SHROM_MPU_TABLE20_REG (DR_REG_DPORT_BASE + 0x4F4) 3761 /* DPORT_SHROM_MPU_TABLE20 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3762 /*description: */ 3763 #define DPORT_SHROM_MPU_TABLE20 0x00000003 3764 #define DPORT_SHROM_MPU_TABLE20_M ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S)) 3765 #define DPORT_SHROM_MPU_TABLE20_V 0x3 3766 #define DPORT_SHROM_MPU_TABLE20_S 0 3767 3768 #define DPORT_SHROM_MPU_TABLE21_REG (DR_REG_DPORT_BASE + 0x4F8) 3769 /* DPORT_SHROM_MPU_TABLE21 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3770 /*description: */ 3771 #define DPORT_SHROM_MPU_TABLE21 0x00000003 3772 #define DPORT_SHROM_MPU_TABLE21_M ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S)) 3773 #define DPORT_SHROM_MPU_TABLE21_V 0x3 3774 #define DPORT_SHROM_MPU_TABLE21_S 0 3775 3776 #define DPORT_SHROM_MPU_TABLE22_REG (DR_REG_DPORT_BASE + 0x4FC) 3777 /* DPORT_SHROM_MPU_TABLE22 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3778 /*description: */ 3779 #define DPORT_SHROM_MPU_TABLE22 0x00000003 3780 #define DPORT_SHROM_MPU_TABLE22_M ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S)) 3781 #define DPORT_SHROM_MPU_TABLE22_V 0x3 3782 #define DPORT_SHROM_MPU_TABLE22_S 0 3783 3784 #define DPORT_SHROM_MPU_TABLE23_REG (DR_REG_DPORT_BASE + 0x500) 3785 /* DPORT_SHROM_MPU_TABLE23 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ 3786 /*description: */ 3787 #define DPORT_SHROM_MPU_TABLE23 0x00000003 3788 #define DPORT_SHROM_MPU_TABLE23_M ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S)) 3789 #define DPORT_SHROM_MPU_TABLE23_V 0x3 3790 #define DPORT_SHROM_MPU_TABLE23_S 0 3791 3792 #define DPORT_IMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x504) 3793 /* DPORT_IMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ 3794 /*description: */ 3795 #define DPORT_IMMU_TABLE0 0x0000007F 3796 #define DPORT_IMMU_TABLE0_M ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S)) 3797 #define DPORT_IMMU_TABLE0_V 0x7F 3798 #define DPORT_IMMU_TABLE0_S 0 3799 3800 #define DPORT_IMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x508) 3801 /* DPORT_IMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ 3802 /*description: */ 3803 #define DPORT_IMMU_TABLE1 0x0000007F 3804 #define DPORT_IMMU_TABLE1_M ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S)) 3805 #define DPORT_IMMU_TABLE1_V 0x7F 3806 #define DPORT_IMMU_TABLE1_S 0 3807 3808 #define DPORT_IMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x50C) 3809 /* DPORT_IMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ 3810 /*description: */ 3811 #define DPORT_IMMU_TABLE2 0x0000007F 3812 #define DPORT_IMMU_TABLE2_M ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S)) 3813 #define DPORT_IMMU_TABLE2_V 0x7F 3814 #define DPORT_IMMU_TABLE2_S 0 3815 3816 #define DPORT_IMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x510) 3817 /* DPORT_IMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ 3818 /*description: */ 3819 #define DPORT_IMMU_TABLE3 0x0000007F 3820 #define DPORT_IMMU_TABLE3_M ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S)) 3821 #define DPORT_IMMU_TABLE3_V 0x7F 3822 #define DPORT_IMMU_TABLE3_S 0 3823 3824 #define DPORT_IMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x514) 3825 /* DPORT_IMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ 3826 /*description: */ 3827 #define DPORT_IMMU_TABLE4 0x0000007F 3828 #define DPORT_IMMU_TABLE4_M ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S)) 3829 #define DPORT_IMMU_TABLE4_V 0x7F 3830 #define DPORT_IMMU_TABLE4_S 0 3831 3832 #define DPORT_IMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x518) 3833 /* DPORT_IMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ 3834 /*description: */ 3835 #define DPORT_IMMU_TABLE5 0x0000007F 3836 #define DPORT_IMMU_TABLE5_M ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S)) 3837 #define DPORT_IMMU_TABLE5_V 0x7F 3838 #define DPORT_IMMU_TABLE5_S 0 3839 3840 #define DPORT_IMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x51C) 3841 /* DPORT_IMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ 3842 /*description: */ 3843 #define DPORT_IMMU_TABLE6 0x0000007F 3844 #define DPORT_IMMU_TABLE6_M ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S)) 3845 #define DPORT_IMMU_TABLE6_V 0x7F 3846 #define DPORT_IMMU_TABLE6_S 0 3847 3848 #define DPORT_IMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x520) 3849 /* DPORT_IMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ 3850 /*description: */ 3851 #define DPORT_IMMU_TABLE7 0x0000007F 3852 #define DPORT_IMMU_TABLE7_M ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S)) 3853 #define DPORT_IMMU_TABLE7_V 0x7F 3854 #define DPORT_IMMU_TABLE7_S 0 3855 3856 #define DPORT_IMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x524) 3857 /* DPORT_IMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ 3858 /*description: */ 3859 #define DPORT_IMMU_TABLE8 0x0000007F 3860 #define DPORT_IMMU_TABLE8_M ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S)) 3861 #define DPORT_IMMU_TABLE8_V 0x7F 3862 #define DPORT_IMMU_TABLE8_S 0 3863 3864 #define DPORT_IMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x528) 3865 /* DPORT_IMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ 3866 /*description: */ 3867 #define DPORT_IMMU_TABLE9 0x0000007F 3868 #define DPORT_IMMU_TABLE9_M ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S)) 3869 #define DPORT_IMMU_TABLE9_V 0x7F 3870 #define DPORT_IMMU_TABLE9_S 0 3871 3872 #define DPORT_IMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x52C) 3873 /* DPORT_IMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ 3874 /*description: */ 3875 #define DPORT_IMMU_TABLE10 0x0000007F 3876 #define DPORT_IMMU_TABLE10_M ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S)) 3877 #define DPORT_IMMU_TABLE10_V 0x7F 3878 #define DPORT_IMMU_TABLE10_S 0 3879 3880 #define DPORT_IMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x530) 3881 /* DPORT_IMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ 3882 /*description: */ 3883 #define DPORT_IMMU_TABLE11 0x0000007F 3884 #define DPORT_IMMU_TABLE11_M ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S)) 3885 #define DPORT_IMMU_TABLE11_V 0x7F 3886 #define DPORT_IMMU_TABLE11_S 0 3887 3888 #define DPORT_IMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x534) 3889 /* DPORT_IMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ 3890 /*description: */ 3891 #define DPORT_IMMU_TABLE12 0x0000007F 3892 #define DPORT_IMMU_TABLE12_M ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S)) 3893 #define DPORT_IMMU_TABLE12_V 0x7F 3894 #define DPORT_IMMU_TABLE12_S 0 3895 3896 #define DPORT_IMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x538) 3897 /* DPORT_IMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ 3898 /*description: */ 3899 #define DPORT_IMMU_TABLE13 0x0000007F 3900 #define DPORT_IMMU_TABLE13_M ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S)) 3901 #define DPORT_IMMU_TABLE13_V 0x7F 3902 #define DPORT_IMMU_TABLE13_S 0 3903 3904 #define DPORT_IMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x53C) 3905 /* DPORT_IMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ 3906 /*description: */ 3907 #define DPORT_IMMU_TABLE14 0x0000007F 3908 #define DPORT_IMMU_TABLE14_M ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S)) 3909 #define DPORT_IMMU_TABLE14_V 0x7F 3910 #define DPORT_IMMU_TABLE14_S 0 3911 3912 #define DPORT_IMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x540) 3913 /* DPORT_IMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ 3914 /*description: */ 3915 #define DPORT_IMMU_TABLE15 0x0000007F 3916 #define DPORT_IMMU_TABLE15_M ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S)) 3917 #define DPORT_IMMU_TABLE15_V 0x7F 3918 #define DPORT_IMMU_TABLE15_S 0 3919 3920 #define DPORT_DMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x544) 3921 /* DPORT_DMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ 3922 /*description: */ 3923 #define DPORT_DMMU_TABLE0 0x0000007F 3924 #define DPORT_DMMU_TABLE0_M ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S)) 3925 #define DPORT_DMMU_TABLE0_V 0x7F 3926 #define DPORT_DMMU_TABLE0_S 0 3927 3928 #define DPORT_DMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x548) 3929 /* DPORT_DMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ 3930 /*description: */ 3931 #define DPORT_DMMU_TABLE1 0x0000007F 3932 #define DPORT_DMMU_TABLE1_M ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S)) 3933 #define DPORT_DMMU_TABLE1_V 0x7F 3934 #define DPORT_DMMU_TABLE1_S 0 3935 3936 #define DPORT_DMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x54C) 3937 /* DPORT_DMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ 3938 /*description: */ 3939 #define DPORT_DMMU_TABLE2 0x0000007F 3940 #define DPORT_DMMU_TABLE2_M ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S)) 3941 #define DPORT_DMMU_TABLE2_V 0x7F 3942 #define DPORT_DMMU_TABLE2_S 0 3943 3944 #define DPORT_DMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x550) 3945 /* DPORT_DMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ 3946 /*description: */ 3947 #define DPORT_DMMU_TABLE3 0x0000007F 3948 #define DPORT_DMMU_TABLE3_M ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S)) 3949 #define DPORT_DMMU_TABLE3_V 0x7F 3950 #define DPORT_DMMU_TABLE3_S 0 3951 3952 #define DPORT_DMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x554) 3953 /* DPORT_DMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ 3954 /*description: */ 3955 #define DPORT_DMMU_TABLE4 0x0000007F 3956 #define DPORT_DMMU_TABLE4_M ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S)) 3957 #define DPORT_DMMU_TABLE4_V 0x7F 3958 #define DPORT_DMMU_TABLE4_S 0 3959 3960 #define DPORT_DMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x558) 3961 /* DPORT_DMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ 3962 /*description: */ 3963 #define DPORT_DMMU_TABLE5 0x0000007F 3964 #define DPORT_DMMU_TABLE5_M ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S)) 3965 #define DPORT_DMMU_TABLE5_V 0x7F 3966 #define DPORT_DMMU_TABLE5_S 0 3967 3968 #define DPORT_DMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x55C) 3969 /* DPORT_DMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ 3970 /*description: */ 3971 #define DPORT_DMMU_TABLE6 0x0000007F 3972 #define DPORT_DMMU_TABLE6_M ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S)) 3973 #define DPORT_DMMU_TABLE6_V 0x7F 3974 #define DPORT_DMMU_TABLE6_S 0 3975 3976 #define DPORT_DMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x560) 3977 /* DPORT_DMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ 3978 /*description: */ 3979 #define DPORT_DMMU_TABLE7 0x0000007F 3980 #define DPORT_DMMU_TABLE7_M ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S)) 3981 #define DPORT_DMMU_TABLE7_V 0x7F 3982 #define DPORT_DMMU_TABLE7_S 0 3983 3984 #define DPORT_DMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x564) 3985 /* DPORT_DMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ 3986 /*description: */ 3987 #define DPORT_DMMU_TABLE8 0x0000007F 3988 #define DPORT_DMMU_TABLE8_M ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S)) 3989 #define DPORT_DMMU_TABLE8_V 0x7F 3990 #define DPORT_DMMU_TABLE8_S 0 3991 3992 #define DPORT_DMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x568) 3993 /* DPORT_DMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ 3994 /*description: */ 3995 #define DPORT_DMMU_TABLE9 0x0000007F 3996 #define DPORT_DMMU_TABLE9_M ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S)) 3997 #define DPORT_DMMU_TABLE9_V 0x7F 3998 #define DPORT_DMMU_TABLE9_S 0 3999 4000 #define DPORT_DMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x56C) 4001 /* DPORT_DMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ 4002 /*description: */ 4003 #define DPORT_DMMU_TABLE10 0x0000007F 4004 #define DPORT_DMMU_TABLE10_M ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S)) 4005 #define DPORT_DMMU_TABLE10_V 0x7F 4006 #define DPORT_DMMU_TABLE10_S 0 4007 4008 #define DPORT_DMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x570) 4009 /* DPORT_DMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ 4010 /*description: */ 4011 #define DPORT_DMMU_TABLE11 0x0000007F 4012 #define DPORT_DMMU_TABLE11_M ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S)) 4013 #define DPORT_DMMU_TABLE11_V 0x7F 4014 #define DPORT_DMMU_TABLE11_S 0 4015 4016 #define DPORT_DMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x574) 4017 /* DPORT_DMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ 4018 /*description: */ 4019 #define DPORT_DMMU_TABLE12 0x0000007F 4020 #define DPORT_DMMU_TABLE12_M ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S)) 4021 #define DPORT_DMMU_TABLE12_V 0x7F 4022 #define DPORT_DMMU_TABLE12_S 0 4023 4024 #define DPORT_DMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x578) 4025 /* DPORT_DMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ 4026 /*description: */ 4027 #define DPORT_DMMU_TABLE13 0x0000007F 4028 #define DPORT_DMMU_TABLE13_M ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S)) 4029 #define DPORT_DMMU_TABLE13_V 0x7F 4030 #define DPORT_DMMU_TABLE13_S 0 4031 4032 #define DPORT_DMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x57C) 4033 /* DPORT_DMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ 4034 /*description: */ 4035 #define DPORT_DMMU_TABLE14 0x0000007F 4036 #define DPORT_DMMU_TABLE14_M ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S)) 4037 #define DPORT_DMMU_TABLE14_V 0x7F 4038 #define DPORT_DMMU_TABLE14_S 0 4039 4040 #define DPORT_DMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x580) 4041 /* DPORT_DMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ 4042 /*description: */ 4043 #define DPORT_DMMU_TABLE15 0x0000007F 4044 #define DPORT_DMMU_TABLE15_M ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S)) 4045 #define DPORT_DMMU_TABLE15_V 0x7F 4046 #define DPORT_DMMU_TABLE15_S 0 4047 4048 #define DPORT_PRO_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x584) 4049 /* DPORT_PRO_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ 4050 /*description: */ 4051 #define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0)) 4052 #define DPORT_PRO_INTRUSION_RECORD_RESET_N_M (BIT(0)) 4053 #define DPORT_PRO_INTRUSION_RECORD_RESET_N_V 0x1 4054 #define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0 4055 4056 #define DPORT_PRO_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x588) 4057 /* DPORT_PRO_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ 4058 /*description: */ 4059 #define DPORT_PRO_INTRUSION_RECORD 0x0000000F 4060 #define DPORT_PRO_INTRUSION_RECORD_M ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S)) 4061 #define DPORT_PRO_INTRUSION_RECORD_V 0xF 4062 #define DPORT_PRO_INTRUSION_RECORD_S 0 4063 4064 #define DPORT_APP_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x58C) 4065 /* DPORT_APP_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ 4066 /*description: */ 4067 #define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0)) 4068 #define DPORT_APP_INTRUSION_RECORD_RESET_N_M (BIT(0)) 4069 #define DPORT_APP_INTRUSION_RECORD_RESET_N_V 0x1 4070 #define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0 4071 4072 #define DPORT_APP_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x590) 4073 /* DPORT_APP_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ 4074 /*description: */ 4075 #define DPORT_APP_INTRUSION_RECORD 0x0000000F 4076 #define DPORT_APP_INTRUSION_RECORD_M ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S)) 4077 #define DPORT_APP_INTRUSION_RECORD_V 0xF 4078 #define DPORT_APP_INTRUSION_RECORD_S 0 4079 4080 #define DPORT_FRONT_END_MEM_PD_REG (DR_REG_DPORT_BASE + 0x594) 4081 /* DPORT_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 4082 /*description: */ 4083 #define DPORT_PBUS_MEM_FORCE_PD (BIT(3)) 4084 #define DPORT_PBUS_MEM_FORCE_PD_M (BIT(3)) 4085 #define DPORT_PBUS_MEM_FORCE_PD_V 0x1 4086 #define DPORT_PBUS_MEM_FORCE_PD_S 3 4087 /* DPORT_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 4088 /*description: */ 4089 #define DPORT_PBUS_MEM_FORCE_PU (BIT(2)) 4090 #define DPORT_PBUS_MEM_FORCE_PU_M (BIT(2)) 4091 #define DPORT_PBUS_MEM_FORCE_PU_V 0x1 4092 #define DPORT_PBUS_MEM_FORCE_PU_S 2 4093 /* DPORT_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 4094 /*description: */ 4095 #define DPORT_AGC_MEM_FORCE_PD (BIT(1)) 4096 #define DPORT_AGC_MEM_FORCE_PD_M (BIT(1)) 4097 #define DPORT_AGC_MEM_FORCE_PD_V 0x1 4098 #define DPORT_AGC_MEM_FORCE_PD_S 1 4099 /* DPORT_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ 4100 /*description: */ 4101 #define DPORT_AGC_MEM_FORCE_PU (BIT(0)) 4102 #define DPORT_AGC_MEM_FORCE_PU_M (BIT(0)) 4103 #define DPORT_AGC_MEM_FORCE_PU_V 0x1 4104 #define DPORT_AGC_MEM_FORCE_PU_S 0 4105 4106 #define DPORT_MMU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x598) 4107 /* DPORT_MMU_IA_INT_EN : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ 4108 /*description: */ 4109 #define DPORT_MMU_IA_INT_EN 0x00FFFFFF 4110 #define DPORT_MMU_IA_INT_EN_M ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S)) 4111 #define DPORT_MMU_IA_INT_EN_V 0xFFFFFF 4112 #define DPORT_MMU_IA_INT_EN_S 0 4113 4114 #define DPORT_MPU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x59C) 4115 /* DPORT_MPU_IA_INT_EN : R/W ;bitpos:[16:0] ;default: 17'b0 ; */ 4116 /*description: */ 4117 #define DPORT_MPU_IA_INT_EN 0x0001FFFF 4118 #define DPORT_MPU_IA_INT_EN_M ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S)) 4119 #define DPORT_MPU_IA_INT_EN_V 0x1FFFF 4120 #define DPORT_MPU_IA_INT_EN_S 0 4121 4122 #define DPORT_CACHE_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x5A0) 4123 /* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ 4124 /*description: Interrupt enable bits for various invalid cache access reasons*/ 4125 #define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF 4126 #define DPORT_CACHE_IA_INT_EN_M ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S)) 4127 #define DPORT_CACHE_IA_INT_EN_V 0xFFFFFFF 4128 #define DPORT_CACHE_IA_INT_EN_S 0 4129 /* Contents of DPORT_CACHE_IA_INT_EN field: */ 4130 /* DPORT_CACHE_IA_INT_PRO_OPPOSITE : R/W ;bitpos:[19] ;default: 1'b0 ; */ 4131 /*description: PRO CPU invalid access to APP CPU cache when cache disabled */ 4132 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE BIT(19) 4133 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE_M BIT(19) 4134 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE_V (1) 4135 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE_S (19) 4136 /* DPORT_CACHE_IA_INT_PRO_DRAM1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ 4137 /*description: PRO CPU invalid access to DRAM1 when cache is disabled */ 4138 #define DPORT_CACHE_IA_INT_PRO_DRAM1 BIT(18) 4139 #define DPORT_CACHE_IA_INT_PRO_DRAM1_M BIT(18) 4140 #define DPORT_CACHE_IA_INT_PRO_DRAM1_V (1) 4141 #define DPORT_CACHE_IA_INT_PRO_DRAM1_S (18) 4142 /* DPORT_CACHE_IA_INT_PRO_IROM0 : R/W ;bitpos:[17] ;default: 1'b0 ; */ 4143 /*description: PRO CPU invalid access to IROM0 when cache is disabled */ 4144 #define DPORT_CACHE_IA_INT_PRO_IROM0 BIT(17) 4145 #define DPORT_CACHE_IA_INT_PRO_IROM0_M BIT(17) 4146 #define DPORT_CACHE_IA_INT_PRO_IROM0_V (1) 4147 #define DPORT_CACHE_IA_INT_PRO_IROM0_S (17) 4148 /* DPORT_CACHE_IA_INT_PRO_IRAM1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ 4149 /*description: PRO CPU invalid access to IRAM1 when cache is disabled */ 4150 #define DPORT_CACHE_IA_INT_PRO_IRAM1 BIT(16) 4151 #define DPORT_CACHE_IA_INT_PRO_IRAM1_M BIT(16) 4152 #define DPORT_CACHE_IA_INT_PRO_IRAM1_V (1) 4153 #define DPORT_CACHE_IA_INT_PRO_IRAM1_S (16) 4154 /* DPORT_CACHE_IA_INT_PRO_IRAM0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ 4155 /*description: PRO CPU invalid access to IRAM0 when cache is disabled */ 4156 #define DPORT_CACHE_IA_INT_PRO_IRAM0 BIT(15) 4157 #define DPORT_CACHE_IA_INT_PRO_IRAM0_M BIT(15) 4158 #define DPORT_CACHE_IA_INT_PRO_IRAM0_V (1) 4159 #define DPORT_CACHE_IA_INT_PRO_IRAM0_S (15) 4160 /* DPORT_CACHE_IA_INT_PRO_DROM0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ 4161 /*description: PRO CPU invalid access to DROM0 when cache is disabled */ 4162 #define DPORT_CACHE_IA_INT_PRO_DROM0 BIT(14) 4163 #define DPORT_CACHE_IA_INT_PRO_DROM0_M BIT(14) 4164 #define DPORT_CACHE_IA_INT_PRO_DROM0_V (1) 4165 #define DPORT_CACHE_IA_INT_PRO_DROM0_S (14) 4166 /* DPORT_CACHE_IA_INT_APP_OPPOSITE : R/W ;bitpos:[5] ;default: 1'b0 ; */ 4167 /*description: APP CPU invalid access to APP CPU cache when cache disabled */ 4168 #define DPORT_CACHE_IA_INT_APP_OPPOSITE BIT(5) 4169 #define DPORT_CACHE_IA_INT_APP_OPPOSITE_M BIT(5) 4170 #define DPORT_CACHE_IA_INT_APP_OPPOSITE_V (1) 4171 #define DPORT_CACHE_IA_INT_APP_OPPOSITE_S (5) 4172 /* DPORT_CACHE_IA_INT_APP_DRAM1 : R/W ;bitpos:43] ;default: 1'b0 ; */ 4173 /*description: APP CPU invalid access to DRAM1 when cache is disabled */ 4174 #define DPORT_CACHE_IA_INT_APP_DRAM1 BIT(4) 4175 #define DPORT_CACHE_IA_INT_APP_DRAM1_M BIT(4) 4176 #define DPORT_CACHE_IA_INT_APP_DRAM1_V (1) 4177 #define DPORT_CACHE_IA_INT_APP_DRAM1_S (4) 4178 /* DPORT_CACHE_IA_INT_APP_IROM0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ 4179 /*description: APP CPU invalid access to IROM0 when cache is disabled */ 4180 #define DPORT_CACHE_IA_INT_APP_IROM0 BIT(3) 4181 #define DPORT_CACHE_IA_INT_APP_IROM0_M BIT(3) 4182 #define DPORT_CACHE_IA_INT_APP_IROM0_V (1) 4183 #define DPORT_CACHE_IA_INT_APP_IROM0_S (3) 4184 /* DPORT_CACHE_IA_INT_APP_IRAM1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ 4185 /*description: APP CPU invalid access to IRAM1 when cache is disabled */ 4186 #define DPORT_CACHE_IA_INT_APP_IRAM1 BIT(2) 4187 #define DPORT_CACHE_IA_INT_APP_IRAM1_M BIT(2) 4188 #define DPORT_CACHE_IA_INT_APP_IRAM1_V (1) 4189 #define DPORT_CACHE_IA_INT_APP_IRAM1_S (2) 4190 /* DPORT_CACHE_IA_INT_APP_IRAM0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ 4191 /*description: APP CPU invalid access to IRAM0 when cache is disabled */ 4192 #define DPORT_CACHE_IA_INT_APP_IRAM0 BIT(1) 4193 #define DPORT_CACHE_IA_INT_APP_IRAM0_M BIT(1) 4194 #define DPORT_CACHE_IA_INT_APP_IRAM0_V (1) 4195 #define DPORT_CACHE_IA_INT_APP_IRAM0_S (1) 4196 /* DPORT_CACHE_IA_INT_APP_DROM0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 4197 /*description: APP CPU invalid access to DROM0 when cache is disabled */ 4198 #define DPORT_CACHE_IA_INT_APP_DROM0 BIT(0) 4199 #define DPORT_CACHE_IA_INT_APP_DROM0_M BIT(0) 4200 #define DPORT_CACHE_IA_INT_APP_DROM0_V (1) 4201 #define DPORT_CACHE_IA_INT_APP_DROM0_S (0) 4202 4203 #define DPORT_SECURE_BOOT_CTRL_REG (DR_REG_DPORT_BASE + 0x5A4) 4204 /* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ 4205 /*description: */ 4206 #define DPORT_SW_BOOTLOADER_SEL (BIT(0)) 4207 #define DPORT_SW_BOOTLOADER_SEL_M (BIT(0)) 4208 #define DPORT_SW_BOOTLOADER_SEL_V 0x1 4209 #define DPORT_SW_BOOTLOADER_SEL_S 0 4210 4211 #define DPORT_SPI_DMA_CHAN_SEL_REG (DR_REG_DPORT_BASE + 0x5A8) 4212 /* DPORT_SPI3_DMA_CHAN_SEL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ 4213 /*description: */ 4214 #define DPORT_SPI3_DMA_CHAN_SEL 0x00000003 4215 #define DPORT_SPI3_DMA_CHAN_SEL_M ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S)) 4216 #define DPORT_SPI3_DMA_CHAN_SEL_V 0x3 4217 #define DPORT_SPI3_DMA_CHAN_SEL_S 4 4218 /* DPORT_SPI2_DMA_CHAN_SEL : R/W ;bitpos:[3:2] ;default: 2'b00 ; */ 4219 /*description: */ 4220 #define DPORT_SPI2_DMA_CHAN_SEL 0x00000003 4221 #define DPORT_SPI2_DMA_CHAN_SEL_M ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S)) 4222 #define DPORT_SPI2_DMA_CHAN_SEL_V 0x3 4223 #define DPORT_SPI2_DMA_CHAN_SEL_S 2 4224 /* DPORT_SPI1_DMA_CHAN_SEL : R/W ;bitpos:[1:0] ;default: 2'b00 ; */ 4225 /*description: */ 4226 #define DPORT_SPI1_DMA_CHAN_SEL 0x00000003 4227 #define DPORT_SPI1_DMA_CHAN_SEL_M ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S)) 4228 #define DPORT_SPI1_DMA_CHAN_SEL_V 0x3 4229 #define DPORT_SPI1_DMA_CHAN_SEL_S 0 4230 4231 #define DPORT_PRO_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5AC) 4232 /* DPORT_PRO_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 4233 /*description: */ 4234 #define DPORT_PRO_OUT_VECBASE_SEL 0x00000003 4235 #define DPORT_PRO_OUT_VECBASE_SEL_M ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S)) 4236 #define DPORT_PRO_OUT_VECBASE_SEL_V 0x3 4237 #define DPORT_PRO_OUT_VECBASE_SEL_S 0 4238 4239 #define DPORT_PRO_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B0) 4240 /* DPORT_PRO_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ 4241 /*description: */ 4242 #define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF 4243 #define DPORT_PRO_OUT_VECBASE_REG_M ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S)) 4244 #define DPORT_PRO_OUT_VECBASE_REG_V 0x3FFFFF 4245 #define DPORT_PRO_OUT_VECBASE_REG_S 0 4246 4247 #define DPORT_APP_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5B4) 4248 /* DPORT_APP_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 4249 /*description: */ 4250 #define DPORT_APP_OUT_VECBASE_SEL 0x00000003 4251 #define DPORT_APP_OUT_VECBASE_SEL_M ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S)) 4252 #define DPORT_APP_OUT_VECBASE_SEL_V 0x3 4253 #define DPORT_APP_OUT_VECBASE_SEL_S 0 4254 4255 #define DPORT_APP_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B8) 4256 /* DPORT_APP_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ 4257 /*description: */ 4258 #define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF 4259 #define DPORT_APP_OUT_VECBASE_REG_M ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S)) 4260 #define DPORT_APP_OUT_VECBASE_REG_V 0x3FFFFF 4261 #define DPORT_APP_OUT_VECBASE_REG_S 0 4262 4263 #define DPORT_DATE_REG (DR_REG_DPORT_BASE + 0xFFC) 4264 /* DPORT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605190 ; */ 4265 /*description: */ 4266 #define DPORT_DATE 0x0FFFFFFF 4267 #define DPORT_DATE_M ((DPORT_DATE_V)<<(DPORT_DATE_S)) 4268 #define DPORT_DATE_V 0xFFFFFFF 4269 #define DPORT_DATE_S 0 4270 #define DPORT_DPORT_DATE_VERSION 0x1605190 4271 4272 /* Flash MMU table for PRO CPU */ 4273 #define DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF10000) 4274 4275 /* Flash MMU table for APP CPU */ 4276 #define DPORT_APP_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF12000) 4277 4278 #define DPORT_FLASH_MMU_TABLE_SIZE 0x100 4279 4280 #define DPORT_FLASH_MMU_TABLE_INVALID_VAL 0x100 4281 4282 #define DPORT_MMU_ADDRESS_MASK 0xff 4283 4284 #define TRACEMEM_MUX_PROBLK0_APPBLK1 0 4285 #define TRACEMEM_MUX_BLK0_ONLY 1 4286 #define TRACEMEM_MUX_BLK1_ONLY 2 4287 #define TRACEMEM_MUX_PROBLK1_APPBLK0 3 4288 4289 #endif /*_SOC_DPORT_REG_H_ */ 4290
