1 /* 2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _CACHE_MEMORY_H_ 7 #define _CACHE_MEMORY_H_ 8 9 #include "esp_bit_defs.h" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /*IRAM0 is connected with Cache IBUS0*/ 16 #define IRAM0_ADDRESS_LOW 0x40000000 17 #define IRAM0_ADDRESS_HIGH 0x40400000 18 #define IRAM0_CACHE_ADDRESS_LOW 0x40080000 19 #define IRAM0_CACHE_ADDRESS_HIGH 0x40400000 20 21 /*IRAM1 is connected with Cache IBUS1*/ 22 #define IRAM1_ADDRESS_LOW 0x40400000 23 #define IRAM1_ADDRESS_HIGH 0x40800000 24 25 /*DROM0 is connected with Cache IBUS2*/ 26 #define DROM0_ADDRESS_LOW 0x3f000000 27 #define DROM0_ADDRESS_HIGH 0x3f400000 28 29 /*DRAM0 is connected with Cache DBUS0*/ 30 #define DRAM0_ADDRESS_LOW 0x3fc00000 31 #define DRAM0_ADDRESS_HIGH 0x40000000 32 #define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000 33 #define DRAM0_CACHE_ADDRESS_HIGH 0x3ff80000 34 35 /*DRAM1 is connected with Cache DBUS1*/ 36 #define DRAM1_ADDRESS_LOW 0x3f800000 37 #define DRAM1_ADDRESS_HIGH 0x3fc00000 38 39 /*DPORT is connected with Cache DBUS2*/ 40 #define DPORT_ADDRESS_LOW 0x3f400000 41 #define DPORT_ADDRESS_HIGH 0x3f800000 42 #define DPORT_CACHE_ADDRESS_LOW 0x3f500000 43 #define DPORT_CACHE_ADDRESS_HIGH 0x3f800000 44 45 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) 46 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) 47 48 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) 49 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) 50 #define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr) 51 #define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr) 52 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) 53 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) 54 #define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr) 55 #define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr) 56 #define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr) 57 58 #define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) 59 #define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1) 60 #define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0) 61 #define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0) 62 #define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) 63 #define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1) 64 #define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT_CACHE) 65 66 #define PRO_CACHE_IBUS0 0 67 #define PRO_CACHE_IBUS0_MMU_START 0 68 #define PRO_CACHE_IBUS0_MMU_END 0x100 69 70 #define PRO_CACHE_IBUS1 1 71 #define PRO_CACHE_IBUS1_MMU_START 0x100 72 #define PRO_CACHE_IBUS1_MMU_END 0x200 73 74 #define PRO_CACHE_IBUS2 2 75 #define PRO_CACHE_IBUS2_MMU_START 0x200 76 #define PRO_CACHE_IBUS2_MMU_END 0x300 77 78 #define PRO_CACHE_DBUS0 3 79 #define PRO_CACHE_DBUS0_MMU_START 0x300 80 #define PRO_CACHE_DBUS0_MMU_END 0x400 81 82 #define PRO_CACHE_DBUS1 4 83 #define PRO_CACHE_DBUS1_MMU_START 0x400 84 #define PRO_CACHE_DBUS1_MMU_END 0x500 85 86 #define PRO_CACHE_DBUS2 5 87 #define PRO_CACHE_DBUS2_MMU_START 0x500 88 #define PRO_CACHE_DBUS2_MMU_END 0x600 89 90 #define ICACHE_MMU_SIZE 0x300 91 #define DCACHE_MMU_SIZE 0x300 92 93 #define MMU_BUS_START(i) ((i) * 0x100) 94 #define MMU_BUS_SIZE 0x100 95 96 #define MMU_INVALID BIT(14) 97 #define MMU_VALID 0 98 #define MMU_ACCESS_FLASH BIT(15) 99 #define MMU_ACCESS_SPIRAM BIT(16) 100 101 /** 102 * MMU entry valid bit mask for mapping value. For an entry: 103 * valid bit + value bits 104 * valid bit is BIT(14), so value bits are 0x3fff 105 */ 106 #define MMU_VALID_VAL_MASK 0x3fff 107 /** 108 * Max MMU available paddr page num. 109 * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: 110 * 16384 * 64KB, means MMU can support 1GB paddr at most 111 */ 112 #define MMU_MAX_PADDR_PAGE_NUM 16384 113 /** 114 * This is the mask used for mapping. e.g.: 115 * 0x4200_0000 & MMU_VADDR_MASK 116 */ 117 #define MMU_VADDR_MASK 0x3FFFFF 118 //MMU entry num 119 #define MMU_ENTRY_NUM 384 120 121 #define BUS_NUM_MASK 0x3 122 123 #define CACHE_MEMORY_BANK_SIZE 8192 124 #define CACHE_MEMORY_BANK_NUM 4 125 #define CACHE_MEMORY_BANK_NUM_MASK 0x3 126 #define CACHE_MEMORY_LAYOUT_SHIFT 4 127 #define CACHE_MEMORY_LAYOUT_SHIFT0 0 128 #define CACHE_MEMORY_LAYOUT_SHIFT1 4 129 #define CACHE_MEMORY_LAYOUT_SHIFT2 8 130 #define CACHE_MEMORY_LAYOUT_SHIFT3 12 131 #define CACHE_MEMORY_LAYOUT_MASK 0xf 132 #define CACHE_MEMORY_BANK0_ADDR 0x3FFB0000 133 #define CACHE_MEMORY_BANK1_ADDR 0x3FFB2000 134 #define CACHE_MEMORY_BANK2_ADDR 0x3FFB4000 135 #define CACHE_MEMORY_BANK3_ADDR 0x3FFB6000 136 137 138 #define SOC_MMU_DBUS_VADDR_BASE 0x3E000000 139 #define SOC_MMU_IBUS_VADDR_BASE 0x40000000 140 141 /*------------------------------------------------------------------------------ 142 * MMU Linear Address 143 *----------------------------------------------------------------------------*/ 144 /** 145 * - 64KB MMU page size: the last 0xFFFF, which is the offset 146 * - 384 MMU entries, needs 0x1FF to hold it. 147 * 148 * Therefore, 0x1FF,FFFF 149 */ 150 #define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF 151 152 #define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 153 #define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 154 155 #define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW (IRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 156 #define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH (IRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 157 158 #define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW (DROM0_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 159 #define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH (DROM0_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 160 161 #define SOC_MMU_DPORT_LINEAR_ADDRESS_LOW (DPORT_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 162 #define SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH (DPORT_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 163 164 #define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW (DRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 165 #define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH (DRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 166 167 #define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 168 #define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 169 170 #ifdef __cplusplus 171 } 172 #endif 173 174 #endif /*_CACHE_MEMORY_H_ */ 175
