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Searched refs:CACHE_BUS_IBUS1 (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-3.7.0/components/hal/esp32s2/include/hal/
Dcache_ll.h46 mask |= CACHE_BUS_IBUS1; in cache_ll_l1_get_bus()
49 mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
53 mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
58 mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
64 mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
71 mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
94 ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0; in cache_ll_l1_enable_bus()
118 ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0; in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32/include/hal/
Dcache_ll.h46 mask |= CACHE_BUS_IBUS1; in cache_ll_l1_get_bus()
50 mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
83 bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0; in cache_ll_l1_enable_bus()
92 bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0; in cache_ll_l1_enable_bus()
117 mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_enabled_bus()
125 mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_enabled_bus()
150 bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0; in cache_ll_l1_disable_bus()
159 bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0; in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32h2/include/hal/
Dcache_ll.h70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32c6/include/hal/
Dcache_ll.h70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32c3/include/hal/
Dcache_ll.h81 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
103 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32c2/include/hal/
Dcache_ll.h80 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
102 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/include/hal/
Dcache_types.h30 CACHE_BUS_IBUS1 = BIT(1), enumerator
/hal_espressif-3.7.0/components/hal/esp32s3/include/hal/
Dcache_ll.h84 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
145 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()