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Searched refs:CACHE_BUS_DBUS0 (Results 1 – 15 of 15) sorted by relevance

/hal_espressif-3.7.0/components/hal/esp32s3/include/hal/
Dcache_ll.h23 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
63 mask |= CACHE_BUS_DBUS0; //Both cores have their own DBUS0 in cache_ll_l1_get_bus()
96 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_enable_bus()
98 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_enable_bus()
126 mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_enabled_bus()
128 mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_enabled_bus()
157 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_disable_bus()
159 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32s2/include/hal/
Dcache_ll.h51 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
56 mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_bus()
62 mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_bus()
69 mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_bus()
99 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0; in cache_ll_l1_enable_bus()
123 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0; in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32/include/hal/
Dcache_ll.h57 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
86 bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0; in cache_ll_l1_enable_bus()
95 bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0; in cache_ll_l1_enable_bus()
120 mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_enabled_bus()
128 mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_enabled_bus()
153 bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0; in cache_ll_l1_disable_bus()
162 bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0; in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32h2/include/hal/
Dcache_ll.h22 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
49 mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
77 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0; in cache_ll_l1_enable_bus()
99 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0; in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32c6/include/hal/
Dcache_ll.h22 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
49 mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
77 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()
99 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0; in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32c3/include/hal/
Dcache_ll.h22 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
60 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
88 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()
110 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/hal/esp32c2/include/hal/
Dcache_ll.h22 #define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
59 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
87 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()
109 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_disable_bus()
/hal_espressif-3.7.0/components/esp_mm/port/esp32c3/
Dext_mem_layout.c21 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
/hal_espressif-3.7.0/components/esp_mm/port/esp32c6/
Dext_mem_layout.c22 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
/hal_espressif-3.7.0/components/esp_mm/port/esp32h2/
Dext_mem_layout.c22 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
/hal_espressif-3.7.0/components/hal/include/hal/
Dcache_types.h32 CACHE_BUS_DBUS0 = BIT(3), enumerator
/hal_espressif-3.7.0/components/esp_mm/port/esp32c2/
Dext_mem_layout.c21 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
/hal_espressif-3.7.0/components/esp_mm/port/esp32s3/
Dext_mem_layout.c21 .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
/hal_espressif-3.7.0/components/esp_mm/port/esp32/
Dext_mem_layout.c30 .bus_id = CACHE_BUS_DBUS0,
/hal_espressif-3.7.0/components/esp_mm/port/esp32s2/
Dext_mem_layout.c54 .bus_id = CACHE_BUS_DBUS0,