1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_I2C_STRUCT_H_ 15 #define _SOC_I2C_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct i2c_dev_s { 24 union { 25 struct { 26 uint32_t period:14; /*This register is used to configure the low level width of SCL clock.*/ 27 uint32_t reserved14: 18; 28 }; 29 uint32_t val; 30 } scl_low_period; 31 union { 32 struct { 33 uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ 34 uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ 35 uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/ 36 uint32_t reserved3: 1; 37 uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/ 38 uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/ 39 uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data need to be send. 1：receive data from most significant bit 0：receive data from least significant bit*/ 40 uint32_t rx_lsb_first: 1; /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit 0：receive data from least significant bit*/ 41 uint32_t clk_en: 1; /*This is the clock gating control bit for reading or writing registers.*/ 42 uint32_t reserved9: 23; 43 }; 44 uint32_t val; 45 } ctr; 46 union { 47 struct { 48 uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/ 49 uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/ 50 uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/ 51 uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/ 52 uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ 53 uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/ 54 uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/ 55 uint32_t reserved7: 1; 56 uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/ 57 uint32_t reserved14: 4; 58 uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/ 59 uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ 60 uint32_t reserved27: 1; 61 uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ 62 uint32_t reserved31: 1; 63 }; 64 uint32_t val; 65 } status_reg; 66 union { 67 struct { 68 uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data, unit: APB clock cycle.*/ 69 uint32_t reserved20:12; 70 }; 71 uint32_t val; 72 } timeout; 73 union { 74 struct { 75 uint32_t addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/ 76 uint32_t reserved15: 16; 77 uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/ 78 }; 79 uint32_t val; 80 } slave_addr; 81 union { 82 struct { 83 uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ 84 uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ 85 uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ 86 uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ 87 uint32_t reserved20: 12; 88 }; 89 uint32_t val; 90 } fifo_st; 91 union { 92 struct { 93 uint32_t rx_fifo_full_thrhd: 5; 94 uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/ 95 uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/ 96 uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/ 97 uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/ 98 uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/ 99 uint32_t nonfifo_rx_thres: 6; /*when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ 100 uint32_t nonfifo_tx_thres: 6; /*when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ 101 uint32_t reserved26: 6; 102 }; 103 uint32_t val; 104 } fifo_conf; 105 union { 106 struct { 107 uint32_t data: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ 108 uint32_t reserved: 24; 109 }; 110 uint32_t val; 111 } fifo_data; 112 union { 113 struct { 114 uint32_t rx_fifo_full: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/ 115 uint32_t tx_fifo_empty: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/ 116 uint32_t rx_fifo_ovf: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/ 117 uint32_t end_detect: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/ 118 uint32_t slave_tran_comp: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/ 119 uint32_t arbitration_lost: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ 120 uint32_t master_tran_comp: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ 121 uint32_t trans_complete: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ 122 uint32_t time_out: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ 123 uint32_t trans_start: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/ 124 uint32_t ack_err: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ 125 uint32_t rx_rec_full: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ 126 uint32_t tx_send_empty: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ 127 uint32_t reserved13: 19; 128 }; 129 uint32_t val; 130 } int_raw; 131 union { 132 struct { 133 uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/ 134 uint32_t tx_fifo_empty: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/ 135 uint32_t rx_fifo_ovf: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/ 136 uint32_t end_detect: 1; /*Set this bit to clear the end_detect_int interrupt.*/ 137 uint32_t slave_tran_comp: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/ 138 uint32_t arbitration_lost: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/ 139 uint32_t master_tran_comp: 1; /*Set this bit to clear the master_tran_comp interrupt.*/ 140 uint32_t trans_complete: 1; /*Set this bit to clear the trans_complete_int interrupt.*/ 141 uint32_t time_out: 1; /*Set this bit to clear the time_out_int interrupt.*/ 142 uint32_t trans_start: 1; /*Set this bit to clear the trans_start_int interrupt.*/ 143 uint32_t ack_err: 1; /*Set this bit to clear the ack_err_int interrupt.*/ 144 uint32_t rx_rec_full: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/ 145 uint32_t tx_send_empty: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/ 146 uint32_t reserved13: 19; 147 }; 148 uint32_t val; 149 } int_clr; 150 union { 151 struct { 152 uint32_t rx_fifo_full: 1; /*The enable bit for rx_fifo_full_int interrupt.*/ 153 uint32_t tx_fifo_empty: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/ 154 uint32_t rx_fifo_ovf: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/ 155 uint32_t end_detect: 1; /*The enable bit for end_detect_int interrupt.*/ 156 uint32_t slave_tran_comp: 1; /*The enable bit for slave_tran_comp_int interrupt.*/ 157 uint32_t arbitration_lost: 1; /*The enable bit for arbitration_lost_int interrupt.*/ 158 uint32_t master_tran_comp: 1; /*The enable bit for master_tran_comp_int interrupt.*/ 159 uint32_t trans_complete: 1; /*The enable bit for trans_complete_int interrupt.*/ 160 uint32_t time_out: 1; /*The enable bit for time_out_int interrupt.*/ 161 uint32_t trans_start: 1; /*The enable bit for trans_start_int interrupt.*/ 162 uint32_t ack_err: 1; /*The enable bit for ack_err_int interrupt.*/ 163 uint32_t rx_rec_full: 1; /*The enable bit for rx_rec_full_int interrupt.*/ 164 uint32_t tx_send_empty: 1; /*The enable bit for tx_send_empty_int interrupt.*/ 165 uint32_t reserved13: 19; 166 }; 167 uint32_t val; 168 } int_ena; 169 union { 170 struct { 171 uint32_t rx_fifo_full: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/ 172 uint32_t tx_fifo_empty: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/ 173 uint32_t rx_fifo_ovf: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/ 174 uint32_t end_detect: 1; /*The masked interrupt status for end_detect_int interrupt.*/ 175 uint32_t slave_tran_comp: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/ 176 uint32_t arbitration_lost: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/ 177 uint32_t master_tran_comp: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/ 178 uint32_t trans_complete: 1; /*The masked interrupt status for trans_complete_int interrupt.*/ 179 uint32_t time_out: 1; /*The masked interrupt status for time_out_int interrupt.*/ 180 uint32_t trans_start: 1; /*The masked interrupt status for trans_start_int interrupt.*/ 181 uint32_t ack_err: 1; /*The masked interrupt status for ack_err_int interrupt.*/ 182 uint32_t rx_rec_full: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/ 183 uint32_t tx_send_empty: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/ 184 uint32_t reserved13: 19; 185 }; 186 uint32_t val; 187 } int_status; 188 union { 189 struct { 190 uint32_t time: 10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/ 191 uint32_t reserved10: 22; 192 }; 193 uint32_t val; 194 } sda_hold; 195 union { 196 struct { 197 uint32_t time: 10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/ 198 uint32_t reserved10: 22; 199 }; 200 uint32_t val; 201 } sda_sample; 202 union { 203 struct { 204 uint32_t period: 14; /*This register is used to configure the clock num during SCL is low level.*/ 205 uint32_t reserved14: 18; 206 }; 207 uint32_t val; 208 } scl_high_period; 209 uint32_t reserved_3c; 210 union { 211 struct { 212 uint32_t time: 10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/ 213 uint32_t reserved10: 22; 214 }; 215 uint32_t val; 216 } scl_start_hold; 217 union { 218 struct { 219 uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/ 220 uint32_t reserved10: 22; 221 }; 222 uint32_t val; 223 } scl_rstart_setup; 224 union { 225 struct { 226 uint32_t time: 14; /*This register is used to configure the clock num after the STOP bit's posedge.*/ 227 uint32_t reserved14: 18; 228 }; 229 uint32_t val; 230 } scl_stop_hold; 231 union { 232 struct { 233 uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/ 234 uint32_t reserved10: 22; 235 }; 236 uint32_t val; 237 } scl_stop_setup; 238 union { 239 struct { 240 uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ 241 uint32_t en: 1; /*This is the filter enable bit for SCL.*/ 242 uint32_t reserved4: 28; 243 }; 244 uint32_t val; 245 } scl_filter_cfg; 246 union { 247 struct { 248 uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ 249 uint32_t en: 1; /*This is the filter enable bit for SDA.*/ 250 uint32_t reserved4: 28; 251 }; 252 uint32_t val; 253 } sda_filter_cfg; 254 union { 255 struct { 256 uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ 257 uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ 258 uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ 259 uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ 260 uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ 261 uint32_t reserved14: 17; 262 uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ 263 }; 264 uint32_t val; 265 } command[16]; 266 uint32_t reserved_98; 267 uint32_t reserved_9c; 268 uint32_t reserved_a0; 269 uint32_t reserved_a4; 270 uint32_t reserved_a8; 271 uint32_t reserved_ac; 272 uint32_t reserved_b0; 273 uint32_t reserved_b4; 274 uint32_t reserved_b8; 275 uint32_t reserved_bc; 276 uint32_t reserved_c0; 277 uint32_t reserved_c4; 278 uint32_t reserved_c8; 279 uint32_t reserved_cc; 280 uint32_t reserved_d0; 281 uint32_t reserved_d4; 282 uint32_t reserved_d8; 283 uint32_t reserved_dc; 284 uint32_t reserved_e0; 285 uint32_t reserved_e4; 286 uint32_t reserved_e8; 287 uint32_t reserved_ec; 288 uint32_t reserved_f0; 289 uint32_t reserved_f4; 290 uint32_t date; /**/ 291 uint32_t reserved_fc; 292 uint32_t ram_data[32]; /*This the start address for ram when use apb nonfifo access.*/ 293 } i2c_dev_t; 294 extern i2c_dev_t I2C0; 295 extern i2c_dev_t I2C1; 296 297 #ifdef __cplusplus 298 } 299 #endif 300 301 #endif /* _SOC_I2C_STRUCT_H_ */ 302
