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Searched refs:phase (Results 1 – 25 of 40) sorted by relevance

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/hal_espressif-3.6.0/components/hal/esp32/include/hal/
Ddac_ll.h154 static inline void dac_ll_cw_set_phase(dac_channel_t channel, dac_cw_phase_t phase) in dac_ll_cw_set_phase() argument
157 SENS.sar_dac_ctrl2.dac_inv1 = phase; in dac_ll_cw_set_phase()
159 SENS.sar_dac_ctrl2.dac_inv2 = phase; in dac_ll_cw_set_phase()
/hal_espressif-3.6.0/components/hal/esp32s2/include/hal/
Ddac_ll.h175 static inline void dac_ll_cw_set_phase(dac_channel_t channel, dac_cw_phase_t phase) in dac_ll_cw_set_phase() argument
178 SENS.sar_dac_ctrl2.dac_inv1 = phase; in dac_ll_cw_set_phase()
180 SENS.sar_dac_ctrl2.dac_inv2 = phase; in dac_ll_cw_set_phase()
/hal_espressif-3.6.0/docs/en/api-reference/protocols/
Desp_spi_slave_protocol.rst39 … This phase determines the rest phases of the transactions. See :ref:`spi_slave_hd_supported_cmds`.
43 For some commands (WRBUF, RDBUF), this phase specifies the address of shared buffer to write
44 to/read from. For other commands with this phase, they are meaningless, but still have to
49 This phase is the turn around time between the master and the slave on the bus, and also
54 This may be a data OUT phase, in which the direction is slave to master, or a data IN phase,
/hal_espressif-3.6.0/docs/_static/diagrams/spi/
Dmiso_timing_waveform.rst8 { name: 'MISO', wave: 'x3x.', node: '.b...', phase:-1.8 },
9 { name: 'MISO delayed', wave: 'x3x.', node: '.c.', phase:-2.4 },
Dmiso_timing_waveform_async.rst8 { name: 'SLV_CLK',wave: 'p..............', node: '..b..', phase: -0.5 },
9 { name: 'MISO', wave: 'x...3.....x....', node: '....c', phase:-0.5},
Dspi_slave_miso_dma.rst9 …e: 'MISO (normal)', wave: 'x3.3.3.3.3', node: '...c.d', data: ['7','6','5','4','3'], phase:-0.8},
11 …me: 'MISO (DMA)', wave: 'x33.3.3.3', node: '..g.h', data: ['7','6','5','4','3','2'], phase:-0.8},
/hal_espressif-3.6.0/components/esp_netif/lwip/
Desp_netif_lwip_ppp.c185 static void on_ppp_notify_phase(ppp_pcb *pcb, u8_t phase, void *ctx) in on_ppp_notify_phase() argument
187 switch (phase) { in on_ppp_notify_phase()
213 ESP_LOGW(TAG, "Phase Unknown: %d", phase); in on_ppp_notify_phase()
220 …esp_err_t err = esp_event_post(NETIF_PPP_STATUS, NETIF_PP_PHASE_OFFSET + phase, &netif, sizeof(net… in on_ppp_notify_phase()
/hal_espressif-3.6.0/docs/en/api-reference/peripherals/
Dspi_slave_hd.rst9 …phase of the transaction. Each transaction may consist of the following phases: command, address, …
Dspi_master.rst99 **Command** In this phase, a command (0-16 bit) is written to the bus by the Host.
100 **Address** In this phase, an address (0-{IDF_TARGET_ADDR_LEN} bit) is transmitted over the bus…
102 **Dummy** This phase is configurable and is used to meet the timing requirements.
123 …nd_bits` and/or :cpp:member:`address_bits` are set to zero, no command or address phase will occur.
125 …not set, the read phase is skipped. If :cpp:member:`tx_buffer` is NULL and :cpp:type:`SPI_TRANS_US…
210 …t::base` and configure the rest of base as usual. Then the length of each phase will be equal to :…
212 If the command and address phase need to be as the same number of lines as data phase, you need to …
525 …before the read phase begins. The Device still sees the dummy clocks and sends out data, but the H…
607 3. Try using the command and address fields to replace the write phase.
Dmcpwm.rst88 …phase. Synchronization is triggered by ``SYNC SIGNALS`` shown on the :ref:`block diagram <mcpwm_bl…
101 …eaches peak/zero. Thus, the PWM timers can be chained together with their phase-locked. During syn…
106 …sync_signal_t`, and setting the desired phase range from 0 to 999 which is mapped to 0%~99.9%. 0 m…
Dspi_slave.rst66 … set to NULL, the read phase will be skipped. If :cpp:member:`spi_slave_transaction_t::tx_buffer` …
/hal_espressif-3.6.0/components/hal/
Ddac_hal.c21 dac_ll_cw_set_phase(cw->en_ch, cw->phase); in dac_hal_cw_generator_config()
Dspi_flash_hal_common.inc109 // phase (and appended as ones).
/hal_espressif-3.6.0/components/hal/include/hal/
Ddac_types.h37 dac_cw_phase_t phase; /*!< Set the phase of the cosine wave generator output. */ member
/hal_espressif-3.6.0/examples/wifi/wifi_enterprise/
DREADME.md7 3. Set identity of phase 1 which is optional.
8 4. Set user name and password of phase 2 which is required in PEAP and TTLS methods.
/hal_espressif-3.6.0/examples/wifi/wifi_eap_fast/main/
DKconfig.projbuild39 Identity in phase 1 of EAP procedure.
/hal_espressif-3.6.0/components/bt/esp_ble_mesh/mesh_core/
Dcfg_srv.c2839 uint16_t idx, uint8_t phase, uint8_t status) in send_krp_status() argument
2847 net_buf_simple_add_u8(&msg, phase); in send_krp_status()
2881 uint8_t phase = 0U; in krp_set() local
2885 phase = net_buf_simple_pull_u8(buf); in krp_set()
2892 BT_DBG("idx 0x%04x transition 0x%02x", idx, phase); in krp_set()
2900 BT_DBG("%u -> %u", sub->kr_phase, phase); in krp_set()
2902 if (phase < BLE_MESH_KR_PHASE_2 || phase > BLE_MESH_KR_PHASE_3 || in krp_set()
2904 phase == BLE_MESH_KR_PHASE_2)) { in krp_set()
2905 BT_WARN("Prohibited transition %u -> %u", sub->kr_phase, phase); in krp_set()
2910 phase == BLE_MESH_KR_PHASE_2) { in krp_set()
[all …]
/hal_espressif-3.6.0/examples/wifi/wifi_enterprise/main/
DKconfig.projbuild76 Identity in phase 1 of EAP procedure.
/hal_espressif-3.6.0/examples/peripherals/twai/twai_alert_and_recovery/
DREADME.md80 …125kbits/sec, and the bit error should be triggered after the arbitration phase of each transmitte…
90 …t the triggering of the bit error is timed to occur after the arbitration phase of the transmitted…
/hal_espressif-3.6.0/docs/en/api-guides/
Dflash_psram_config.rst16 …als used to transfer data in the data phase of SPI transactions. e.g., for 4-bit-mode, the speed o…
/hal_espressif-3.6.0/components/driver/test/
Dtest_dac.c97 .phase = DAC_CW_PHASE_0,
/hal_espressif-3.6.0/examples/peripherals/mcpwm/mcpwm_sync_example/
DREADME.md68 Sync with phase:
/hal_espressif-3.6.0/examples/peripherals/mcpwm/mcpwm_bldc_hall_control/
DREADME.md17 2. A three-phase gate driver, this example uses [IR2136](https://www.infineon.com/cms/en/product/po…
/hal_espressif-3.6.0/components/bt/esp_ble_mesh/mesh_core/include/
Dcfg_cli.h246 uint8_t phase; member
/hal_espressif-3.6.0/components/bt/esp_ble_mesh/api/models/include/
Desp_ble_mesh_config_model_api.h557 uint8_t phase; /*!< Key Refresh Phase state */ member

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