Searched refs:ns (Results 1 – 11 of 11) sorted by relevance
| /hal_espressif-3.6.0/components/nvs_flash/src/ |
| D | nvs_storage.cpp | 403 uint8_t ns; in createOrOpenNamespace() local
404 for (ns = 1; ns < 255; ++ns) { in createOrOpenNamespace()
405 if (mNamespaceUsage.get(ns) == false) { in createOrOpenNamespace()
410 if (ns == 255) { in createOrOpenNamespace()
414 auto err = writeItem(Page::NS_INDEX, ItemType::U8, nsName, &ns, sizeof(ns)); in createOrOpenNamespace()
418 mNamespaceUsage.set(ns, true); in createOrOpenNamespace()
419 nsIndex = ns; in createOrOpenNamespace()
426 entry->mIndex = ns; in createOrOpenNamespace()
|
| /hal_espressif-3.6.0/docs/_static/diagrams/spi/ |
| D | spi_master_freq_tv.plt | 3 set xlabel "Input delay (ns)"
|
| /hal_espressif-3.6.0/docs/en/api-reference/peripherals/ |
| D | spi_slave.rst | 176 | | Output delay of MISO (ns) | Freq. limit (MHz) |
185 2. The clock uncertainty between Host and Device (12.5ns) is included.
206 … sampling is 68.75 ns and no longer a half of an SPI clock cycle. If the GPIO matrix is used, the …
|
| D | spi_master.rst | 527 … is so fast that the input delay is shorter than an APB clock cycle - 12.5 ns - the maximum freque…
555 | Device | Input delay (ns) |
566 *Freq limit [MHz] = 80 / (floor(MISO delay[ns]/12.5) + 1)*
575 | Master | Input delay (ns) | MISO path delay (ns) | Freq. limit (MHz) |
578 + (0ns) +------------------+----------------------+-------------------+
584 + (25ns) +------------------+----------------------+-------------------+
|
| D | pcnt.rst | 58 …y pulses, the pulse duration should be longer than one APB_CLK cycle (12.5 ns). The pulses are sam…
|
| /hal_espressif-3.6.0/docs/zh_CN/api-guides/ |
| D | app_trace.rst | 331 …RGET_NAME} 内部的循环计数器生成时间戳，其最大的工作频率是 240 MHz（时间戳粒度大约为 4 ns）。在双核模式下，使用工作在 40 MHz 的外部定时器，因此时间戳粒度为 25 n…
|
| D | wifi.rst | 1636 …- 对于 STBC 数据包，每个空时流都提供了 CSI，不会出现 CSD（循环移位延迟）。由于附加链上的每一次循环移位为 -200 ns，因为子载波 0 中没有信道频率响应，在 HT-LTF 和 …
|
| /hal_espressif-3.6.0/components/fatfs/src/ |
| D | ff.c | 1989 BYTE ns[8], c; local
2015 ns[i--] = c;
2018 ns[i] = '~';
2028 dst[j++] = (i < 8) ? ns[i++] : ' ';
3032 BYTE ns; local
3071 ns = dp->fn[NSFLAG];
3074 if (FF_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */
3075 if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */
3079 if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */
3084 if (ns & NS_LAST) break; /* Last segment matched. Function completed. */
|
| /hal_espressif-3.6.0/examples/ethernet/enc28j60/ |
| D | README.md | 96 4. CS Hold Time needs to be configured to be at least 210 ns to properly read MAC and MII registers…
|
| /hal_espressif-3.6.0/docs/en/api-guides/ |
| D | app_trace.rst | 331 … maximum 240 Mhz (~4 ns granularity). In dual-core mode external timer working at 40 Mhz is used, …
|
| D | wifi.rst | 1832 … shift delay). As each cyclic shift on the additional chains shall be -200 ns, only the CSD angle …
|
