1 // Copyright 2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <string.h>
15 #include <stdlib.h>
16 #include <sys/cdefs.h>
17 #include "esp_log.h"
18 #include "esp_check.h"
19 #include "esp_eth.h"
20 #include "eth_phy_regs_struct.h"
21 #include "freertos/FreeRTOS.h"
22 #include "freertos/task.h"
23 #include "driver/gpio.h"
24 #include "esp_rom_gpio.h"
25 #include "esp_rom_sys.h"
26
27 static const char *TAG = "dm9051.phy";
28
29 /***************Vendor Specific Register***************/
30
31 /**
32 * @brief DSCR(DAVICOM Specified Configuration Register)
33 *
34 */
35 typedef union {
36 struct {
37 uint32_t reserved1 : 1; /* Reserved */
38 uint32_t sleep : 1; /* Set 1 to enable PHY into sleep mode */
39 uint32_t mfpsc : 1; /* MII frame preamble suppression control bit */
40 uint32_t smrst : 1; /* Set 1 to reset all state machines of PHY */
41 uint32_t rpdctr_en : 1; /* Set 1 to enable automatic reduced power down */
42 uint32_t reserved2 : 2; /* Reserved */
43 uint32_t flink100 : 1; /* Force Good Link in 100Mbps */
44 uint32_t reserved3 : 2; /* Reserved */
45 uint32_t tx_fx : 1; /* 100BASE-TX or FX Mode Control */
46 uint32_t reserved4 : 1; /* Reserved */
47 uint32_t bp_adpok : 1; /* BYPASS ADPOK */
48 uint32_t bp_align : 1; /* Bypass Symbol Alignment Function */
49 uint32_t bp_scr : 1; /* Bypass Scrambler/Descrambler Function */
50 uint32_t bp_4b5b : 1; /* Bypass 4B5B Encoding and 5B4B Decoding */
51 };
52 uint32_t val;
53 } dscr_reg_t;
54 #define ETH_PHY_DSCR_REG_ADDR (0x10)
55
56 /**
57 * @brief DSCSR(DAVICOM Specified Configuration and Status Register)
58 *
59 */
60 typedef union {
61 struct {
62 uint32_t anmb : 4; /* Auto-Negotiation Monitor Bits */
63 uint32_t phy_addr : 5; /* PHY Address */
64 uint32_t reserved : 3; /* Reserved */
65 uint32_t hdx10 : 1; /* 10M Half-Duplex Operation Mode */
66 uint32_t fdx10 : 1; /* 10M Full-Duplex Operation Mode */
67 uint32_t hdx100 : 1; /* 100M Half-Duplex Operation Mode */
68 uint32_t fdx100 : 1; /* 100M Full-Duplex Operation Mode */
69 };
70 uint32_t val;
71 } dscsr_reg_t;
72 #define ETH_PHY_DSCSR_REG_ADDR (0x11)
73
74 typedef struct {
75 esp_eth_phy_t parent;
76 esp_eth_mediator_t *eth;
77 int addr;
78 uint32_t reset_timeout_ms;
79 uint32_t autonego_timeout_ms;
80 eth_link_t link_status;
81 int reset_gpio_num;
82 } phy_dm9051_t;
83
dm9051_update_link_duplex_speed(phy_dm9051_t * dm9051)84 static esp_err_t dm9051_update_link_duplex_speed(phy_dm9051_t *dm9051)
85 {
86 esp_err_t ret = ESP_OK;
87 esp_eth_mediator_t *eth = dm9051->eth;
88 eth_speed_t speed = ETH_SPEED_10M;
89 eth_duplex_t duplex = ETH_DUPLEX_HALF;
90 uint32_t peer_pause_ability = false;
91 bmsr_reg_t bmsr;
92 dscsr_reg_t dscsr;
93 anlpar_reg_t anlpar;
94 // BMSR is a latch low register
95 // after power up, the first latched value must be 0, which means down
96 // to speed up power up link speed, double read this register as a workaround
97 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
98 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
99 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
100 eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
101 /* check if link status changed */
102 if (dm9051->link_status != link) {
103 /* when link up, read negotiation result */
104 if (link == ETH_LINK_UP) {
105 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_DSCSR_REG_ADDR, &(dscsr.val)), err, TAG, "read DSCSR failed");
106 if (dscsr.fdx100 || dscsr.hdx100) {
107 speed = ETH_SPEED_100M;
108 } else {
109 speed = ETH_SPEED_10M;
110 }
111 if (dscsr.fdx100 || dscsr.fdx10) {
112 duplex = ETH_DUPLEX_FULL;
113 } else {
114 duplex = ETH_DUPLEX_HALF;
115 }
116 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
117 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
118 /* if we're in duplex mode, and peer has the flow control ability */
119 if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
120 peer_pause_ability = 1;
121 } else {
122 peer_pause_ability = 0;
123 }
124 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
125 }
126 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
127 dm9051->link_status = link;
128 }
129 return ESP_OK;
130 err:
131 return ret;
132 }
133
dm9051_set_mediator(esp_eth_phy_t * phy,esp_eth_mediator_t * eth)134 static esp_err_t dm9051_set_mediator(esp_eth_phy_t *phy, esp_eth_mediator_t *eth)
135 {
136 esp_err_t ret = ESP_OK;
137 ESP_GOTO_ON_FALSE(eth, ESP_ERR_INVALID_ARG, err, TAG, "can't set mediator to null");
138 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
139 dm9051->eth = eth;
140 return ESP_OK;
141 err:
142 return ret;
143 }
144
dm9051_get_link(esp_eth_phy_t * phy)145 static esp_err_t dm9051_get_link(esp_eth_phy_t *phy)
146 {
147 esp_err_t ret = ESP_OK;
148 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
149 /* Updata information about link, speed, duplex */
150 ESP_GOTO_ON_ERROR(dm9051_update_link_duplex_speed(dm9051), err, TAG, "update link duplex speed failed");
151 return ESP_OK;
152 err:
153 return ret;
154 }
155
dm9051_reset(esp_eth_phy_t * phy)156 static esp_err_t dm9051_reset(esp_eth_phy_t *phy)
157 {
158 esp_err_t ret = ESP_OK;
159 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
160 dm9051->link_status = ETH_LINK_DOWN;
161 esp_eth_mediator_t *eth = dm9051->eth;
162 dscr_reg_t dscr;
163 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_DSCR_REG_ADDR, &(dscr.val)), err, TAG, "read DSCR failed");
164 dscr.smrst = 1;
165 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dm9051->addr, ETH_PHY_DSCR_REG_ADDR, dscr.val), err, TAG, "write DSCR failed");
166 bmcr_reg_t bmcr = {.reset = 1};
167 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
168 /* Wait for reset complete */
169 uint32_t to = 0;
170 for (to = 0; to < dm9051->reset_timeout_ms / 10; to++) {
171 vTaskDelay(pdMS_TO_TICKS(10));
172 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
173 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_DSCR_REG_ADDR, &(dscr.val)), err, TAG, "read DSCR failed");
174 if (!bmcr.reset && !dscr.smrst) {
175 break;
176 }
177 }
178 ESP_GOTO_ON_FALSE(to < dm9051->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "PHY reset timeout");
179 return ESP_OK;
180 err:
181 return ret;
182 }
183
dm9051_reset_hw(esp_eth_phy_t * phy)184 static esp_err_t dm9051_reset_hw(esp_eth_phy_t *phy)
185 {
186 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
187 // set reset_gpio_num minus zero can skip hardware reset phy chip
188 if (dm9051->reset_gpio_num >= 0) {
189 esp_rom_gpio_pad_select_gpio(dm9051->reset_gpio_num);
190 gpio_set_direction(dm9051->reset_gpio_num, GPIO_MODE_OUTPUT);
191 gpio_set_level(dm9051->reset_gpio_num, 0);
192 esp_rom_delay_us(100); // insert min input assert time
193 gpio_set_level(dm9051->reset_gpio_num, 1);
194 }
195 return ESP_OK;
196 }
197
198 /**
199 * @note This function is responsible for restarting a new auto-negotiation,
200 * the result of negotiation won't be relected to uppler layers.
201 * Instead, the negotiation result is fetched by linker timer, see `dm9051_get_link()`
202 */
dm9051_negotiate(esp_eth_phy_t * phy)203 static esp_err_t dm9051_negotiate(esp_eth_phy_t *phy)
204 {
205 esp_err_t ret = ESP_OK;
206 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
207 esp_eth_mediator_t *eth = dm9051->eth;
208 /* in case any link status has changed, let's assume we're in link down status */
209 dm9051->link_status = ETH_LINK_DOWN;
210 /* Start auto negotiation */
211 bmcr_reg_t bmcr = {
212 .speed_select = 1, /* 100Mbps */
213 .duplex_mode = 1, /* Full Duplex */
214 .en_auto_nego = 1, /* Auto Negotiation */
215 .restart_auto_nego = 1 /* Restart Auto Negotiation */
216 };
217 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
218 /* Wait for auto negotiation complete */
219 bmsr_reg_t bmsr;
220 dscsr_reg_t dscsr;
221 uint32_t to = 0;
222 for (to = 0; to < dm9051->autonego_timeout_ms / 100; to++) {
223 vTaskDelay(pdMS_TO_TICKS(100));
224 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
225 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_DSCSR_REG_ADDR, &(dscsr.val)), err, TAG, "read DSCSR failed");
226 if (bmsr.auto_nego_complete && dscsr.anmb & 0x08) {
227 break;
228 }
229 }
230 if ((to >= dm9051->autonego_timeout_ms / 100) && (dm9051->link_status == ETH_LINK_UP)) {
231 ESP_LOGW(TAG, "Ethernet PHY auto negotiation timeout");
232 }
233 return ESP_OK;
234 err:
235 return ret;
236 }
237
dm9051_pwrctl(esp_eth_phy_t * phy,bool enable)238 static esp_err_t dm9051_pwrctl(esp_eth_phy_t *phy, bool enable)
239 {
240 esp_err_t ret = ESP_OK;
241 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
242 esp_eth_mediator_t *eth = dm9051->eth;
243 bmcr_reg_t bmcr;
244 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
245 if (!enable) {
246 /* Enable IEEE Power Down Mode */
247 bmcr.power_down = 1;
248 } else {
249 /* Disable IEEE Power Down Mode */
250 bmcr.power_down = 0;
251 }
252 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
253 if (!enable) {
254 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
255 ESP_GOTO_ON_FALSE(bmcr.power_down == 1, ESP_FAIL, err, TAG, "power down failed");
256 } else {
257 /* wait for power up complete */
258 uint32_t to = 0;
259 for (to = 0; to < dm9051->reset_timeout_ms / 10; to++) {
260 vTaskDelay(pdMS_TO_TICKS(10));
261 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
262 if (bmcr.power_down == 0) {
263 break;
264 }
265 }
266 ESP_GOTO_ON_FALSE(to < dm9051->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "power up timeout");
267 }
268 return ESP_OK;
269 err:
270 return ret;
271 }
272
dm9051_set_addr(esp_eth_phy_t * phy,uint32_t addr)273 static esp_err_t dm9051_set_addr(esp_eth_phy_t *phy, uint32_t addr)
274 {
275 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
276 dm9051->addr = addr;
277 return ESP_OK;
278 }
279
dm9051_get_addr(esp_eth_phy_t * phy,uint32_t * addr)280 static esp_err_t dm9051_get_addr(esp_eth_phy_t *phy, uint32_t *addr)
281 {
282 esp_err_t ret = ESP_OK;
283 ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "addr can't be null");
284 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
285 *addr = dm9051->addr;
286 return ESP_OK;
287 err:
288 return ret;
289 }
290
dm9051_del(esp_eth_phy_t * phy)291 static esp_err_t dm9051_del(esp_eth_phy_t *phy)
292 {
293 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
294 free(dm9051);
295 return ESP_OK;
296 }
297
dm9051_advertise_pause_ability(esp_eth_phy_t * phy,uint32_t ability)298 static esp_err_t dm9051_advertise_pause_ability(esp_eth_phy_t *phy, uint32_t ability)
299 {
300 esp_err_t ret = ESP_OK;
301 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
302 esp_eth_mediator_t *eth = dm9051->eth;
303 /* Set PAUSE function ability */
304 anar_reg_t anar;
305 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_ANAR_REG_ADDR, &(anar.val)), err, TAG, "read ANAR failed");
306 if (ability) {
307 anar.asymmetric_pause = 1;
308 anar.symmetric_pause = 1;
309 } else {
310 anar.asymmetric_pause = 0;
311 anar.symmetric_pause = 0;
312 }
313 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dm9051->addr, ETH_PHY_ANAR_REG_ADDR, anar.val), err, TAG, "write ANAR failed");
314 return ESP_OK;
315 err:
316 return ret;
317 }
318
dm9051_loopback(esp_eth_phy_t * phy,bool enable)319 static esp_err_t dm9051_loopback(esp_eth_phy_t *phy, bool enable)
320 {
321 esp_err_t ret = ESP_OK;
322 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
323 esp_eth_mediator_t *eth = dm9051->eth;
324 /* Set Loopback function */
325 bmcr_reg_t bmcr;
326 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
327 if (enable) {
328 bmcr.en_loopback = 1;
329 } else {
330 bmcr.en_loopback = 0;
331 }
332 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dm9051->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
333 return ESP_OK;
334 err:
335 return ret;
336 }
337
dm9051_init(esp_eth_phy_t * phy)338 static esp_err_t dm9051_init(esp_eth_phy_t *phy)
339 {
340 esp_err_t ret = ESP_OK;
341 phy_dm9051_t *dm9051 = __containerof(phy, phy_dm9051_t, parent);
342 esp_eth_mediator_t *eth = dm9051->eth;
343 // Detect PHY address
344 if (dm9051->addr == ESP_ETH_PHY_ADDR_AUTO) {
345 ESP_GOTO_ON_ERROR(esp_eth_detect_phy_addr(eth, &dm9051->addr), err, TAG, "Detect PHY address failed");
346 }
347 /* Power on Ethernet PHY */
348 ESP_GOTO_ON_ERROR(dm9051_pwrctl(phy, true), err, TAG, "power control failed");
349 /* Reset Ethernet PHY */
350 ESP_GOTO_ON_ERROR(dm9051_reset(phy), err, TAG, "reset failed");
351 /* Check PHY ID */
352 phyidr1_reg_t id1;
353 phyidr2_reg_t id2;
354 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_IDR1_REG_ADDR, &(id1.val)), err, TAG, "read ID1 failed");
355 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dm9051->addr, ETH_PHY_IDR2_REG_ADDR, &(id2.val)), err, TAG, "read ID2 failed");
356 ESP_GOTO_ON_FALSE(id1.oui_msb == 0x0181 && id2.oui_lsb == 0x2E && id2.vendor_model == 0x0A, ESP_FAIL, err, TAG, "wrong chip ID");
357 return ESP_OK;
358 err:
359 return ret;
360 }
361
dm9051_deinit(esp_eth_phy_t * phy)362 static esp_err_t dm9051_deinit(esp_eth_phy_t *phy)
363 {
364 esp_err_t ret = ESP_OK;
365 /* Power off Ethernet PHY */
366 ESP_GOTO_ON_ERROR(dm9051_pwrctl(phy, false), err, TAG, "power control failed");
367 return ESP_OK;
368 err:
369 return ret;
370 }
371
esp_eth_phy_new_dm9051(const eth_phy_config_t * config)372 esp_eth_phy_t *esp_eth_phy_new_dm9051(const eth_phy_config_t *config)
373 {
374 esp_eth_phy_t *ret = NULL;
375 ESP_GOTO_ON_FALSE(config, NULL, err, TAG, "can't set phy config to null");
376 phy_dm9051_t *dm9051 = calloc(1, sizeof(phy_dm9051_t));
377 ESP_GOTO_ON_FALSE(dm9051, NULL, err, TAG, "calloc dm9051 failed");
378 dm9051->addr = config->phy_addr;
379 dm9051->reset_timeout_ms = config->reset_timeout_ms;
380 dm9051->reset_gpio_num = config->reset_gpio_num;
381 dm9051->link_status = ETH_LINK_DOWN;
382 dm9051->autonego_timeout_ms = config->autonego_timeout_ms;
383 dm9051->parent.reset = dm9051_reset;
384 dm9051->parent.reset_hw = dm9051_reset_hw;
385 dm9051->parent.init = dm9051_init;
386 dm9051->parent.deinit = dm9051_deinit;
387 dm9051->parent.set_mediator = dm9051_set_mediator;
388 dm9051->parent.negotiate = dm9051_negotiate;
389 dm9051->parent.get_link = dm9051_get_link;
390 dm9051->parent.pwrctl = dm9051_pwrctl;
391 dm9051->parent.get_addr = dm9051_get_addr;
392 dm9051->parent.set_addr = dm9051_set_addr;
393 dm9051->parent.advertise_pause_ability = dm9051_advertise_pause_ability;
394 dm9051->parent.loopback = dm9051_loopback;
395 dm9051->parent.del = dm9051_del;
396 return &(dm9051->parent);
397 err:
398 return ret;
399 }
400
