interrupts (reference) in projects: hal_espressif-3.6.0

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Searched refs:interrupts (Results 1 – 25 of 66) sorted by relevance

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/hal_espressif-3.6.0/docs/en/api-reference/system/
D	intr_alloc.rst	9 …T_NAME} has two cores, with 32 interrupts each. Each interrupt has a certain priority level, most … 13 …RGET_NAME} has one core, with 32 interrupts. Each interrupt has a certain priority level, most (bu… 17 …GET_NAME} has two cores, with 32 interrupts. Each interrupt has a certain priority level, most (bu… 21 …The {IDF_TARGET_NAME} has one core, with 31 interrupts. Each interrupt has a programmable priority… 23 Because there are more interrupt sources than interrupts, sometimes it makes sense to share an inte… 30 … code presents two different types of interrupts, handled differently: shared interrupts and non-s… 31 ones are non-shared interrupts: a separate interrupt is allocated per :cpp:func:`esp_intr_alloc` ca… 32 … it, with only one ISR that will get called. On the other hand, shared interrupts can have multipl… 34 interrupts should check the interrupt status of the peripheral they service in order to check if an… 36 Non-shared interrupts can be either level- or edge-triggered. Shared interrupts can [all …]
D	ipc.rst	54 - The calling CPU will disable interrupts of level 3 and lower 55 …L`, during the execution IPC ISR callback, the target CPU will disable interrupts of level 5 and l… 107 …rget CPU. The calling CPU disables interrupts of level 3 and lower while the target CPU will busy-…
/hal_espressif-3.6.0/components/hal/
D	twai_hal_iram.c	`35 uint32_t interrupts = twai_ll_get_and_clear_intrs(hal_ctx->dev); local 42 if (interrupts & TWAI_LL_INTR_EI) { 68 if (interrupts & TWAI_LL_INTR_RI) { 73 …if ((interrupts & TWAI_LL_INTR_TI \|\| hal_ctx->state_flags & TWAI_HAL_STATE_FLAG_TX_BUFF_OCCUPIED) … 75 if (interrupts & TWAI_LL_INTR_TI) { 81 if (interrupts & TWAI_LL_INTR_EPI) { 91 if (interrupts & TWAI_LL_INTR_BEI) { 95 if (interrupts & TWAI_LL_INTR_ALI) {`
/hal_espressif-3.6.0/docs/en/api-guides/
D	hlinterrupts.rst	7 …interrupts, divided over 7 levels (levels 1 to 7, with 7 being an NMI), plus an assortment of exce… 17 1 N/A Exception and level 0 interrupts. Handled by ESP-IDF 18 2-3 N/A Medium level interrupts. Handled by ESP-IDF 38 1 N/A Exception and level 0 interrupts. Handled by ESP-IDF 39 2-3 N/A Medium level interrupts. Handled by ESP-IDF 63 …- Do not call C code from a high-level interrupt; as these interrupts are run from a critical sect… 87 …- High-level interrupts can be routed and handled using :cpp:func:`esp_intr_alloc` and associated … 90 …- In theory, medium priority interrupts could also be handled in this way. ESP-IDF does not suppor…
D	freertos-smp.rst	40 - has multiple cores running independently. Each core has its own register file, interrupts, and in… 64 - Cross-core interrupts that allow one CPU to trigger and interrupt on another CPU. This allows cor… 270 … periodic interrupt and independently run the tick interrupt. The tick interrupts on each core are… 293 - Task switching is disabled but interrupts are left enabled. 301 - Task switching is disabled only on the current core but interrupts for the current core are left … 313 Vanilla FreeRTOS allows interrupts to be disabled and enabled by calling :c:macro:`taskDISABLE_INTE… 315 ESP-IDF FreeRTOS provides the same API, however interrupts will only disabled or enabled on the cur… 318 …interrupts is a valid method of achieve mutual exclusion in Vanilla FreeRTOS (and single core syst… 336 Vanilla FreeRTOS implements critical sections by disabling interrupts, This prevents preemptive con… 338 - ``taskENTER_CRITICAL()`` enters a critical section by disabling interrupts [all …]
/hal_espressif-3.6.0/docs/zh_CN/api-reference/peripherals/
D	timer.rst	31 * :ref:`timer-api-interrupts`- 如何使用中断提供的回调函数。 85 * 如果先前已配置，此时将触发中断。有关如何配置中断，请参见 :ref:`timer-api-interrupts`。 96 .. _timer-api-interrupts:
/hal_espressif-3.6.0/components/freertos/port/xtensa/
D	readme_xtensa.txt	320 for handling interrupts. Thus, it is no longer necessary for each task to 321 reserve space on its stack to handle interrupts. The size of the interrupt 379 cycles between interrupts to process them. 400 XT_USE_SWPRI Enable software prioritization of interrupts. 401 Enabling this will prioritize interrupts with 404 low and medium priority interrupts that can be 522 classes of exceptions and interrupts. Being a configurable architecture, 537 The handlers provided for low and medium priority interrupts are just 545 into which the application adds code to service specific interrupts. 549 This FreeRTOS port supports strict priority-based nesting of interrupts. [all …]
/hal_espressif-3.6.0/docs/en/api-reference/peripherals/
D	uart.rst	30 5. :ref:`uart-api-using-interrupts` - Triggering interrupts on specific communication events 218 .. _uart-api-using-interrupts: 223 …interrupts that can be generated following specific UART states or detected errors. The full list … 225 …ll not automatically work in this case - it is necessary to handle the interrupts directly in the … 227 The API provides a convenient way to handle specific interrupts discussed in this document by wrapp… 231 …characters, or on a timeout of sending or receiving data. To use these interrupts, do the followin… 234 …- Enable the interrupts using the functions :cpp:func:`uart_enable_tx_intr` and :cpp:func:`uart_en… 235 …- Disable these interrupts using the corresponding functions :cpp:func:`uart_disable_tx_intr` or :… 270 …on feature allows handling collisions when their interrupts are activated and triggered. The inter… 377 - Reporting various communication events, using pattern detection interrupts.
D	timer.rst	24 * :ref:`timer-api-interrupts`- explains how to use interrupt callbacks. 78 …d if previously configured. See Section :ref:`timer-api-interrupts` on how to configure interrupts. 89 .. _timer-api-interrupts: 97 For more information on how to use interrupts, please see the application example below.
D	touch_pad.rst	41 - Setting up interrupts to report touch detection 50 …removes the information about which pads have been touched before, if any, and disables interrupts. 142 Hardware touch detection can also be wired to interrupts. This is described in the next section. 144 … To resolve this issue, instead of using hardware detection / provided interrupts, implement measu… 155 …In the next step, configure how interrupts are triggered. They can be triggered below or above the… 162 When interrupts are operational, you can obtain the information from which particular pad an interr… 175 …If touch pad interrupts are used to wake up the chip from a sleep mode, you can select a certain c…
D	pcnt.rst	21 * :ref:`pcnt-api-using-interrupts` - presents how to trigger interrupts on specific states of the c… 36 …(minimum / maximum) that are used to establish watchpoints and trigger interrupts when the pulse c… 73 .. _pcnt-api-using-interrupts:
D	sdio_slave.rst	119 - Interrupts: the esp32 slave support interrupts in two directions: from host to slave (called slav… 120 and from slave to host (called host interrupts below). See more in :ref:`interrupts`. 143 There are interrupts from host to slave, and from slave to host to help communicating conveniently. 155 certain time, or call ``sdio_slave_clear_int`` to clear interrupts from host. The callback function…
/hal_espressif-3.6.0/examples/peripherals/timer_group/
D	README.md	`3 This example uses the timer group driver to generate timer interrupts at two specified alarm interv… 55 * Alarms trigger subsequent interrupts, that is tracked with messages printed on the terminal:`
/hal_espressif-3.6.0/examples/peripherals/sdio/host/main/
D	Kconfig.projbuild	`19 mandatory for interrupts. 40 registers to see whether the slave has interrupts for the host.`
/hal_espressif-3.6.0/components/soc/esp32h2/
D	CMakeLists.txt	`6 "interrupts.c"`
/hal_espressif-3.6.0/examples/system/
D	README.md	`3 Configuration and management of memory, interrupts, WDT (watchdog timer), OTA (over the air updates…`
/hal_espressif-3.6.0/components/soc/esp32c3/
D	CMakeLists.txt	`6 "interrupts.c"`
/hal_espressif-3.6.0/components/soc/esp32/
D	CMakeLists.txt	`7 "interrupts.c"`
/hal_espressif-3.6.0/components/soc/esp32s2/
D	CMakeLists.txt	`8 "interrupts.c"`
/hal_espressif-3.6.0/components/soc/esp32s3/
D	CMakeLists.txt	`8 "interrupts.c"`
/hal_espressif-3.6.0/docs/en/api-reference/protocols/
D	esp_sdio_slave_protocol.rst	`131 - 0x0DC (INT_ENA): mask bits for interrupts from slave to host. 172 SDIO interrupts are "level sensitive". For host interrupts, the slave sends an interrupt by pulling… 176 For slave interrupts, the host sends a transfer to write the SLAVE_INT register. Once a bit is set …`
D	esp_serial_slave_link.rst	135 1. Call :cpp:func:`essl_get_intr_ena` to know which events will trigger the interrupts to the maste… 137 2. Call :cpp:func:`essl_set_intr_ena` to set the events that will trigger interrupts to the master.
/hal_espressif-3.6.0/components/log/
D	README.rst	51 …`. These versions are used in some places where logging may occur with interrupts disabled or with… 55 …Inside critical sections interrupts are disabled so it's only possible to use ``ESP_DRAM_LOGx`` (p…
/hal_espressif-3.6.0/examples/peripherals/sdio/
D	README.md	`11 peripheral, providing 8 interrupts, 52 8-bit R/W registers, an input FIFO and 17 interrupts to the host. Then the host start sending data to the slave FIFO`
/hal_espressif-3.6.0/docs/en/api-reference/storage/
D	sdmmc.rst	94 …interrupts can be enabled by the application using the function :cpp:func:`sdmmc_io_enable_int`. W…

12 3

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
babblesim_base-3.6.0-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
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babblesim_ext_2G4_modem_BLE_simple-3.7.0
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bsim-3.4.0
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cmsis-2.7.6
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cmsis-3.5.0
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cmsis-dsp-3.5.0
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edtt-3.7.0
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