1 // Copyright 2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <string.h>
15 #include <stdlib.h>
16 #include <sys/cdefs.h>
17 #include "esp_log.h"
18 #include "esp_check.h"
19 #include "esp_eth.h"
20 #include "eth_phy_regs_struct.h"
21 #include "freertos/FreeRTOS.h"
22 #include "freertos/task.h"
23 #include "driver/gpio.h"
24 #include "esp_rom_gpio.h"
25 #include "esp_rom_sys.h"
26
27 static const char *TAG = "dp83848";
28
29 /***************Vendor Specific Register***************/
30
31 /**
32 * @brief PHYSTS(PHY Status Register)
33 *
34 */
35 typedef union {
36 struct {
37 uint32_t link_status : 1; /* Link Status */
38 uint32_t speed_status : 1; /* Speed Status */
39 uint32_t duplex_status : 1; /* Duplex Status */
40 uint32_t loopback_status : 1; /* MII Loopback */
41 uint32_t auto_nego_complete : 1; /* Auto-Negotiation Complete */
42 uint32_t jabber_detect : 1; /* Jabber Detect */
43 uint32_t remote_fault : 1; /* Remote Fault */
44 uint32_t mii_interrupt : 1; /* MII Interrupt Pending */
45 uint32_t page_received : 1; /* Link Code Word Page Received */
46 uint32_t descrambler_lock : 1; /* Descrambler Lock */
47 uint32_t signal_detect : 1; /* Signal Detect */
48 uint32_t false_carrier_sense_latch : 1; /* False Carrier Sense Latch */
49 uint32_t polarity_status : 1; /* Polarity Status */
50 uint32_t receive_error_latch : 1; /* Receive Error Latch */
51 uint32_t mdix_mode : 1; /* MDI-X mode reported by auto-negotiation */
52 uint32_t reserved : 1; /* Reserved */
53 };
54 uint32_t val;
55 } physts_reg_t;
56 #define ETH_PHY_STS_REG_ADDR (0x10)
57
58 /**
59 * @brief PHYCR(PHY Control Register)
60 *
61 */
62 typedef union {
63 struct {
64 uint32_t phy_addr : 5; /* PHY Address */
65 uint32_t led_cfg : 2; /* LED Configuration Modes */
66 uint32_t bypass_led_stretching : 1; /* Bypass LED Stretching */
67 uint32_t bist_start : 1; /* BIST Start */
68 uint32_t bist_status : 1; /* BIST Test Status */
69 uint32_t psr_15 : 1; /* BIST Sequence select */
70 uint32_t bist_force_error : 1; /* BIST Force Error */
71 uint32_t pause_trans_negotiate : 1; /* Pause Transmit Negotiated Status */
72 uint32_t pause_receive_negotiat : 1; /* Pause Receive Negotiated Status */
73 uint32_t force_mdix : 1; /* Force MDIX */
74 uint32_t en_auto_mdix : 1; /* Auto-MDIX Enable */
75 };
76 uint32_t val;
77 } phycr_reg_t;
78 #define ETH_PHY_CR_REG_ADDR (0x19)
79
80 typedef struct {
81 esp_eth_phy_t parent;
82 esp_eth_mediator_t *eth;
83 int addr;
84 uint32_t reset_timeout_ms;
85 uint32_t autonego_timeout_ms;
86 eth_link_t link_status;
87 int reset_gpio_num;
88 } phy_dp83848_t;
89
dp83848_update_link_duplex_speed(phy_dp83848_t * dp83848)90 static esp_err_t dp83848_update_link_duplex_speed(phy_dp83848_t *dp83848)
91 {
92 esp_err_t ret = ESP_OK;
93 esp_eth_mediator_t *eth = dp83848->eth;
94 eth_speed_t speed = ETH_SPEED_10M;
95 eth_duplex_t duplex = ETH_DUPLEX_HALF;
96 uint32_t peer_pause_ability = false;
97 anlpar_reg_t anlpar;
98 physts_reg_t physts;
99 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
100 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_STS_REG_ADDR, &(physts.val)), err, TAG, "read PHYSTS failed");
101 eth_link_t link = physts.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
102 /* check if link status changed */
103 if (dp83848->link_status != link) {
104 /* when link up, read negotiation result */
105 if (link == ETH_LINK_UP) {
106 if (physts.speed_status) {
107 speed = ETH_SPEED_10M;
108 } else {
109 speed = ETH_SPEED_100M;
110 }
111 if (physts.duplex_status) {
112 duplex = ETH_DUPLEX_FULL;
113 } else {
114 duplex = ETH_DUPLEX_HALF;
115 }
116 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
117 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
118 /* if we're in duplex mode, and peer has the flow control ability */
119 if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
120 peer_pause_ability = 1;
121 } else {
122 peer_pause_ability = 0;
123 }
124 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
125 }
126 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
127 dp83848->link_status = link;
128 }
129 return ESP_OK;
130 err:
131 return ret;
132 }
133
dp83848_set_mediator(esp_eth_phy_t * phy,esp_eth_mediator_t * eth)134 static esp_err_t dp83848_set_mediator(esp_eth_phy_t *phy, esp_eth_mediator_t *eth)
135 {
136 esp_err_t ret = ESP_OK;
137 ESP_GOTO_ON_FALSE(eth, ESP_ERR_INVALID_ARG, err, TAG, "can't set mediator to null");
138 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
139 dp83848->eth = eth;
140 return ESP_OK;
141 err:
142 return ret;
143 }
144
dp83848_get_link(esp_eth_phy_t * phy)145 static esp_err_t dp83848_get_link(esp_eth_phy_t *phy)
146 {
147 esp_err_t ret = ESP_OK;
148 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
149 /* Updata information about link, speed, duplex */
150 ESP_GOTO_ON_ERROR(dp83848_update_link_duplex_speed(dp83848), err, TAG, "update link duplex speed failed");
151 return ESP_OK;
152 err:
153 return ret;
154 }
155
dp83848_reset(esp_eth_phy_t * phy)156 static esp_err_t dp83848_reset(esp_eth_phy_t *phy)
157 {
158 esp_err_t ret = ESP_OK;
159 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
160 dp83848->link_status = ETH_LINK_DOWN;
161 esp_eth_mediator_t *eth = dp83848->eth;
162 bmcr_reg_t bmcr = {.reset = 1};
163 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dp83848->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
164 /* Wait for reset complete */
165 uint32_t to = 0;
166 for (to = 0; to < dp83848->reset_timeout_ms / 10; to++) {
167 vTaskDelay(pdMS_TO_TICKS(10));
168 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
169 if (!bmcr.reset) {
170 break;
171 }
172 }
173 ESP_GOTO_ON_FALSE(to < dp83848->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "reset timeout");
174 return ESP_OK;
175 err:
176 return ret;
177 }
178
dp83848_reset_hw(esp_eth_phy_t * phy)179 static esp_err_t dp83848_reset_hw(esp_eth_phy_t *phy)
180 {
181 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
182 if (dp83848->reset_gpio_num >= 0) {
183 esp_rom_gpio_pad_select_gpio(dp83848->reset_gpio_num);
184 gpio_set_direction(dp83848->reset_gpio_num, GPIO_MODE_OUTPUT);
185 gpio_set_level(dp83848->reset_gpio_num, 0);
186 esp_rom_delay_us(100); // insert min input assert time
187 gpio_set_level(dp83848->reset_gpio_num, 1);
188 }
189 return ESP_OK;
190 }
191
192 /**
193 * @note This function is responsible for restarting a new auto-negotiation,
194 * the result of negotiation won't be relected to uppler layers.
195 * Instead, the negotiation result is fetched by linker timer, see `dp83848_get_link()`
196 */
dp83848_negotiate(esp_eth_phy_t * phy)197 static esp_err_t dp83848_negotiate(esp_eth_phy_t *phy)
198 {
199 esp_err_t ret = ESP_OK;
200 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
201 esp_eth_mediator_t *eth = dp83848->eth;
202 /* in case any link status has changed, let's assume we're in link down status */
203 dp83848->link_status = ETH_LINK_DOWN;
204 /* Start auto negotiation */
205 bmcr_reg_t bmcr = {
206 .speed_select = 1, /* 100Mbps */
207 .duplex_mode = 1, /* Full Duplex */
208 .en_auto_nego = 1, /* Auto Negotiation */
209 .restart_auto_nego = 1 /* Restart Auto Negotiation */
210 };
211 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dp83848->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
212 /* Wait for auto negotiation complete */
213 bmsr_reg_t bmsr;
214 physts_reg_t physts;
215 uint32_t to = 0;
216 for (to = 0; to < dp83848->autonego_timeout_ms / 100; to++) {
217 vTaskDelay(pdMS_TO_TICKS(100));
218 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
219 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_STS_REG_ADDR, &(physts.val)), err, TAG, "read PHYSTS failed");
220 if (bmsr.auto_nego_complete && physts.auto_nego_complete) {
221 break;
222 }
223 }
224 if ((to >= dp83848->autonego_timeout_ms / 100) && (dp83848->link_status == ETH_LINK_UP)) {
225 ESP_LOGW(TAG, "auto negotiation timeout");
226 }
227 return ESP_OK;
228 err:
229 return ret;
230 }
231
dp83848_pwrctl(esp_eth_phy_t * phy,bool enable)232 static esp_err_t dp83848_pwrctl(esp_eth_phy_t *phy, bool enable)
233 {
234 esp_err_t ret = ESP_OK;
235 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
236 esp_eth_mediator_t *eth = dp83848->eth;
237 bmcr_reg_t bmcr;
238 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
239 if (!enable) {
240 /* Enable IEEE Power Down Mode */
241 bmcr.power_down = 1;
242 } else {
243 /* Disable IEEE Power Down Mode */
244 bmcr.power_down = 0;
245 }
246 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dp83848->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
247 if (!enable) {
248 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
249 ESP_GOTO_ON_FALSE(bmcr.power_down == 1, ESP_FAIL, err, TAG, "power down failed");
250 } else {
251 /* wait for power up complete */
252 uint32_t to = 0;
253 for (to = 0; to < dp83848->reset_timeout_ms / 10; to++) {
254 vTaskDelay(pdMS_TO_TICKS(10));
255 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
256 if (bmcr.power_down == 0) {
257 break;
258 }
259 }
260 ESP_GOTO_ON_FALSE(to < dp83848->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "power up timeout");
261 }
262 return ESP_OK;
263 err:
264 return ret;
265 }
266
dp83848_set_addr(esp_eth_phy_t * phy,uint32_t addr)267 static esp_err_t dp83848_set_addr(esp_eth_phy_t *phy, uint32_t addr)
268 {
269 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
270 dp83848->addr = addr;
271 return ESP_OK;
272 }
273
dp83848_get_addr(esp_eth_phy_t * phy,uint32_t * addr)274 static esp_err_t dp83848_get_addr(esp_eth_phy_t *phy, uint32_t *addr)
275 {
276 esp_err_t ret = ESP_OK;
277 ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "addr can't be null");
278 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
279 *addr = dp83848->addr;
280 return ESP_OK;
281 err:
282 return ret;
283 }
284
dp83848_del(esp_eth_phy_t * phy)285 static esp_err_t dp83848_del(esp_eth_phy_t *phy)
286 {
287 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
288 free(dp83848);
289 return ESP_OK;
290 }
291
dp83848_advertise_pause_ability(esp_eth_phy_t * phy,uint32_t ability)292 static esp_err_t dp83848_advertise_pause_ability(esp_eth_phy_t *phy, uint32_t ability)
293 {
294 esp_err_t ret = ESP_OK;
295 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
296 esp_eth_mediator_t *eth = dp83848->eth;
297 /* Set PAUSE function ability */
298 anar_reg_t anar;
299 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_ANAR_REG_ADDR, &(anar.val)), err, TAG, "read ANAR failed");
300 if (ability) {
301 anar.asymmetric_pause = 1;
302 anar.symmetric_pause = 1;
303 } else {
304 anar.asymmetric_pause = 0;
305 anar.symmetric_pause = 0;
306 }
307 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dp83848->addr, ETH_PHY_ANAR_REG_ADDR, anar.val), err, TAG, "write ANAR failed");
308 return ESP_OK;
309 err:
310 return ret;
311 }
312
dp83848_loopback(esp_eth_phy_t * phy,bool enable)313 static esp_err_t dp83848_loopback(esp_eth_phy_t *phy, bool enable)
314 {
315 esp_err_t ret = ESP_OK;
316 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
317 esp_eth_mediator_t *eth = dp83848->eth;
318 /* Set Loopback function */
319 bmcr_reg_t bmcr;
320 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
321 if (enable) {
322 bmcr.en_loopback = 1;
323 } else {
324 bmcr.en_loopback = 0;
325 }
326 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, dp83848->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
327 return ESP_OK;
328 err:
329 return ret;
330 }
331
dp83848_init(esp_eth_phy_t * phy)332 static esp_err_t dp83848_init(esp_eth_phy_t *phy)
333 {
334 esp_err_t ret = ESP_OK;
335 phy_dp83848_t *dp83848 = __containerof(phy, phy_dp83848_t, parent);
336 esp_eth_mediator_t *eth = dp83848->eth;
337 // Detect PHY address
338 if (dp83848->addr == ESP_ETH_PHY_ADDR_AUTO) {
339 ESP_GOTO_ON_ERROR(esp_eth_detect_phy_addr(eth, &dp83848->addr), err, TAG, "Detect PHY address failed");
340 }
341 /* Power on Ethernet PHY */
342 ESP_GOTO_ON_ERROR(dp83848_pwrctl(phy, true), err, TAG, "power control failed");
343 /* Reset Ethernet PHY */
344 ESP_GOTO_ON_ERROR(dp83848_reset(phy), err, TAG, "reset failed");
345 /* Check PHY ID */
346 phyidr1_reg_t id1;
347 phyidr2_reg_t id2;
348 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_IDR1_REG_ADDR, &(id1.val)), err, TAG, "read ID1 failed");
349 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, dp83848->addr, ETH_PHY_IDR2_REG_ADDR, &(id2.val)), err, TAG, "read ID2 failed");
350 ESP_GOTO_ON_FALSE(id1.oui_msb == 0x2000 && id2.oui_lsb == 0x17 && id2.vendor_model == 0x09, ESP_FAIL, err, TAG, "wrong chip ID");
351 return ESP_OK;
352 err:
353 return ret;
354 }
355
dp83848_deinit(esp_eth_phy_t * phy)356 static esp_err_t dp83848_deinit(esp_eth_phy_t *phy)
357 {
358 esp_err_t ret = ESP_OK;
359 /* Power off Ethernet PHY */
360 ESP_GOTO_ON_ERROR(dp83848_pwrctl(phy, false), err, TAG, "power control failed");
361 return ESP_OK;
362 err:
363 return ret;
364 }
365
esp_eth_phy_new_dp83848(const eth_phy_config_t * config)366 esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config)
367 {
368 esp_eth_phy_t *ret = NULL;
369 ESP_GOTO_ON_FALSE(config, NULL, err, TAG, "can't set phy config to null");
370 phy_dp83848_t *dp83848 = calloc(1, sizeof(phy_dp83848_t));
371 ESP_GOTO_ON_FALSE(dp83848, NULL, err, TAG, "calloc dp83848 failed");
372 dp83848->addr = config->phy_addr;
373 dp83848->reset_timeout_ms = config->reset_timeout_ms;
374 dp83848->link_status = ETH_LINK_DOWN;
375 dp83848->reset_gpio_num = config->reset_gpio_num;
376 dp83848->autonego_timeout_ms = config->autonego_timeout_ms;
377 dp83848->parent.reset = dp83848_reset;
378 dp83848->parent.reset_hw = dp83848_reset_hw;
379 dp83848->parent.init = dp83848_init;
380 dp83848->parent.deinit = dp83848_deinit;
381 dp83848->parent.set_mediator = dp83848_set_mediator;
382 dp83848->parent.negotiate = dp83848_negotiate;
383 dp83848->parent.get_link = dp83848_get_link;
384 dp83848->parent.pwrctl = dp83848_pwrctl;
385 dp83848->parent.get_addr = dp83848_get_addr;
386 dp83848->parent.set_addr = dp83848_set_addr;
387 dp83848->parent.advertise_pause_ability = dp83848_advertise_pause_ability;
388 dp83848->parent.loopback = dp83848_loopback;
389 dp83848->parent.del = dp83848_del;
390 return &(dp83848->parent);
391 err:
392 return ret;
393 }
394
