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/hal_espressif-3.6.0/components/hal/esp32/include/hal/
Dtimer_ll.h47 static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider) in timer_ll_set_divider() argument
49 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_divider()
50 if (divider >= 65536) { in timer_ll_set_divider()
51 divider = 0; in timer_ll_set_divider()
55 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider, divider); in timer_ll_set_divider()
68 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider) in timer_ll_get_divider() argument
70 uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider); in timer_ll_get_divider()
76 *divider = d; in timer_ll_get_divider()
/hal_espressif-3.6.0/components/soc/src/esp32/
Drtc_clk.c517 uint32_t divider = 0; in rtc_clk_cpu_freq_to_config() local
526 divider = source_freq_mhz / 2; in rtc_clk_cpu_freq_to_config()
529 divider = 1; in rtc_clk_cpu_freq_to_config()
535 divider = 4; in rtc_clk_cpu_freq_to_config()
541 divider = 2; in rtc_clk_cpu_freq_to_config()
547 divider = 2; in rtc_clk_cpu_freq_to_config()
558 .div = divider, in rtc_clk_cpu_freq_to_config()
567 uint32_t divider = 0; in rtc_clk_cpu_freq_mhz_to_config() local
572 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
573 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
[all …]
/hal_espressif-3.6.0/components/hal/esp32h2/include/hal/
Dtimer_ll.h51 static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider) in timer_ll_set_divider() argument
53 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_divider()
54 if (divider >= 65536) { in timer_ll_set_divider()
55 divider = 0; in timer_ll_set_divider()
60 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); in timer_ll_set_divider()
73 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider) in timer_ll_get_divider() argument
81 *divider = d; in timer_ll_get_divider()
Dtwai_ll.h652 static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider) in twai_ll_set_clkout() argument
654 if (divider >= 2 && divider <= 490) { in twai_ll_set_clkout()
656 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
657 } else if (divider == 1) { in twai_ll_set_clkout()
/hal_espressif-3.6.0/components/hal/esp32s3/include/hal/
Dtimer_ll.h52 static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider) in timer_ll_set_divider() argument
54 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_divider()
55 if (divider >= 65536) { in timer_ll_set_divider()
56 divider = 0; in timer_ll_set_divider()
60 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tn_divider, divider); in timer_ll_set_divider()
73 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider) in timer_ll_get_divider() argument
81 *divider = d; in timer_ll_get_divider()
Dtwai_ll.h652 static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider) in twai_ll_set_clkout() argument
654 if (divider >= 2 && divider <= 490) { in twai_ll_set_clkout()
656 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
657 } else if (divider == 1) { in twai_ll_set_clkout()
/hal_espressif-3.6.0/components/hal/esp32c3/include/hal/
Dtimer_ll.h51 static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider) in timer_ll_set_divider() argument
53 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_divider()
54 if (divider >= 65536) { in timer_ll_set_divider()
55 divider = 0; in timer_ll_set_divider()
60 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); in timer_ll_set_divider()
73 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider) in timer_ll_get_divider() argument
81 *divider = d; in timer_ll_get_divider()
Dtwai_ll.h652 static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider) in twai_ll_set_clkout() argument
654 if (divider >= 2 && divider <= 490) { in twai_ll_set_clkout()
656 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
657 } else if (divider == 1) { in twai_ll_set_clkout()
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32/
Drtc_clk.c552 uint32_t divider; in rtc_clk_cpu_freq_to_config() local
561 divider = source_freq_mhz / 2; in rtc_clk_cpu_freq_to_config()
564 divider = 1; in rtc_clk_cpu_freq_to_config()
570 divider = 4; in rtc_clk_cpu_freq_to_config()
576 divider = 2; in rtc_clk_cpu_freq_to_config()
582 divider = 2; in rtc_clk_cpu_freq_to_config()
593 .div = divider, in rtc_clk_cpu_freq_to_config()
602 uint32_t divider; in rtc_clk_cpu_freq_mhz_to_config() local
607 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
608 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
[all …]
Drtc_time.c123 uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; in rtc_clk_cal() local
124 uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; in rtc_clk_cal()
/hal_espressif-3.6.0/components/driver/test/
Dtest_timer.c197 static void all_timer_set_divider(uint32_t divider) in all_timer_set_divider() argument
201 TEST_ESP_OK(timer_set_divider(tg_idx, timer_idx, divider)); in all_timer_set_divider()
302 .divider = TIMER_DIVIDER,
316 .divider = TIMER_DIVIDER,
332 .divider = TIMER_DIVIDER,
345 TEST_ASSERT_EQUAL(config.divider, get_config.divider);
372 .divider = TIMER_DIVIDER,
411 .divider = TIMER_DIVIDER,
442 .divider = TIMER_DIVIDER,
469 .divider = TIMER_DIVIDER,
[all …]
/hal_espressif-3.6.0/components/hal/esp32s2/include/hal/
Dtimer_ll.h47 static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider) in timer_ll_set_divider() argument
49 HAL_ASSERT(divider >= 2 && divider <= 65536); in timer_ll_set_divider()
50 if (divider >= 65536) { in timer_ll_set_divider()
51 divider = 0; in timer_ll_set_divider()
55 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); in timer_ll_set_divider()
68 static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider) in timer_ll_get_divider() argument
76 *divider = d; in timer_ll_get_divider()
Dtwai_ll.h652 static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider) in twai_ll_set_clkout() argument
654 if (divider >= 2 && divider <= 490) { in twai_ll_set_clkout()
656 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
657 } else if (divider == 1) { in twai_ll_set_clkout()
/hal_espressif-3.6.0/examples/system/app_trace_to_host/main/
DKconfig.projbuild4 bool "Set custom RTC 8 MHz clock divider to lower CW frequency (CHECK HELP FIRST)"
7 Set custom / non standard divider for RTC 8 MHz clock.
11 WARNINIG: setting non standard divider for the RTC 8 MHz clock
17 DO NOT use this option / change default RTC 8 MHz clock divider
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32s2/
Drtc_clk.c302 uint32_t divider; in rtc_clk_cpu_freq_mhz_to_config() local
307 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
308 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
320 divider = 6; in rtc_clk_cpu_freq_mhz_to_config()
325 divider = 3; in rtc_clk_cpu_freq_mhz_to_config()
330 divider = 2; in rtc_clk_cpu_freq_mhz_to_config()
337 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
Drtc_time.c132 uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; in rtc_clk_xtal_to_slowclk() local
133 uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; in rtc_clk_xtal_to_slowclk()
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32s3/
Drtc_clk.c322 uint32_t divider; in rtc_clk_cpu_freq_mhz_to_config() local
327 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
328 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
340 divider = 6; in rtc_clk_cpu_freq_mhz_to_config()
345 divider = 3; in rtc_clk_cpu_freq_mhz_to_config()
350 divider = 2; in rtc_clk_cpu_freq_mhz_to_config()
357 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
Drtc_time.c139 uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; in rtc_clk_cal() local
140 uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; in rtc_clk_cal()
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32c3/
Drtc_clk.c295 uint32_t divider; in rtc_clk_cpu_freq_mhz_to_config() local
300 divider = xtal_freq / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
301 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */ in rtc_clk_cpu_freq_mhz_to_config()
313 divider = 6; in rtc_clk_cpu_freq_mhz_to_config()
318 divider = 3; in rtc_clk_cpu_freq_mhz_to_config()
325 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
Drtc_time.c133 uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; in rtc_clk_cal() local
134 uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; in rtc_clk_cal()
/hal_espressif-3.6.0/components/hal/include/hal/
Dtimer_hal.h79 #define timer_hal_set_divider(hal, divider) timer_ll_set_divider((hal)->dev, (hal)->idx, divider) argument
89 #define timer_hal_get_divider(hal, divider) timer_ll_get_divider((hal)->dev, (hal)->idx, divider) argument
/hal_espressif-3.6.0/components/bt/esp_ble_mesh/mesh_common/include/
Dmesh_util.h97 #define ceiling_fraction(numerator, divider) \ argument
98 (((numerator) + ((divider) - 1)) / (divider))
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32h2/
Drtc_time.c125 uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles; in rtc_clk_cal() local
126 uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider; in rtc_clk_cal()
Drtc_clk.c208 uint32_t divider; in rtc_clk_cpu_freq_mhz_to_config() local
213 divider = RTC_PLL_FREQ_96M / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
218 divider = source_freq_mhz / freq_mhz; in rtc_clk_cpu_freq_mhz_to_config()
223 .div = divider, in rtc_clk_cpu_freq_mhz_to_config()
/hal_espressif-3.6.0/components/driver/
Dtimer.c139 esp_err_t timer_set_divider(timer_group_t group_num, timer_idx_t timer_num, uint32_t divider) in timer_set_divider() argument
143 …ESP_RETURN_ON_FALSE(divider > 1 && divider < 65537, ESP_ERR_INVALID_ARG, TIMER_TAG, DIVIDER_RANGE… in timer_set_divider()
146 timer_hal_set_divider(&(p_timer_obj[group_num][timer_num]->hal), divider); in timer_set_divider()
273 …ESP_RETURN_ON_FALSE(config->divider > 1 && config->divider < 65537, ESP_ERR_INVALID_ARG, TIMER_TAG… in timer_init()
290 timer_hal_set_divider(&(p_timer_obj[group_num][timer_num]->hal), config->divider); in timer_init()
339 config->divider = div; in timer_get_config()

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