Searched refs:dig_dbias_slp (Results 1 – 16 of 16) sorted by relevance
| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32s3/ |
| D | rtc_sleep.c | 83 out_config->dig_dbias_slp = 0; //not used in rtc_sleep_get_default_config()
136 out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10; in rtc_sleep_get_default_config()
148 out_config->dig_dbias_slp = 0; in rtc_sleep_get_default_config()
158 out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; in rtc_sleep_get_default_config()
223 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); in rtc_sleep_init()
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| D | rtc_pm.c | 48 cfg.dig_dbias_slp = 0; in pm_set_sleep_mode()
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| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32h2/ |
| D | rtc_pm.c | 49 cfg.dig_dbias_slp = 0; in pm_set_sleep_mode()
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| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32s2/ |
| D | rtc_pm.c | 49 cfg.dig_dbias_slp = 0; in pm_set_sleep_mode()
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| D | rtc_sleep.c | 129 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); in rtc_sleep_init()
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| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32c3/ |
| D | rtc_pm.c | 49 cfg.dig_dbias_slp = 0; in pm_set_sleep_mode()
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| D | rtc_sleep.c | 129 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); in rtc_sleep_init()
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| /hal_espressif-3.6.0/components/soc/esp32/include/soc/ |
| D | rtc.h | 501 uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode member
531 .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_0V90 \
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| D | rtc_cntl_struct.h | 338 uint32_t dig_dbias_slp: 3; /*DIG_REG_DBIAS during sleep*/ member
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| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32/ |
| D | rtc_pm.c | 47 cfg.dig_dbias_slp = 0; in pm_set_sleep_mode()
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| D | rtc_sleep.c | 203 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); in rtc_sleep_init()
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| /hal_espressif-3.6.0/components/soc/esp32c3/include/soc/ |
| D | rtc.h | 645 uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode member
677 .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \
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| /hal_espressif-3.6.0/components/soc/esp32s2/include/soc/ |
| D | rtc.h | 670 uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode member
699 .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DIG_DBIAS_0V90 \
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| D | rtc_cntl_struct.h | 424 uint32_t dig_dbias_slp: 3; /*DIG_REG_DBIAS during sleep*/ member
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| /hal_espressif-3.6.0/components/soc/esp32h2/include/soc/ |
| D | rtc.h | 661 uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode member
693 .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \
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| /hal_espressif-3.6.0/components/soc/esp32s3/include/soc/ |
| D | rtc.h | 683 uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode member
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