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Searched refs:configISR_STACK_SIZE (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-3.6.0/components/freertos/port/riscv/include/freertos/
DFreeRTOSConfig_arch.h92 #ifndef configISR_STACK_SIZE
93 #define configISR_STACK_SIZE (CONFIG_FREERTOS_ISR_STACKSIZE) macro
/hal_espressif-3.6.0/components/freertos/port/xtensa/include/freertos/
DFreeRTOSConfig_arch.h153 #ifndef configISR_STACK_SIZE
154 #define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTA… macro
/hal_espressif-3.6.0/components/freertos/port/riscv/
Dport.c117 __attribute__((aligned(16))) static StackType_t xIsrStack[configISR_STACK_SIZE];
118 StackType_t *xIsrStackTop = &xIsrStack[0] + (configISR_STACK_SIZE & (~((portPOINTER_SIZE_TYPE)portB…
/hal_espressif-3.6.0/components/freertos/port/xtensa/
Dportasm.S47 ….space configISR_STACK_SIZE*portNUM_PROCESSORS /* This allocates stacks for each individual …
136 movi a1, port_IntStack+configISR_STACK_SIZE /* a1 = top of intr stack for CPU 0 */
137 …movi a2, configISR_STACK_SIZE /* add configISR_STACK_SIZE * cpu_num to arrive at top of stac…
Dreadme_xtensa.txt322 stack is controlled by the parameter "configISR_STACK_SIZE" defined in
/hal_espressif-3.6.0/components/espcoredump/src/
Dcore_dump_common.c131 …esp_cpu_set_watchpoint(1, topStack+xPortGetCoreID()*configISR_STACK_SIZE, 1, ESP_WATCHPOINT_STORE); in esp_core_dump_setup_stack()
/hal_espressif-3.6.0/components/espcoredump/src/port/riscv/
Dcore_dump_port.c222 return (uint32_t)(isr_top_stack + (xPortGetCoreID()+1)*configISR_STACK_SIZE); in esp_core_dump_get_isr_stack_end()
/hal_espressif-3.6.0/components/espcoredump/src/port/xtensa/
Dcore_dump_port.c289 return (uint32_t)(isr_top_stack + (xPortGetCoreID()+1)*configISR_STACK_SIZE); in esp_core_dump_get_isr_stack_end()