Searched refs:alu_reg (Results 1 – 3 of 3) sorted by relevance
/hal_espressif-3.6.0/components/ulp/include/esp32s3/ |
D | ulp.h | 177 } alu_reg; /*!< Format of ALU instruction (both sources are registers) */ member 583 #define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 595 #define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 607 #define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 619 #define I_ORR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 631 #define I_MOVR(reg_dest, reg_src) { .alu_reg = { \ 643 #define I_LSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ 656 #define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \
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/hal_espressif-3.6.0/components/ulp/include/esp32s2/ |
D | ulp.h | 177 } alu_reg; /*!< Format of ALU instruction (both sources are registers) */ member 583 #define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 595 #define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 607 #define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 619 #define I_ORR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 631 #define I_MOVR(reg_dest, reg_src) { .alu_reg = { \ 643 #define I_LSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ 656 #define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \
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/hal_espressif-3.6.0/components/ulp/include/esp32/ |
D | ulp.h | 199 } alu_reg; /*!< Format of ALU instruction (both sources are registers) */ member 617 #define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 629 #define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 641 #define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 653 #define I_ORR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ 665 #define I_MOVR(reg_dest, reg_src) { .alu_reg = { \ 677 #define I_LSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ 690 #define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \
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