1 /* Copyright (c) 2010-2017, The Regents of the University of California
2    (Regents).  All Rights Reserved.
3 
4    Redistribution and use in source and binary forms, with or without
5    modification, are permitted provided that the following conditions are met:
6    1. Redistributions of source code must retain the above copyright
7       notice, this list of conditions and the following disclaimer.
8    2. Redistributions in binary form must reproduce the above copyright
9       notice, this list of conditions and the following disclaimer in the
10       documentation and/or other materials provided with the distribution.
11    3. Neither the name of the Regents nor the
12       names of its contributors may be used to endorse or promote products
13       derived from this software without specific prior written permission.
14 
15       IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
16       SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
17       OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
18       BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 
20       REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21       THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22       PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
23       HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
24       MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
25 */
26 
27 /* Adapted from https://github.com/riscv/riscv-opcodes/blob/master/encoding.h */
28 
29 #pragma once
30 
31 
32 #define MSTATUS_UIE         0x00000001
33 #define MSTATUS_SIE         0x00000002
34 #define MSTATUS_HIE         0x00000004
35 #define MSTATUS_MIE         0x00000008
36 #define MSTATUS_UPIE        0x00000010
37 #define MSTATUS_SPIE        0x00000020
38 #define MSTATUS_HPIE        0x00000040
39 #define MSTATUS_MPIE        0x00000080
40 #define MSTATUS_SPP         0x00000100
41 #define MSTATUS_VS          0x00000600
42 #define MSTATUS_MPP         0x00001800
43 #define MSTATUS_FS          0x00006000
44 #define MSTATUS_XS          0x00018000
45 #define MSTATUS_MPRV        0x00020000
46 #define MSTATUS_SUM         0x00040000
47 #define MSTATUS_MXR         0x00080000
48 #define MSTATUS_TVM         0x00100000
49 #define MSTATUS_TW          0x00200000
50 #define MSTATUS_TSR         0x00400000
51 #define MSTATUS32_SD        0x80000000
52 #define MSTATUS_UXL         0x0000000300000000
53 #define MSTATUS_SXL         0x0000000C00000000
54 #define MSTATUS64_SD        0x8000000000000000
55 
56 #define SSTATUS_UIE         0x00000001
57 #define SSTATUS_SIE         0x00000002
58 #define SSTATUS_UPIE        0x00000010
59 #define SSTATUS_SPIE        0x00000020
60 #define SSTATUS_SPP         0x00000100
61 #define SSTATUS_VS          0x00000600
62 #define SSTATUS_FS          0x00006000
63 #define SSTATUS_XS          0x00018000
64 #define SSTATUS_SUM         0x00040000
65 #define SSTATUS_MXR         0x00080000
66 #define SSTATUS32_SD        0x80000000
67 #define SSTATUS_UXL         0x0000000300000000
68 #define SSTATUS64_SD        0x8000000000000000
69 
70 #define USTATUS_UIE         0x00000001
71 #define USTATUS_UPIE        0x00000010
72 
73 #define DCSR_XDEBUGVER      (3U<<30)
74 #define DCSR_NDRESET        (1<<29)
75 #define DCSR_FULLRESET      (1<<28)
76 #define DCSR_EBREAKM        (1<<15)
77 #define DCSR_EBREAKH        (1<<14)
78 #define DCSR_EBREAKS        (1<<13)
79 #define DCSR_EBREAKU        (1<<12)
80 #define DCSR_STOPCYCLE      (1<<10)
81 #define DCSR_STOPTIME       (1<<9)
82 #define DCSR_CAUSE          (7<<6)
83 #define DCSR_DEBUGINT       (1<<5)
84 #define DCSR_HALT           (1<<3)
85 #define DCSR_STEP           (1<<2)
86 #define DCSR_PRV            (3<<0)
87 
88 #define DCSR_CAUSE_NONE     0
89 #define DCSR_CAUSE_SWBP     1
90 #define DCSR_CAUSE_HWBP     2
91 #define DCSR_CAUSE_DEBUGINT 3
92 #define DCSR_CAUSE_STEP     4
93 #define DCSR_CAUSE_HALT     5
94 #define DCSR_CAUSE_GROUP    6
95 
96 #define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
97 #define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
98 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
99 
100 #define MCONTROL_SELECT     (1<<19)
101 #define MCONTROL_TIMING     (1<<18)
102 #define MCONTROL_ACTION     (0x3f<<12)
103 #define MCONTROL_CHAIN      (1<<11)
104 #define MCONTROL_MATCH      (0xf<<7)
105 #define MCONTROL_M          (1<<6)
106 #define MCONTROL_H          (1<<5)
107 #define MCONTROL_S          (1<<4)
108 #define MCONTROL_U          (1<<3)
109 #define MCONTROL_EXECUTE    (1<<2)
110 #define MCONTROL_STORE      (1<<1)
111 #define MCONTROL_LOAD       (1<<0)
112 
113 #define MCONTROL_TYPE_NONE      0
114 #define MCONTROL_TYPE_MATCH     2
115 
116 #define MCONTROL_ACTION_DEBUG_EXCEPTION   0
117 #define MCONTROL_ACTION_DEBUG_MODE        1
118 #define MCONTROL_ACTION_TRACE_START       2
119 #define MCONTROL_ACTION_TRACE_STOP        3
120 #define MCONTROL_ACTION_TRACE_EMIT        4
121 
122 #define MCONTROL_MATCH_EQUAL     0
123 #define MCONTROL_MATCH_NAPOT     1
124 #define MCONTROL_MATCH_GE        2
125 #define MCONTROL_MATCH_LT        3
126 #define MCONTROL_MATCH_MASK_LOW  4
127 #define MCONTROL_MATCH_MASK_HIGH 5
128 
129 #define MIP_USIP            (1 << IRQ_U_SOFT)
130 #define MIP_SSIP            (1 << IRQ_S_SOFT)
131 #define MIP_HSIP            (1 << IRQ_H_SOFT)
132 #define MIP_MSIP            (1 << IRQ_M_SOFT)
133 #define MIP_UTIP            (1 << IRQ_U_TIMER)
134 #define MIP_STIP            (1 << IRQ_S_TIMER)
135 #define MIP_HTIP            (1 << IRQ_H_TIMER)
136 #define MIP_MTIP            (1 << IRQ_M_TIMER)
137 #define MIP_UEIP            (1 << IRQ_U_EXT)
138 #define MIP_SEIP            (1 << IRQ_S_EXT)
139 #define MIP_HEIP            (1 << IRQ_H_EXT)
140 #define MIP_MEIP            (1 << IRQ_M_EXT)
141 
142 #define SIP_SSIP MIP_SSIP
143 #define SIP_STIP MIP_STIP
144 
145 #define PRV_U 0
146 #define PRV_S 1
147 #define PRV_H 2
148 #define PRV_M 3
149 
150 #define SATP32_MODE 0x80000000
151 #define SATP32_ASID 0x7FC00000
152 #define SATP32_PPN  0x003FFFFF
153 #define SATP64_MODE 0xF000000000000000
154 #define SATP64_ASID 0x0FFFF00000000000
155 #define SATP64_PPN  0x00000FFFFFFFFFFF
156 
157 #define SATP_MODE_OFF  0
158 #define SATP_MODE_SV32 1
159 #define SATP_MODE_SV39 8
160 #define SATP_MODE_SV48 9
161 #define SATP_MODE_SV57 10
162 #define SATP_MODE_SV64 11
163 
164 #define PMP_R     0x01
165 #define PMP_W     0x02
166 #define PMP_X     0x04
167 #define PMP_A     0x18
168 #define PMP_L     0x80
169 #define PMP_SHIFT 2
170 
171 #define PMP_TOR   0x08
172 #define PMP_NA4   0x10
173 #define PMP_NAPOT 0x18
174 
175 #define IRQ_U_SOFT   0
176 #define IRQ_S_SOFT   1
177 #define IRQ_H_SOFT   2
178 #define IRQ_M_SOFT   3
179 #define IRQ_U_TIMER  4
180 #define IRQ_S_TIMER  5
181 #define IRQ_H_TIMER  6
182 #define IRQ_M_TIMER  7
183 #define IRQ_U_EXT    8
184 #define IRQ_S_EXT    9
185 #define IRQ_H_EXT    10
186 #define IRQ_M_EXT    11
187 #define IRQ_COP      12
188 #define IRQ_HOST     13
189 
190 #define DEFAULT_RSTVEC     0x00001000
191 #define CLINT_BASE         0x02000000
192 #define CLINT_SIZE         0x000c0000
193 #define EXT_IO_BASE        0x40000000
194 #define DRAM_BASE          0x80000000
195 
196 /* page table entry (PTE) fields */
197 #define PTE_V     0x001 /* Valid */
198 #define PTE_R     0x002 /* Read */
199 #define PTE_W     0x004 /* Write */
200 #define PTE_X     0x008 /* Execute */
201 #define PTE_U     0x010 /* User */
202 #define PTE_G     0x020 /* Global */
203 #define PTE_A     0x040 /* Accessed */
204 #define PTE_D     0x080 /* Dirty */
205 #define PTE_SOFT  0x300 /* Reserved for Software */
206 
207 #define PTE_PPN_SHIFT 10
208 
209 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
210 
211 #ifdef __riscv
212 
213 #if __riscv_xlen == 64
214 # define MSTATUS_SD MSTATUS64_SD
215 # define SSTATUS_SD SSTATUS64_SD
216 # define RISCV_PGLEVEL_BITS 9
217 # define SATP_MODE SATP64_MODE
218 #else
219 # define MSTATUS_SD MSTATUS32_SD
220 # define SSTATUS_SD SSTATUS32_SD
221 # define RISCV_PGLEVEL_BITS 10
222 # define SATP_MODE SATP32_MODE
223 #endif
224 #define RISCV_PGSHIFT 12
225 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
226 
227 #endif // __riscv
228