Searched refs:SYSTEM_SYSCLK_CONF_REG (Results 1 – 8 of 8) sorted by relevance
| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32c3/ |
| D | rtc_clk.c | 285 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); in rtc_clk_cpu_freq_to_pll_mhz()
286 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); in rtc_clk_cpu_freq_to_pll_mhz()
334 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in rtc_clk_cpu_freq_set_config()
362 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
366 div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
438 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); in rtc_clk_cpu_freq_to_xtal()
439 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1); in rtc_clk_cpu_freq_to_xtal()
442 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_XTAL); in rtc_clk_cpu_freq_to_xtal()
449 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); in rtc_clk_cpu_freq_to_8m()
450 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M); in rtc_clk_cpu_freq_to_8m()
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| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32s3/ |
| D | rtc_clk.c | 312 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); in rtc_clk_cpu_freq_to_pll_mhz()
313 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); in rtc_clk_cpu_freq_to_pll_mhz()
366 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in rtc_clk_cpu_freq_set_config()
394 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
398 div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config()
481 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); in rtc_clk_cpu_freq_to_xtal()
482 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1); in rtc_clk_cpu_freq_to_xtal()
485 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_XTAL); in rtc_clk_cpu_freq_to_xtal()
494 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); in rtc_clk_cpu_freq_to_8m()
495 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M); in rtc_clk_cpu_freq_to_8m()
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| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32h2/ |
| D | rtc_clk.c | 243 uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
409 return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SPLL_FREQ); in read_spll_freq()
414 return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_CLK_XTAL_FREQ); in read_xtal_freq()
451 REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, source); in root_clk_slt()
457 uint32_t src_slt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in root_clk_get()
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| /hal_espressif-3.6.0/components/esptool_py/esptool/flasher_stub/ |
| D | stub_flasher.c | 83 sysclk_conf_reg = READ_REG(SYSTEM_SYSCLK_CONF_REG); in set_max_cpu_freq()
84 …WRITE_REG(SYSTEM_SYSCLK_CONF_REG, (sysclk_conf_reg & ~SYSTEM_SOC_CLK_SEL_M) | (SYSTEM_SOC_CLK_MAX … in set_max_cpu_freq()
104 …WRITE_REG(SYSTEM_SYSCLK_CONF_REG, (READ_REG(SYSTEM_SYSCLK_CONF_REG) & ~SYSTEM_SOC_CLK_SEL_M) | (sy… in reset_cpu_freq()
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| /hal_espressif-3.6.0/components/esptool_py/esptool/flasher_stub/include/ |
| D | soc_support.h | 359 #define SYSTEM_SYSCLK_CONF_REG (SYSTEM_BASE_REG + 0x060) macro
373 #define SYSTEM_SYSCLK_CONF_REG (SYSTEM_BASE_REG + 0x058) macro
387 #define SYSTEM_SYSCLK_CONF_REG (SYSTEM_BASE_REG + 0x08C) macro
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| /hal_espressif-3.6.0/components/soc/esp32c3/include/soc/ |
| D | system_reg.h | 822 #define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x058) macro
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| /hal_espressif-3.6.0/components/soc/esp32h2/include/soc/ |
| D | clkrst_reg.h | 22 #define SYSTEM_SYSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0000) macro
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| /hal_espressif-3.6.0/components/soc/esp32s3/include/soc/ |
| D | system_reg.h | 863 #define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x60) macro
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