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Searched refs:SYSTEM_CPU_INTR_FROM_CPU_0_REG (Results 1 – 5 of 5) sorted by relevance

/hal_espressif-3.6.0/components/esp_system/
Dcrosscore_int.c66 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); in esp_crosscore_isr()
71 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); in esp_crosscore_isr()
133 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); in esp_crosscore_int_send()
138 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); in esp_crosscore_int_send()
/hal_espressif-3.6.0/components/freertos/port/riscv/
Dport.c349 …le (uxSchedulerRunning && uxCriticalNesting == 0 && REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG) != 0)… in vPortYield()
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dsystem_reg.h73 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x010) macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dsystem_reg.h648 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x028) macro
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dsystem_reg.h689 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x30) macro