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Searched refs:SYSTEM_BT_LPCK_DIV_FRAC_REG (Results 1 – 5 of 5) sorted by relevance

/hal_espressif-3.6.0/components/esp_system/port/soc/esp32c3/
Dclk.c299 CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); in esp_perip_clk_init()
300 SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); in esp_perip_clk_init()
/hal_espressif-3.6.0/components/esp_system/port/soc/esp32s3/
Dclk.c327 CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); in esp_perip_clk_init()
328 SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); in esp_perip_clk_init()
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dsystem_reg.h604 #define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x024) macro
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dsystem_reg.h645 #define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x2C) macro
/hal_espressif-3.6.0/zephyr/esp32s3/src/wifi/
Desp_wifi_adapter.c499 if (GET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL)) { in esp_clk_slowclk_cal_get_wrapper()