1 // Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SYSCON_REG_H_ 15 #define _SOC_SYSCON_REG_H_ 16 17 18 #include "soc.h" 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0) 24 /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ 25 /*description: .*/ 26 #define SYSCON_RST_TICK_CNT (BIT(12)) 27 #define SYSCON_RST_TICK_CNT_M (BIT(12)) 28 #define SYSCON_RST_TICK_CNT_V 0x1 29 #define SYSCON_RST_TICK_CNT_S 12 30 /* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 31 /*description: .*/ 32 #define SYSCON_CLK_EN (BIT(11)) 33 #define SYSCON_CLK_EN_M (BIT(11)) 34 #define SYSCON_CLK_EN_V 0x1 35 #define SYSCON_CLK_EN_S 11 36 /* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 37 /*description: .*/ 38 #define SYSCON_CLK_320M_EN (BIT(10)) 39 #define SYSCON_CLK_320M_EN_M (BIT(10)) 40 #define SYSCON_CLK_320M_EN_V 0x1 41 #define SYSCON_CLK_320M_EN_S 10 42 /* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ 43 /*description: .*/ 44 #define SYSCON_PRE_DIV_CNT 0x000003FF 45 #define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S)) 46 #define SYSCON_PRE_DIV_CNT_V 0x3FF 47 #define SYSCON_PRE_DIV_CNT_S 0 48 49 #define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4) 50 /* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ 51 /*description: .*/ 52 #define SYSCON_TICK_ENABLE (BIT(16)) 53 #define SYSCON_TICK_ENABLE_M (BIT(16)) 54 #define SYSCON_TICK_ENABLE_V 0x1 55 #define SYSCON_TICK_ENABLE_S 16 56 /* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ 57 /*description: .*/ 58 #define SYSCON_CK8M_TICK_NUM 0x000000FF 59 #define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S)) 60 #define SYSCON_CK8M_TICK_NUM_V 0xFF 61 #define SYSCON_CK8M_TICK_NUM_S 8 62 /* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ 63 /*description: .*/ 64 #define SYSCON_XTAL_TICK_NUM 0x000000FF 65 #define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S)) 66 #define SYSCON_XTAL_TICK_NUM_V 0xFF 67 #define SYSCON_XTAL_TICK_NUM_S 0 68 69 #define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x8) 70 /* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 71 /*description: .*/ 72 #define SYSCON_CLK_XTAL_OEN (BIT(10)) 73 #define SYSCON_CLK_XTAL_OEN_M (BIT(10)) 74 #define SYSCON_CLK_XTAL_OEN_V 0x1 75 #define SYSCON_CLK_XTAL_OEN_S 10 76 /* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 77 /*description: .*/ 78 #define SYSCON_CLK40X_BB_OEN (BIT(9)) 79 #define SYSCON_CLK40X_BB_OEN_M (BIT(9)) 80 #define SYSCON_CLK40X_BB_OEN_V 0x1 81 #define SYSCON_CLK40X_BB_OEN_S 9 82 /* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ 83 /*description: .*/ 84 #define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) 85 #define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) 86 #define SYSCON_CLK_DAC_CPU_OEN_V 0x1 87 #define SYSCON_CLK_DAC_CPU_OEN_S 8 88 /* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ 89 /*description: .*/ 90 #define SYSCON_CLK_ADC_INF_OEN (BIT(7)) 91 #define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) 92 #define SYSCON_CLK_ADC_INF_OEN_V 0x1 93 #define SYSCON_CLK_ADC_INF_OEN_S 7 94 /* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 95 /*description: .*/ 96 #define SYSCON_CLK_320M_OEN (BIT(6)) 97 #define SYSCON_CLK_320M_OEN_M (BIT(6)) 98 #define SYSCON_CLK_320M_OEN_V 0x1 99 #define SYSCON_CLK_320M_OEN_S 6 100 /* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 101 /*description: .*/ 102 #define SYSCON_CLK160_OEN (BIT(5)) 103 #define SYSCON_CLK160_OEN_M (BIT(5)) 104 #define SYSCON_CLK160_OEN_V 0x1 105 #define SYSCON_CLK160_OEN_S 5 106 /* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ 107 /*description: .*/ 108 #define SYSCON_CLK80_OEN (BIT(4)) 109 #define SYSCON_CLK80_OEN_M (BIT(4)) 110 #define SYSCON_CLK80_OEN_V 0x1 111 #define SYSCON_CLK80_OEN_S 4 112 /* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 113 /*description: .*/ 114 #define SYSCON_CLK_BB_OEN (BIT(3)) 115 #define SYSCON_CLK_BB_OEN_M (BIT(3)) 116 #define SYSCON_CLK_BB_OEN_V 0x1 117 #define SYSCON_CLK_BB_OEN_S 3 118 /* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 119 /*description: .*/ 120 #define SYSCON_CLK44_OEN (BIT(2)) 121 #define SYSCON_CLK44_OEN_M (BIT(2)) 122 #define SYSCON_CLK44_OEN_V 0x1 123 #define SYSCON_CLK44_OEN_S 2 124 /* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 125 /*description: .*/ 126 #define SYSCON_CLK22_OEN (BIT(1)) 127 #define SYSCON_CLK22_OEN_M (BIT(1)) 128 #define SYSCON_CLK22_OEN_V 0x1 129 #define SYSCON_CLK22_OEN_S 1 130 /* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 131 /*description: .*/ 132 #define SYSCON_CLK20_OEN (BIT(0)) 133 #define SYSCON_CLK20_OEN_M (BIT(0)) 134 #define SYSCON_CLK20_OEN_V 0x1 135 #define SYSCON_CLK20_OEN_S 0 136 137 #define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC) 138 /* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 139 /*description: .*/ 140 #define SYSCON_WIFI_BB_CFG 0xFFFFFFFF 141 #define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S)) 142 #define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF 143 #define SYSCON_WIFI_BB_CFG_S 0 144 145 #define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10) 146 /* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 147 /*description: .*/ 148 #define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF 149 #define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S)) 150 #define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF 151 #define SYSCON_WIFI_BB_CFG_2_S 0 152 153 #define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x14) 154 /* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 155 /*description: .*/ 156 #define SYSCON_WIFI_CLK_EN 0xFFFFFFFF 157 #define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S)) 158 #define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF 159 #define SYSCON_WIFI_CLK_EN_S 0 160 161 #define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18) 162 /* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 163 /*description: .*/ 164 #define SYSCON_WIFI_RST 0xFFFFFFFF 165 #define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S)) 166 #define SYSCON_WIFI_RST_V 0xFFFFFFFF 167 #define SYSCON_WIFI_RST_S 0 168 169 #define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG 170 /* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 171 /*description: */ 172 #define SYSTEM_WIFI_CLK_EN 0x00FB9FCF 173 #define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V) << (SYSTEM_WIFI_CLK_EN_S)) 174 #define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF 175 #define SYSTEM_WIFI_CLK_EN_S 0 176 177 /* Mask for all Wifi clock bits, 6 */ 178 #define SYSTEM_WIFI_CLK_WIFI_EN 0x0 179 #define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S)) 180 #define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0 181 #define SYSTEM_WIFI_CLK_WIFI_EN_S 0 182 /* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */ 183 #define SYSTEM_WIFI_CLK_BT_EN 0x0 184 #define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S)) 185 #define SYSTEM_WIFI_CLK_BT_EN_V 0x0 186 #define SYSTEM_WIFI_CLK_BT_EN_S 0 187 /* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */ 188 #define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F 189 190 /* Digital team to check */ 191 //bluetooth baseband bit11 192 #define SYSTEM_BT_BASEBAND_EN BIT(11) 193 //bluetooth LC bit16 and bit17 194 #define SYSTEM_BT_LC_EN (BIT(16) | BIT(17)) 195 196 /* Remaining single bit clock masks */ 197 #define SYSTEM_WIFI_CLK_UNUSED_BIT5 BIT(5) 198 #define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12) 199 #define SYSTEM_WIFI_CLK_SDIO_HOST_EN BIT(13) 200 #define SYSTEM_WIFI_CLK_EMAC_EN BIT(14) 201 #define SYSTEM_WIFI_CLK_RNG_EN BIT(15) 202 203 #define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG 204 #define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG 205 /* SYSTEM_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 206 /*description: */ 207 #define SYSTEM_WIFI_RST 0xFFFFFFFF 208 #define SYSTEM_WIFI_RST_M ((SYSTEM_WIFI_RST_V) << (SYSTEM_WIFI_RST_S)) 209 #define SYSTEM_WIFI_RST_V 0xFFFFFFFF 210 #define SYSTEM_WIFI_RST_S 0 211 #define SYSTEM_BB_REG_RST (BIT(13)) 212 #define SYSTEM_PWR_REG_RST (BIT(12)) 213 #define SYSTEM_BLE_REG_RST (BIT(11)) 214 #define SYSTEM_RW_BTLP_RST (BIT(10)) 215 #define SYSTEM_RW_BTMAC_RST (BIT(9)) 216 #define SYSTEM_MACPWR_RST (BIT(8)) 217 #define SYSTEM_EMAC_RST (BIT(7)) 218 #define SYSTEM_SDIO_RST (BIT(5)) 219 #define SYSTEM_BTMAC_RST (BIT(4)) 220 #define SYSTEM_BT_RST (BIT(3)) 221 #define SYSTEM_MAC_RST (BIT(2)) 222 #define SYSTEM_FE_RST (BIT(1)) 223 #define SYSTEM_BB_RST (BIT(0)) 224 225 #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C) 226 /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 227 /*description: .*/ 228 #define SYSCON_PERI_IO_SWAP 0x000000FF 229 #define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S)) 230 #define SYSCON_PERI_IO_SWAP_V 0xFF 231 #define SYSCON_PERI_IO_SWAP_S 0 232 233 #define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20) 234 /* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 235 /*description: .*/ 236 #define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) 237 #define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) 238 #define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 239 #define SYSCON_EXT_MEM_PMS_LOCK_S 0 240 241 #define SYSCON_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_SYSCON_BASE + 0x24) 242 /* SYSCON_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 243 /*description: Set 1 to bypass cache writeback request to external memory so that spi will not 244 check its attribute..*/ 245 #define SYSCON_WRITEBACK_BYPASS (BIT(0)) 246 #define SYSCON_WRITEBACK_BYPASS_M (BIT(0)) 247 #define SYSCON_WRITEBACK_BYPASS_V 0x1 248 #define SYSCON_WRITEBACK_BYPASS_S 0 249 250 #define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28) 251 /* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 252 /*description: .*/ 253 #define SYSCON_FLASH_ACE0_ATTR 0x000001FF 254 #define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S)) 255 #define SYSCON_FLASH_ACE0_ATTR_V 0x1FF 256 #define SYSCON_FLASH_ACE0_ATTR_S 0 257 258 #define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2C) 259 /* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 260 /*description: .*/ 261 #define SYSCON_FLASH_ACE1_ATTR 0x000001FF 262 #define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S)) 263 #define SYSCON_FLASH_ACE1_ATTR_V 0x1FF 264 #define SYSCON_FLASH_ACE1_ATTR_S 0 265 266 #define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30) 267 /* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 268 /*description: .*/ 269 #define SYSCON_FLASH_ACE2_ATTR 0x000001FF 270 #define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S)) 271 #define SYSCON_FLASH_ACE2_ATTR_V 0x1FF 272 #define SYSCON_FLASH_ACE2_ATTR_S 0 273 274 #define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34) 275 /* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 276 /*description: .*/ 277 #define SYSCON_FLASH_ACE3_ATTR 0x000001FF 278 #define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S)) 279 #define SYSCON_FLASH_ACE3_ATTR_V 0x1FF 280 #define SYSCON_FLASH_ACE3_ATTR_S 0 281 282 #define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38) 283 /* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 284 /*description: .*/ 285 #define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF 286 #define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S)) 287 #define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF 288 #define SYSCON_FLASH_ACE0_ADDR_S_S 0 289 290 #define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3C) 291 /* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ 292 /*description: .*/ 293 #define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF 294 #define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S)) 295 #define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF 296 #define SYSCON_FLASH_ACE1_ADDR_S_S 0 297 298 #define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40) 299 /* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ 300 /*description: .*/ 301 #define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF 302 #define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S)) 303 #define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF 304 #define SYSCON_FLASH_ACE2_ADDR_S_S 0 305 306 #define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44) 307 /* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ 308 /*description: .*/ 309 #define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF 310 #define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S)) 311 #define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF 312 #define SYSCON_FLASH_ACE3_ADDR_S_S 0 313 314 #define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48) 315 /* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 316 /*description: .*/ 317 #define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF 318 #define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S)) 319 #define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF 320 #define SYSCON_FLASH_ACE0_SIZE_S 0 321 322 #define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4C) 323 /* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 324 /*description: .*/ 325 #define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF 326 #define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S)) 327 #define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF 328 #define SYSCON_FLASH_ACE1_SIZE_S 0 329 330 #define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50) 331 /* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 332 /*description: .*/ 333 #define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF 334 #define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S)) 335 #define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF 336 #define SYSCON_FLASH_ACE2_SIZE_S 0 337 338 #define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54) 339 /* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 340 /*description: .*/ 341 #define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF 342 #define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S)) 343 #define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF 344 #define SYSCON_FLASH_ACE3_SIZE_S 0 345 346 #define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x58) 347 /* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 348 /*description: .*/ 349 #define SYSCON_SRAM_ACE0_ATTR 0x000001FF 350 #define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S)) 351 #define SYSCON_SRAM_ACE0_ATTR_V 0x1FF 352 #define SYSCON_SRAM_ACE0_ATTR_S 0 353 354 #define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x5C) 355 /* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 356 /*description: .*/ 357 #define SYSCON_SRAM_ACE1_ATTR 0x000001FF 358 #define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S)) 359 #define SYSCON_SRAM_ACE1_ATTR_V 0x1FF 360 #define SYSCON_SRAM_ACE1_ATTR_S 0 361 362 #define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x60) 363 /* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 364 /*description: .*/ 365 #define SYSCON_SRAM_ACE2_ATTR 0x000001FF 366 #define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S)) 367 #define SYSCON_SRAM_ACE2_ATTR_V 0x1FF 368 #define SYSCON_SRAM_ACE2_ATTR_S 0 369 370 #define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x64) 371 /* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ 372 /*description: .*/ 373 #define SYSCON_SRAM_ACE3_ATTR 0x000001FF 374 #define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S)) 375 #define SYSCON_SRAM_ACE3_ATTR_V 0x1FF 376 #define SYSCON_SRAM_ACE3_ATTR_S 0 377 378 #define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x68) 379 /* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 380 /*description: .*/ 381 #define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF 382 #define SYSCON_SRAM_ACE0_ADDR_S_M ((SYSCON_SRAM_ACE0_ADDR_S_V)<<(SYSCON_SRAM_ACE0_ADDR_S_S)) 383 #define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF 384 #define SYSCON_SRAM_ACE0_ADDR_S_S 0 385 386 #define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x6C) 387 /* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ 388 /*description: .*/ 389 #define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF 390 #define SYSCON_SRAM_ACE1_ADDR_S_M ((SYSCON_SRAM_ACE1_ADDR_S_V)<<(SYSCON_SRAM_ACE1_ADDR_S_S)) 391 #define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF 392 #define SYSCON_SRAM_ACE1_ADDR_S_S 0 393 394 #define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x70) 395 /* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ 396 /*description: .*/ 397 #define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF 398 #define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S)) 399 #define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF 400 #define SYSCON_SRAM_ACE2_ADDR_S_S 0 401 402 #define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x74) 403 /* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ 404 /*description: .*/ 405 #define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF 406 #define SYSCON_SRAM_ACE3_ADDR_S_M ((SYSCON_SRAM_ACE3_ADDR_S_V)<<(SYSCON_SRAM_ACE3_ADDR_S_S)) 407 #define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF 408 #define SYSCON_SRAM_ACE3_ADDR_S_S 0 409 410 #define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x78) 411 /* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 412 /*description: .*/ 413 #define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF 414 #define SYSCON_SRAM_ACE0_SIZE_M ((SYSCON_SRAM_ACE0_SIZE_V)<<(SYSCON_SRAM_ACE0_SIZE_S)) 415 #define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF 416 #define SYSCON_SRAM_ACE0_SIZE_S 0 417 418 #define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x7C) 419 /* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 420 /*description: .*/ 421 #define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF 422 #define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S)) 423 #define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF 424 #define SYSCON_SRAM_ACE1_SIZE_S 0 425 426 #define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x80) 427 /* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 428 /*description: .*/ 429 #define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF 430 #define SYSCON_SRAM_ACE2_SIZE_M ((SYSCON_SRAM_ACE2_SIZE_V)<<(SYSCON_SRAM_ACE2_SIZE_S)) 431 #define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF 432 #define SYSCON_SRAM_ACE2_SIZE_S 0 433 434 #define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x84) 435 /* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 436 /*description: .*/ 437 #define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF 438 #define SYSCON_SRAM_ACE3_SIZE_M ((SYSCON_SRAM_ACE3_SIZE_V)<<(SYSCON_SRAM_ACE3_SIZE_S)) 439 #define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF 440 #define SYSCON_SRAM_ACE3_SIZE_S 0 441 442 #define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88) 443 /* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ 444 /*description: .*/ 445 #define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F 446 #define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S)) 447 #define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F 448 #define SYSCON_SPI_MEM_REJECT_CDE_S 2 449 /* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 450 /*description: .*/ 451 #define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) 452 #define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) 453 #define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 454 #define SYSCON_SPI_MEM_REJECT_CLR_S 1 455 /* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ 456 /*description: .*/ 457 #define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) 458 #define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) 459 #define SYSCON_SPI_MEM_REJECT_INT_V 0x1 460 #define SYSCON_SPI_MEM_REJECT_INT_S 0 461 462 #define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8C) 463 /* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 464 /*description: .*/ 465 #define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF 466 #define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S)) 467 #define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF 468 #define SYSCON_SPI_MEM_REJECT_ADDR_S 0 469 470 #define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90) 471 /* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 472 /*description: .*/ 473 #define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) 474 #define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) 475 #define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 476 #define SYSCON_SDIO_WIN_ACCESS_EN_S 0 477 478 #define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94) 479 /* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 480 /*description: .*/ 481 #define SYSCON_REDCY_ANDOR (BIT(31)) 482 #define SYSCON_REDCY_ANDOR_M (BIT(31)) 483 #define SYSCON_REDCY_ANDOR_V 0x1 484 #define SYSCON_REDCY_ANDOR_S 31 485 /* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 486 /*description: .*/ 487 #define SYSCON_REDCY_SIG0 0x7FFFFFFF 488 #define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S)) 489 #define SYSCON_REDCY_SIG0_V 0x7FFFFFFF 490 #define SYSCON_REDCY_SIG0_S 0 491 492 #define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98) 493 /* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 494 /*description: .*/ 495 #define SYSCON_REDCY_NANDOR (BIT(31)) 496 #define SYSCON_REDCY_NANDOR_M (BIT(31)) 497 #define SYSCON_REDCY_NANDOR_V 0x1 498 #define SYSCON_REDCY_NANDOR_S 31 499 /* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 500 /*description: .*/ 501 #define SYSCON_REDCY_SIG1 0x7FFFFFFF 502 #define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S)) 503 #define SYSCON_REDCY_SIG1_V 0x7FFFFFFF 504 #define SYSCON_REDCY_SIG1_S 0 505 506 #define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C) 507 /* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 508 /*description: .*/ 509 #define SYSCON_FREQ_MEM_FORCE_PD (BIT(7)) 510 #define SYSCON_FREQ_MEM_FORCE_PD_M (BIT(7)) 511 #define SYSCON_FREQ_MEM_FORCE_PD_V 0x1 512 #define SYSCON_FREQ_MEM_FORCE_PD_S 7 513 /* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */ 514 /*description: .*/ 515 #define SYSCON_FREQ_MEM_FORCE_PU (BIT(6)) 516 #define SYSCON_FREQ_MEM_FORCE_PU_M (BIT(6)) 517 #define SYSCON_FREQ_MEM_FORCE_PU_V 0x1 518 #define SYSCON_FREQ_MEM_FORCE_PU_S 6 519 /* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 520 /*description: .*/ 521 #define SYSCON_DC_MEM_FORCE_PD (BIT(5)) 522 #define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) 523 #define SYSCON_DC_MEM_FORCE_PD_V 0x1 524 #define SYSCON_DC_MEM_FORCE_PD_S 5 525 /* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 526 /*description: .*/ 527 #define SYSCON_DC_MEM_FORCE_PU (BIT(4)) 528 #define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) 529 #define SYSCON_DC_MEM_FORCE_PU_V 0x1 530 #define SYSCON_DC_MEM_FORCE_PU_S 4 531 /* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 532 /*description: .*/ 533 #define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) 534 #define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) 535 #define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 536 #define SYSCON_PBUS_MEM_FORCE_PD_S 3 537 /* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 538 /*description: .*/ 539 #define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) 540 #define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) 541 #define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 542 #define SYSCON_PBUS_MEM_FORCE_PU_S 2 543 /* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 544 /*description: .*/ 545 #define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) 546 #define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) 547 #define SYSCON_AGC_MEM_FORCE_PD_V 0x1 548 #define SYSCON_AGC_MEM_FORCE_PD_S 1 549 /* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ 550 /*description: .*/ 551 #define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) 552 #define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) 553 #define SYSCON_AGC_MEM_FORCE_PU_V 0x1 554 #define SYSCON_AGC_MEM_FORCE_PU_S 0 555 556 #define SYSCON_SPI_MEM_ECC_CTRL_REG (DR_REG_SYSCON_BASE + 0xA0) 557 /* SYSCON_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */ 558 /*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 559 1024 bytes. 3: 2048 bytes..*/ 560 #define SYSCON_SRAM_PAGE_SIZE 0x00000003 561 #define SYSCON_SRAM_PAGE_SIZE_M ((SYSCON_SRAM_PAGE_SIZE_V)<<(SYSCON_SRAM_PAGE_SIZE_S)) 562 #define SYSCON_SRAM_PAGE_SIZE_V 0x3 563 #define SYSCON_SRAM_PAGE_SIZE_S 20 564 /* SYSCON_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ 565 /*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by 566 tes. 3: 2048 bytes..*/ 567 #define SYSCON_FLASH_PAGE_SIZE 0x00000003 568 #define SYSCON_FLASH_PAGE_SIZE_M ((SYSCON_FLASH_PAGE_SIZE_V)<<(SYSCON_FLASH_PAGE_SIZE_S)) 569 #define SYSCON_FLASH_PAGE_SIZE_V 0x3 570 #define SYSCON_FLASH_PAGE_SIZE_S 18 571 572 #define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xA8) 573 /* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */ 574 /*description: .*/ 575 #define SYSCON_SRAM_CLKGATE_FORCE_ON 0x000007FF 576 #define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S)) 577 #define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0x7FF 578 #define SYSCON_SRAM_CLKGATE_FORCE_ON_S 3 579 /* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ 580 /*description: .*/ 581 #define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000007 582 #define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S)) 583 #define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x7 584 #define SYSCON_ROM_CLKGATE_FORCE_ON_S 0 585 586 #define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xAC) 587 /* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */ 588 /*description: .*/ 589 #define SYSCON_SRAM_POWER_DOWN 0x000007FF 590 #define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S)) 591 #define SYSCON_SRAM_POWER_DOWN_V 0x7FF 592 #define SYSCON_SRAM_POWER_DOWN_S 3 593 /* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ 594 /*description: .*/ 595 #define SYSCON_ROM_POWER_DOWN 0x00000007 596 #define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S)) 597 #define SYSCON_ROM_POWER_DOWN_V 0x7 598 #define SYSCON_ROM_POWER_DOWN_S 0 599 600 #define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xB0) 601 /* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */ 602 /*description: .*/ 603 #define SYSCON_SRAM_POWER_UP 0x000007FF 604 #define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S)) 605 #define SYSCON_SRAM_POWER_UP_V 0x7FF 606 #define SYSCON_SRAM_POWER_UP_S 3 607 /* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ 608 /*description: .*/ 609 #define SYSCON_ROM_POWER_UP 0x00000007 610 #define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S)) 611 #define SYSCON_ROM_POWER_UP_V 0x7 612 #define SYSCON_ROM_POWER_UP_S 0 613 614 #define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xB4) 615 /* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ 616 /*description: .*/ 617 #define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27)) 618 #define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27)) 619 #define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1 620 #define SYSCON_NOBYPASS_CPU_ISO_RST_S 27 621 /* SYSCON_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ 622 /*description: .*/ 623 #define SYSCON_RETENTION_CPU_LINK_ADDR 0x07FFFFFF 624 #define SYSCON_RETENTION_CPU_LINK_ADDR_M ((SYSCON_RETENTION_CPU_LINK_ADDR_V)<<(SYSCON_RETENTION_CPU_LINK_ADDR_S)) 625 #define SYSCON_RETENTION_CPU_LINK_ADDR_V 0x7FFFFFF 626 #define SYSCON_RETENTION_CPU_LINK_ADDR_S 0 627 628 #define SYSCON_RETENTION_CTRL1_REG (DR_REG_SYSCON_BASE + 0xB8) 629 /* SYSCON_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ 630 /*description: .*/ 631 #define SYSCON_RETENTION_TAG_LINK_ADDR 0x07FFFFFF 632 #define SYSCON_RETENTION_TAG_LINK_ADDR_M ((SYSCON_RETENTION_TAG_LINK_ADDR_V)<<(SYSCON_RETENTION_TAG_LINK_ADDR_S)) 633 #define SYSCON_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF 634 #define SYSCON_RETENTION_TAG_LINK_ADDR_S 0 635 636 #define SYSCON_RETENTION_CTRL2_REG (DR_REG_SYSCON_BASE + 0xBC) 637 /* SYSCON_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 638 /*description: .*/ 639 #define SYSCON_RET_ICACHE_ENABLE (BIT(31)) 640 #define SYSCON_RET_ICACHE_ENABLE_M (BIT(31)) 641 #define SYSCON_RET_ICACHE_ENABLE_V 0x1 642 #define SYSCON_RET_ICACHE_ENABLE_S 31 643 /* SYSCON_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */ 644 /*description: .*/ 645 #define SYSCON_RET_ICACHE_START_POINT 0x000000FF 646 #define SYSCON_RET_ICACHE_START_POINT_M ((SYSCON_RET_ICACHE_START_POINT_V)<<(SYSCON_RET_ICACHE_START_POINT_S)) 647 #define SYSCON_RET_ICACHE_START_POINT_V 0xFF 648 #define SYSCON_RET_ICACHE_START_POINT_S 22 649 /* SYSCON_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */ 650 /*description: .*/ 651 #define SYSCON_RET_ICACHE_VLD_SIZE 0x000000FF 652 #define SYSCON_RET_ICACHE_VLD_SIZE_M ((SYSCON_RET_ICACHE_VLD_SIZE_V)<<(SYSCON_RET_ICACHE_VLD_SIZE_S)) 653 #define SYSCON_RET_ICACHE_VLD_SIZE_V 0xFF 654 #define SYSCON_RET_ICACHE_VLD_SIZE_S 13 655 /* SYSCON_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */ 656 /*description: .*/ 657 #define SYSCON_RET_ICACHE_SIZE 0x000000FF 658 #define SYSCON_RET_ICACHE_SIZE_M ((SYSCON_RET_ICACHE_SIZE_V)<<(SYSCON_RET_ICACHE_SIZE_S)) 659 #define SYSCON_RET_ICACHE_SIZE_V 0xFF 660 #define SYSCON_RET_ICACHE_SIZE_S 4 661 662 #define SYSCON_RETENTION_CTRL3_REG (DR_REG_SYSCON_BASE + 0xC0) 663 /* SYSCON_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 664 /*description: .*/ 665 #define SYSCON_RET_DCACHE_ENABLE (BIT(31)) 666 #define SYSCON_RET_DCACHE_ENABLE_M (BIT(31)) 667 #define SYSCON_RET_DCACHE_ENABLE_V 0x1 668 #define SYSCON_RET_DCACHE_ENABLE_S 31 669 /* SYSCON_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */ 670 /*description: .*/ 671 #define SYSCON_RET_DCACHE_START_POINT 0x000001FF 672 #define SYSCON_RET_DCACHE_START_POINT_M ((SYSCON_RET_DCACHE_START_POINT_V)<<(SYSCON_RET_DCACHE_START_POINT_S)) 673 #define SYSCON_RET_DCACHE_START_POINT_V 0x1FF 674 #define SYSCON_RET_DCACHE_START_POINT_S 22 675 /* SYSCON_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */ 676 /*description: .*/ 677 #define SYSCON_RET_DCACHE_VLD_SIZE 0x000001FF 678 #define SYSCON_RET_DCACHE_VLD_SIZE_M ((SYSCON_RET_DCACHE_VLD_SIZE_V)<<(SYSCON_RET_DCACHE_VLD_SIZE_S)) 679 #define SYSCON_RET_DCACHE_VLD_SIZE_V 0x1FF 680 #define SYSCON_RET_DCACHE_VLD_SIZE_S 13 681 /* SYSCON_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */ 682 /*description: .*/ 683 #define SYSCON_RET_DCACHE_SIZE 0x000001FF 684 #define SYSCON_RET_DCACHE_SIZE_M ((SYSCON_RET_DCACHE_SIZE_V)<<(SYSCON_RET_DCACHE_SIZE_S)) 685 #define SYSCON_RET_DCACHE_SIZE_V 0x1FF 686 #define SYSCON_RET_DCACHE_SIZE_S 4 687 688 #define SYSCON_RETENTION_CTRL4_REG (DR_REG_SYSCON_BASE + 0xC4) 689 /* SYSCON_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */ 690 /*description: .*/ 691 #define SYSCON_RETENTION_INV_CFG 0xFFFFFFFF 692 #define SYSCON_RETENTION_INV_CFG_M ((SYSCON_RETENTION_INV_CFG_V)<<(SYSCON_RETENTION_INV_CFG_S)) 693 #define SYSCON_RETENTION_INV_CFG_V 0xFFFFFFFF 694 #define SYSCON_RETENTION_INV_CFG_S 0 695 696 #define SYSCON_RETENTION_CTRL5_REG (DR_REG_SYSCON_BASE + 0xC8) 697 /* SYSCON_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 698 /*description: .*/ 699 #define SYSCON_RETENTION_DISABLE (BIT(0)) 700 #define SYSCON_RETENTION_DISABLE_M (BIT(0)) 701 #define SYSCON_RETENTION_DISABLE_V 0x1 702 #define SYSCON_RETENTION_DISABLE_S 0 703 704 #define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) 705 /* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */ 706 /*description: Version control.*/ 707 #define SYSCON_DATE 0xFFFFFFFF 708 #define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) 709 #define SYSCON_DATE_V 0xFFFFFFFF 710 #define SYSCON_DATE_S 0 711 712 713 #ifdef __cplusplus 714 } 715 #endif 716 717 718 719 #endif /*_SOC_SYSCON_REG_H_ */ 720
