1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SYSCON_REG_H_ 15 #define _SOC_SYSCON_REG_H_ 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 #include "soc.h" 22 #define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) 23 /* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ 24 /*description: */ 25 #define SYSCON_RST_TICK_CNT (BIT(12)) 26 #define SYSCON_RST_TICK_CNT_M (BIT(12)) 27 #define SYSCON_RST_TICK_CNT_V 0x1 28 #define SYSCON_RST_TICK_CNT_S 12 29 /* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 30 /*description: */ 31 #define SYSCON_CLK_EN (BIT(11)) 32 #define SYSCON_CLK_EN_M (BIT(11)) 33 #define SYSCON_CLK_EN_V 0x1 34 #define SYSCON_CLK_EN_S 11 35 /* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 36 /*description: */ 37 #define SYSCON_CLK_320M_EN (BIT(10)) 38 #define SYSCON_CLK_320M_EN_M (BIT(10)) 39 #define SYSCON_CLK_320M_EN_V 0x1 40 #define SYSCON_CLK_320M_EN_S 10 41 /* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ 42 /*description: */ 43 #define SYSCON_PRE_DIV_CNT 0x000003FF 44 #define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S)) 45 #define SYSCON_PRE_DIV_CNT_V 0x3FF 46 #define SYSCON_PRE_DIV_CNT_S 0 47 48 #define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004) 49 /* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ 50 /*description: */ 51 #define SYSCON_TICK_ENABLE (BIT(16)) 52 #define SYSCON_TICK_ENABLE_M (BIT(16)) 53 #define SYSCON_TICK_ENABLE_V 0x1 54 #define SYSCON_TICK_ENABLE_S 16 55 /* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ 56 /*description: */ 57 #define SYSCON_CK8M_TICK_NUM 0x000000FF 58 #define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S)) 59 #define SYSCON_CK8M_TICK_NUM_V 0xFF 60 #define SYSCON_CK8M_TICK_NUM_S 8 61 /* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ 62 /*description: */ 63 #define SYSCON_XTAL_TICK_NUM 0x000000FF 64 #define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S)) 65 #define SYSCON_XTAL_TICK_NUM_V 0xFF 66 #define SYSCON_XTAL_TICK_NUM_S 0 67 68 #define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008) 69 /* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 70 /*description: */ 71 #define SYSCON_CLK_XTAL_OEN (BIT(10)) 72 #define SYSCON_CLK_XTAL_OEN_M (BIT(10)) 73 #define SYSCON_CLK_XTAL_OEN_V 0x1 74 #define SYSCON_CLK_XTAL_OEN_S 10 75 /* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 76 /*description: */ 77 #define SYSCON_CLK40X_BB_OEN (BIT(9)) 78 #define SYSCON_CLK40X_BB_OEN_M (BIT(9)) 79 #define SYSCON_CLK40X_BB_OEN_V 0x1 80 #define SYSCON_CLK40X_BB_OEN_S 9 81 /* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ 82 /*description: */ 83 #define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) 84 #define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) 85 #define SYSCON_CLK_DAC_CPU_OEN_V 0x1 86 #define SYSCON_CLK_DAC_CPU_OEN_S 8 87 /* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ 88 /*description: */ 89 #define SYSCON_CLK_ADC_INF_OEN (BIT(7)) 90 #define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) 91 #define SYSCON_CLK_ADC_INF_OEN_V 0x1 92 #define SYSCON_CLK_ADC_INF_OEN_S 7 93 /* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 94 /*description: */ 95 #define SYSCON_CLK_320M_OEN (BIT(6)) 96 #define SYSCON_CLK_320M_OEN_M (BIT(6)) 97 #define SYSCON_CLK_320M_OEN_V 0x1 98 #define SYSCON_CLK_320M_OEN_S 6 99 /* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 100 /*description: */ 101 #define SYSCON_CLK160_OEN (BIT(5)) 102 #define SYSCON_CLK160_OEN_M (BIT(5)) 103 #define SYSCON_CLK160_OEN_V 0x1 104 #define SYSCON_CLK160_OEN_S 5 105 /* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ 106 /*description: */ 107 #define SYSCON_CLK80_OEN (BIT(4)) 108 #define SYSCON_CLK80_OEN_M (BIT(4)) 109 #define SYSCON_CLK80_OEN_V 0x1 110 #define SYSCON_CLK80_OEN_S 4 111 /* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 112 /*description: */ 113 #define SYSCON_CLK_BB_OEN (BIT(3)) 114 #define SYSCON_CLK_BB_OEN_M (BIT(3)) 115 #define SYSCON_CLK_BB_OEN_V 0x1 116 #define SYSCON_CLK_BB_OEN_S 3 117 /* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 118 /*description: */ 119 #define SYSCON_CLK44_OEN (BIT(2)) 120 #define SYSCON_CLK44_OEN_M (BIT(2)) 121 #define SYSCON_CLK44_OEN_V 0x1 122 #define SYSCON_CLK44_OEN_S 2 123 /* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 124 /*description: */ 125 #define SYSCON_CLK22_OEN (BIT(1)) 126 #define SYSCON_CLK22_OEN_M (BIT(1)) 127 #define SYSCON_CLK22_OEN_V 0x1 128 #define SYSCON_CLK22_OEN_S 1 129 /* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 130 /*description: */ 131 #define SYSCON_CLK20_OEN (BIT(0)) 132 #define SYSCON_CLK20_OEN_M (BIT(0)) 133 #define SYSCON_CLK20_OEN_V 0x1 134 #define SYSCON_CLK20_OEN_S 0 135 136 #define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C) 137 /* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 138 /*description: */ 139 #define SYSCON_WIFI_BB_CFG 0xFFFFFFFF 140 #define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S)) 141 #define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF 142 #define SYSCON_WIFI_BB_CFG_S 0 143 144 #define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010) 145 /* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 146 /*description: */ 147 #define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF 148 #define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S)) 149 #define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF 150 #define SYSCON_WIFI_BB_CFG_2_S 0 151 152 #define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014) 153 /* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 154 /*description: */ 155 #define SYSCON_WIFI_CLK_EN 0xFFFFFFFF 156 #define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S)) 157 #define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF 158 #define SYSCON_WIFI_CLK_EN_S 0 159 160 #define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018) 161 /* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 162 /*description: */ 163 #define SYSCON_WIFI_RST 0xFFFFFFFF 164 #define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S)) 165 #define SYSCON_WIFI_RST_V 0xFFFFFFFF 166 #define SYSCON_WIFI_RST_S 0 167 168 #define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG 169 /* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ 170 /*description: */ 171 #define SYSTEM_WIFI_CLK_EN 0x00FB9FCF 172 #define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S)) 173 #define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF 174 #define SYSTEM_WIFI_CLK_EN_S 0 175 176 /* Mask for all Wifi clock bits, 6 */ 177 #define SYSTEM_WIFI_CLK_WIFI_EN 0x0 178 #define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S)) 179 #define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0 180 #define SYSTEM_WIFI_CLK_WIFI_EN_S 0 181 /* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */ 182 #define SYSTEM_WIFI_CLK_BT_EN 0x0 183 #define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S)) 184 #define SYSTEM_WIFI_CLK_BT_EN_V 0x0 185 #define SYSTEM_WIFI_CLK_BT_EN_S 0 186 /* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */ 187 #define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F 188 189 /* Digital team to check */ 190 //bluetooth baseband bit11 191 #define SYSTEM_BT_BASEBAND_EN BIT(11) 192 //bluetooth LC bit16 and bit17 193 #define SYSTEM_BT_LC_EN (BIT(16)|BIT(17)) 194 195 /* Remaining single bit clock masks */ 196 #define SYSTEM_WIFI_CLK_SDIOSLAVE_EN BIT(4) 197 #define SYSTEM_WIFI_CLK_UNUSED_BIT5 BIT(5) 198 #define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12) 199 #define SYSTEM_WIFI_CLK_EMAC_EN BIT(14) 200 #define SYSTEM_WIFI_CLK_RNG_EN BIT(15) 201 202 #define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG 203 #define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG 204 /* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 205 /*description: */ 206 #define SYSTEM_BB_RST BIT(0) 207 #define SYSTEM_FE_RST BIT(1) 208 #define SYSTEM_MAC_RST BIT(2) 209 #define SYSTEM_BT_RST BIT(3) 210 #define SYSTEM_BTMAC_RST BIT(4) 211 #define SYSTEM_SDIO_RST BIT(5) 212 #define SYSTEM_EMAC_RST BIT(7) 213 #define SYSTEM_MACPWR_RST BIT(8) 214 #define SYSTEM_RW_BTMAC_RST BIT(9) 215 #define SYSTEM_RW_BTLP_RST BIT(10) 216 #define BLE_REG_REST_BIT BIT(11) 217 #define BLE_PWR_REG_REST_BIT BIT(12) 218 #define BLE_BB_REG_REST_BIT BIT(13) 219 220 #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) 221 /* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 222 /*description: */ 223 #define SYSCON_PERI_IO_SWAP 0x000000FF 224 #define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S)) 225 #define SYSCON_PERI_IO_SWAP_V 0xFF 226 #define SYSCON_PERI_IO_SWAP_S 0 227 228 #define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020) 229 /* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ 230 /*description: */ 231 #define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) 232 #define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) 233 #define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 234 #define SYSCON_EXT_MEM_PMS_LOCK_S 0 235 236 #define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x028) 237 /* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 238 /*description: */ 239 #define SYSCON_FLASH_ACE0_ATTR 0x00000003 240 #define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S)) 241 #define SYSCON_FLASH_ACE0_ATTR_V 0x3 242 #define SYSCON_FLASH_ACE0_ATTR_S 0 243 244 #define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C) 245 /* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 246 /*description: */ 247 #define SYSCON_FLASH_ACE1_ATTR 0x00000003 248 #define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S)) 249 #define SYSCON_FLASH_ACE1_ATTR_V 0x3 250 #define SYSCON_FLASH_ACE1_ATTR_S 0 251 252 #define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x030) 253 /* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 254 /*description: */ 255 #define SYSCON_FLASH_ACE2_ATTR 0x00000003 256 #define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S)) 257 #define SYSCON_FLASH_ACE2_ATTR_V 0x3 258 #define SYSCON_FLASH_ACE2_ATTR_S 0 259 260 #define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x034) 261 /* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */ 262 /*description: */ 263 #define SYSCON_FLASH_ACE3_ATTR 0x00000003 264 #define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S)) 265 #define SYSCON_FLASH_ACE3_ATTR_V 0x3 266 #define SYSCON_FLASH_ACE3_ATTR_S 0 267 268 #define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x038) 269 /* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 270 /*description: */ 271 #define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF 272 #define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S)) 273 #define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF 274 #define SYSCON_FLASH_ACE0_ADDR_S_S 0 275 276 #define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C) 277 /* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */ 278 /*description: */ 279 #define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF 280 #define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S)) 281 #define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF 282 #define SYSCON_FLASH_ACE1_ADDR_S_S 0 283 284 #define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x040) 285 /* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */ 286 /*description: */ 287 #define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF 288 #define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S)) 289 #define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF 290 #define SYSCON_FLASH_ACE2_ADDR_S_S 0 291 292 #define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x044) 293 /* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */ 294 /*description: */ 295 #define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF 296 #define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S)) 297 #define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF 298 #define SYSCON_FLASH_ACE3_ADDR_S_S 0 299 300 #define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x048) 301 /* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 302 /*description: */ 303 #define SYSCON_FLASH_ACE0_SIZE 0x00001FFF 304 #define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S)) 305 #define SYSCON_FLASH_ACE0_SIZE_V 0x1FFF 306 #define SYSCON_FLASH_ACE0_SIZE_S 0 307 308 #define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C) 309 /* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 310 /*description: */ 311 #define SYSCON_FLASH_ACE1_SIZE 0x00001FFF 312 #define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S)) 313 #define SYSCON_FLASH_ACE1_SIZE_V 0x1FFF 314 #define SYSCON_FLASH_ACE1_SIZE_S 0 315 316 #define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x050) 317 /* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 318 /*description: */ 319 #define SYSCON_FLASH_ACE2_SIZE 0x00001FFF 320 #define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S)) 321 #define SYSCON_FLASH_ACE2_SIZE_V 0x1FFF 322 #define SYSCON_FLASH_ACE2_SIZE_S 0 323 324 #define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x054) 325 /* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */ 326 /*description: */ 327 #define SYSCON_FLASH_ACE3_SIZE 0x00001FFF 328 #define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S)) 329 #define SYSCON_FLASH_ACE3_SIZE_V 0x1FFF 330 #define SYSCON_FLASH_ACE3_SIZE_S 0 331 332 #define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x088) 333 /* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ 334 /*description: */ 335 #define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F 336 #define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S)) 337 #define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F 338 #define SYSCON_SPI_MEM_REJECT_CDE_S 2 339 /* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 340 /*description: */ 341 #define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) 342 #define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) 343 #define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 344 #define SYSCON_SPI_MEM_REJECT_CLR_S 1 345 /* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ 346 /*description: */ 347 #define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) 348 #define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) 349 #define SYSCON_SPI_MEM_REJECT_INT_V 0x1 350 #define SYSCON_SPI_MEM_REJECT_INT_S 0 351 352 #define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x08C) 353 /* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 354 /*description: */ 355 #define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF 356 #define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S)) 357 #define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF 358 #define SYSCON_SPI_MEM_REJECT_ADDR_S 0 359 360 #define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x090) 361 /* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 362 /*description: */ 363 #define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) 364 #define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) 365 #define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 366 #define SYSCON_SDIO_WIN_ACCESS_EN_S 0 367 368 #define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x094) 369 /* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 370 /*description: */ 371 #define SYSCON_REDCY_ANDOR (BIT(31)) 372 #define SYSCON_REDCY_ANDOR_M (BIT(31)) 373 #define SYSCON_REDCY_ANDOR_V 0x1 374 #define SYSCON_REDCY_ANDOR_S 31 375 /* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 376 /*description: */ 377 #define SYSCON_REDCY_SIG0 0x7FFFFFFF 378 #define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S)) 379 #define SYSCON_REDCY_SIG0_V 0x7FFFFFFF 380 #define SYSCON_REDCY_SIG0_S 0 381 382 #define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x098) 383 /* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ 384 /*description: */ 385 #define SYSCON_REDCY_NANDOR (BIT(31)) 386 #define SYSCON_REDCY_NANDOR_M (BIT(31)) 387 #define SYSCON_REDCY_NANDOR_V 0x1 388 #define SYSCON_REDCY_NANDOR_S 31 389 /* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ 390 /*description: */ 391 #define SYSCON_REDCY_SIG1 0x7FFFFFFF 392 #define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S)) 393 #define SYSCON_REDCY_SIG1_V 0x7FFFFFFF 394 #define SYSCON_REDCY_SIG1_S 0 395 396 #define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x09C) 397 /* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 398 /*description: */ 399 #define SYSCON_DC_MEM_FORCE_PD (BIT(5)) 400 #define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) 401 #define SYSCON_DC_MEM_FORCE_PD_V 0x1 402 #define SYSCON_DC_MEM_FORCE_PD_S 5 403 /* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 404 /*description: */ 405 #define SYSCON_DC_MEM_FORCE_PU (BIT(4)) 406 #define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) 407 #define SYSCON_DC_MEM_FORCE_PU_V 0x1 408 #define SYSCON_DC_MEM_FORCE_PU_S 4 409 /* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 410 /*description: */ 411 #define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) 412 #define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) 413 #define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 414 #define SYSCON_PBUS_MEM_FORCE_PD_S 3 415 /* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 416 /*description: */ 417 #define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) 418 #define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) 419 #define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 420 #define SYSCON_PBUS_MEM_FORCE_PU_S 2 421 /* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 422 /*description: */ 423 #define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) 424 #define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) 425 #define SYSCON_AGC_MEM_FORCE_PD_V 0x1 426 #define SYSCON_AGC_MEM_FORCE_PD_S 1 427 /* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ 428 /*description: */ 429 #define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) 430 #define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) 431 #define SYSCON_AGC_MEM_FORCE_PU_V 0x1 432 #define SYSCON_AGC_MEM_FORCE_PU_S 0 433 434 #define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0x0A0) 435 /* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ 436 /*description: */ 437 #define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27)) 438 #define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27)) 439 #define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1 440 #define SYSCON_NOBYPASS_CPU_ISO_RST_S 27 441 /* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ 442 /*description: */ 443 #define SYSCON_RETENTION_LINK_ADDR 0x07FFFFFF 444 #define SYSCON_RETENTION_LINK_ADDR_M ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S)) 445 #define SYSCON_RETENTION_LINK_ADDR_V 0x7FFFFFF 446 #define SYSCON_RETENTION_LINK_ADDR_S 0 447 448 #define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0x0A4) 449 /* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ 450 /*description: */ 451 #define SYSCON_SRAM_CLKGATE_FORCE_ON 0x0000000F 452 #define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S)) 453 #define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0xF 454 #define SYSCON_SRAM_CLKGATE_FORCE_ON_S 2 455 /* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ 456 /*description: */ 457 #define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000003 458 #define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S)) 459 #define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x3 460 #define SYSCON_ROM_CLKGATE_FORCE_ON_S 0 461 462 #define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0x0A8) 463 /* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */ 464 /*description: */ 465 #define SYSCON_SRAM_POWER_DOWN 0x0000000F 466 #define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S)) 467 #define SYSCON_SRAM_POWER_DOWN_V 0xF 468 #define SYSCON_SRAM_POWER_DOWN_S 2 469 /* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 470 /*description: */ 471 #define SYSCON_ROM_POWER_DOWN 0x00000003 472 #define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S)) 473 #define SYSCON_ROM_POWER_DOWN_V 0x3 474 #define SYSCON_ROM_POWER_DOWN_S 0 475 476 #define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0x0AC) 477 /* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */ 478 /*description: */ 479 #define SYSCON_SRAM_POWER_UP 0x0000000F 480 #define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S)) 481 #define SYSCON_SRAM_POWER_UP_V 0xF 482 #define SYSCON_SRAM_POWER_UP_S 2 483 /* SYSCON_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ 484 /*description: */ 485 #define SYSCON_ROM_POWER_UP 0x00000003 486 #define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S)) 487 #define SYSCON_ROM_POWER_UP_V 0x3 488 #define SYSCON_ROM_POWER_UP_S 0 489 490 #define SYSCON_RND_DATA_REG (DR_REG_SYSCON_BASE + 0x0B0) 491 /* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 492 /*description: */ 493 #define SYSCON_RND_DATA 0xFFFFFFFF 494 #define SYSCON_RND_DATA_M ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S)) 495 #define SYSCON_RND_DATA_V 0xFFFFFFFF 496 #define SYSCON_RND_DATA_S 0 497 498 #define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0x0B4) 499 /* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ 500 /*description: */ 501 #define SYSCON_PERI_BACKUP_ENA (BIT(31)) 502 #define SYSCON_PERI_BACKUP_ENA_M (BIT(31)) 503 #define SYSCON_PERI_BACKUP_ENA_V 0x1 504 #define SYSCON_PERI_BACKUP_ENA_S 31 505 /* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */ 506 /*description: */ 507 #define SYSCON_PERI_BACKUP_TO_MEM (BIT(30)) 508 #define SYSCON_PERI_BACKUP_TO_MEM_M (BIT(30)) 509 #define SYSCON_PERI_BACKUP_TO_MEM_V 0x1 510 #define SYSCON_PERI_BACKUP_TO_MEM_S 30 511 /* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */ 512 /*description: */ 513 #define SYSCON_PERI_BACKUP_START (BIT(29)) 514 #define SYSCON_PERI_BACKUP_START_M (BIT(29)) 515 #define SYSCON_PERI_BACKUP_START_V 0x1 516 #define SYSCON_PERI_BACKUP_START_S 29 517 /* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */ 518 /*description: */ 519 #define SYSCON_PERI_BACKUP_SIZE 0x000003FF 520 #define SYSCON_PERI_BACKUP_SIZE_M ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S)) 521 #define SYSCON_PERI_BACKUP_SIZE_V 0x3FF 522 #define SYSCON_PERI_BACKUP_SIZE_S 19 523 /* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */ 524 /*description: */ 525 #define SYSCON_PERI_BACKUP_TOUT_THRES 0x000003FF 526 #define SYSCON_PERI_BACKUP_TOUT_THRES_M ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S)) 527 #define SYSCON_PERI_BACKUP_TOUT_THRES_V 0x3FF 528 #define SYSCON_PERI_BACKUP_TOUT_THRES_S 9 529 /* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */ 530 /*description: */ 531 #define SYSCON_PERI_BACKUP_BURST_LIMIT 0x0000001F 532 #define SYSCON_PERI_BACKUP_BURST_LIMIT_M ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S)) 533 #define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x1F 534 #define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4 535 /* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */ 536 /*description: */ 537 #define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000003 538 #define SYSCON_PERI_BACKUP_FLOW_ERR_M ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S)) 539 #define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x3 540 #define SYSCON_PERI_BACKUP_FLOW_ERR_S 1 541 542 #define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0x0B8) 543 /* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ 544 /*description: */ 545 #define SYSCON_BACKUP_APB_START_ADDR 0xFFFFFFFF 546 #define SYSCON_BACKUP_APB_START_ADDR_M ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S)) 547 #define SYSCON_BACKUP_APB_START_ADDR_V 0xFFFFFFFF 548 #define SYSCON_BACKUP_APB_START_ADDR_S 0 549 550 #define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0x0BC) 551 /* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ 552 /*description: */ 553 #define SYSCON_BACKUP_MEM_START_ADDR 0xFFFFFFFF 554 #define SYSCON_BACKUP_MEM_START_ADDR_M ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S)) 555 #define SYSCON_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF 556 #define SYSCON_BACKUP_MEM_START_ADDR_S 0 557 558 #define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0x0C0) 559 /* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */ 560 /*description: */ 561 #define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1)) 562 #define SYSCON_PERI_BACKUP_ERR_INT_RAW_M (BIT(1)) 563 #define SYSCON_PERI_BACKUP_ERR_INT_RAW_V 0x1 564 #define SYSCON_PERI_BACKUP_ERR_INT_RAW_S 1 565 /* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */ 566 /*description: */ 567 #define SYSCON_PERI_BACKUP_DONE_INT_RAW (BIT(0)) 568 #define SYSCON_PERI_BACKUP_DONE_INT_RAW_M (BIT(0)) 569 #define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x1 570 #define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0 571 572 #define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0x0C4) 573 /* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */ 574 /*description: */ 575 #define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1)) 576 #define SYSCON_PERI_BACKUP_ERR_INT_ST_M (BIT(1)) 577 #define SYSCON_PERI_BACKUP_ERR_INT_ST_V 0x1 578 #define SYSCON_PERI_BACKUP_ERR_INT_ST_S 1 579 /* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */ 580 /*description: */ 581 #define SYSCON_PERI_BACKUP_DONE_INT_ST (BIT(0)) 582 #define SYSCON_PERI_BACKUP_DONE_INT_ST_M (BIT(0)) 583 #define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x1 584 #define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0 585 586 #define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0x0C8) 587 /* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */ 588 /*description: */ 589 #define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1)) 590 #define SYSCON_PERI_BACKUP_ERR_INT_ENA_M (BIT(1)) 591 #define SYSCON_PERI_BACKUP_ERR_INT_ENA_V 0x1 592 #define SYSCON_PERI_BACKUP_ERR_INT_ENA_S 1 593 /* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */ 594 /*description: */ 595 #define SYSCON_PERI_BACKUP_DONE_INT_ENA (BIT(0)) 596 #define SYSCON_PERI_BACKUP_DONE_INT_ENA_M (BIT(0)) 597 #define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x1 598 #define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0 599 600 #define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0x0D0) 601 /* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */ 602 /*description: */ 603 #define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1)) 604 #define SYSCON_PERI_BACKUP_ERR_INT_CLR_M (BIT(1)) 605 #define SYSCON_PERI_BACKUP_ERR_INT_CLR_V 0x1 606 #define SYSCON_PERI_BACKUP_ERR_INT_CLR_S 1 607 /* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */ 608 /*description: */ 609 #define SYSCON_PERI_BACKUP_DONE_INT_CLR (BIT(0)) 610 #define SYSCON_PERI_BACKUP_DONE_INT_CLR_M (BIT(0)) 611 #define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x1 612 #define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0 613 614 #define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) 615 /* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */ 616 /*description: Version control*/ 617 #define SYSCON_DATE 0xFFFFFFFF 618 #define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) 619 #define SYSCON_DATE_V 0xFFFFFFFF 620 #define SYSCON_DATE_S 0 621 622 #ifdef __cplusplus 623 } 624 #endif 625 626 627 628 #endif /*_SOC_SYSCON_REG_H_ */ 629
