Searched refs:SPI_CACHE_SCTRL_REG (Results 1 – 2 of 2) sorted by relevance
| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32/ |
| D | spiram_psram.c | 1045 …CLEAR_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_DIO_M); //disable dio mode for cach… in psram_cache_init()
1046 …SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_QIO_M); //enable qio mode for cache… in psram_cache_init()
1047 … SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable cache read command in psram_cache_init()
1048 …SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_WCMD_M); //enable cache write command in psram_cache_init()
1049 …SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_ADDR_BITLEN_V, 23, SPI_SRAM_ADDR_BITLEN_S); //w… in psram_cache_init()
1050 SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy in psram_cache_init()
1061 …SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + … in psram_cache_init()
1079 …SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + … in psram_cache_init()
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| /hal_espressif-3.6.0/components/soc/esp32/include/soc/ |
| D | spi_reg.h | 903 #define SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54) macro
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