Home
last modified time | relevance | path

Searched refs:SOC_CPU_CORES_NUM (Results 1 – 25 of 32) sorted by relevance

12

/hal_espressif-3.6.0/components/hal/esp32c3/include/hal/
Dsoc_ll.h26 const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M}; in soc_ll_stall_core()
27 const int rtc_cntl_c1_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_S}; in soc_ll_stall_core()
28 const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M}; in soc_ll_stall_core()
29 const int rtc_cntl_c0_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_S}; in soc_ll_stall_core()
39 const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M}; in soc_ll_unstall_core()
40 const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M}; in soc_ll_unstall_core()
/hal_espressif-3.6.0/components/hal/esp32h2/include/hal/
Dsoc_ll.h26 const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M}; in soc_ll_stall_core()
27 const int rtc_cntl_c1_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_S}; in soc_ll_stall_core()
28 const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M}; in soc_ll_stall_core()
29 const int rtc_cntl_c0_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_S}; in soc_ll_stall_core()
39 const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M}; in soc_ll_unstall_core()
40 const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M}; in soc_ll_unstall_core()
/hal_espressif-3.6.0/components/hal/esp32/include/hal/
Dsoc_ll.h27 …const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
28 …const int rtc_cntl_c1_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_S, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
29 …const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
30 …const int rtc_cntl_c0_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_S, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
40 …const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M, RTC_CNTL_SW_STALL_APP… in soc_ll_unstall_core()
41 …const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M, RTC_CNTL_SW_STALL_APP… in soc_ll_unstall_core()
/hal_espressif-3.6.0/components/hal/esp32s3/include/hal/
Dsoc_ll.h27 …const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
28 …const int rtc_cntl_c1_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_S, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
29 …const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
30 …const int rtc_cntl_c0_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_S, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
40 …const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M, RTC_CNTL_SW_STALL_APP… in soc_ll_unstall_core()
41 …const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M, RTC_CNTL_SW_STALL_APP… in soc_ll_unstall_core()
/hal_espressif-3.6.0/components/esp_system/
Dstartup.c80 #if !(SOC_CPU_CORES_NUM > 1) && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
104 static volatile bool s_system_inited[SOC_CPU_CORES_NUM] = { false };
106 const sys_startup_fn_t g_startup_fn[SOC_CPU_CORES_NUM] = { [0] = start_cpu0,
107 #if SOC_CPU_CORES_NUM > 1
108 [1 ... SOC_CPU_CORES_NUM - 1] = start_cpu_other_cores
363 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { in do_secondary_init()
418 #if SOC_CPU_CORES_NUM > 1 && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE in start_cpu0_default()
/hal_espressif-3.6.0/components/esp_system/port/
Dcpu_start.c135 static volatile bool s_cpu_up[SOC_CPU_CORES_NUM] = { false };
136 static volatile bool s_cpu_inited[SOC_CPU_CORES_NUM] = { false };
254 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { in start_other_core()
269 soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM];
424 #if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
633 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
Dpanic_handler.c52 void *g_exc_frames[SOC_CPU_CORES_NUM] = {NULL};
94 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
/hal_espressif-3.6.0/components/hal/include/hal/
Dsoc_hal.h30 #if SOC_CPU_CORES_NUM > 1
33 … for (uint32_t i = 0, cur = cpu_hal_get_core_id(); i < SOC_CPU_CORES_NUM; i++) { \
Dinterrupt_controller_types.h39 int_desc_flag_t cpuflags[SOC_CPU_CORES_NUM];
/hal_espressif-3.6.0/components/esp_hw_support/
Dcpu_util.c26 #if SOC_CPU_CORES_NUM > 1 in esp_cpu_stall()
33 #if SOC_CPU_CORES_NUM > 1 in esp_cpu_unstall()
Dintr_alloc.c96 static uint32_t non_iram_int_mask[SOC_CPU_CORES_NUM];
99 static uint32_t non_iram_int_disabled[SOC_CPU_CORES_NUM];
100 static bool non_iram_int_disabled_flag[SOC_CPU_CORES_NUM];
185 if (cpu>=SOC_CPU_CORES_NUM) return ESP_ERR_INVALID_ARG; in esp_intr_mark_shared()
203 if (cpu>=SOC_CPU_CORES_NUM) return ESP_ERR_INVALID_ARG; in esp_intr_reserve()
/hal_espressif-3.6.0/components/driver/test/
Dtest_dedicated_gpio.c145 SemaphoreHandle_t sem = xSemaphoreCreateCounting(SOC_CPU_CORES_NUM, 0);
147 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
156 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
/hal_espressif-3.6.0/components/freertos/port/
Dport_systick.c55 _Static_assert(SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the…
88 for (cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++) { in vPortSetupTimer()
/hal_espressif-3.6.0/components/hal/
Dsoc_hal.c26 #if SOC_CPU_CORES_NUM > 1
/hal_espressif-3.6.0/components/soc/include/soc/
Ddedic_gpio_periph.h33 } cores[SOC_CPU_CORES_NUM]; // Signals routed to/from GPIO matrix
/hal_espressif-3.6.0/components/newlib/
Dabort.c28 _Static_assert(SOC_CPU_CORES_NUM < 10, "abort() assumes number of cores is 1 to 9"); in abort()
/hal_espressif-3.6.0/components/esp_system/include/esp_private/
Dstartup_internal.h36 extern sys_startup_fn_t const g_startup_fn[SOC_CPU_CORES_NUM];
Dpanic_internal.h31 extern void *g_exc_frames[SOC_CPU_CORES_NUM];
/hal_espressif-3.6.0/tools/unit-test-app/components/test_utils/
Dccomp_timer_impl_riscv.c41 ccomp_timer_status_t s_status[SOC_CPU_CORES_NUM];
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dsoc_caps.h14 #define SOC_CPU_CORES_NUM 1 macro
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dsoc_caps.h8 #define SOC_CPU_CORES_NUM 1 macro
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dsoc_caps.h22 #define SOC_CPU_CORES_NUM 2 macro
/hal_espressif-3.6.0/components/esp_system/port/soc/esp32s3/
Dhighint_hdl.S41 ….space L4_INTR_STACK_SIZE*SOC_CPU_CORES_NUM /* This allocates stacks for each individual CPU.…
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dsoc_caps.h36 #define SOC_CPU_CORES_NUM 1 macro
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
Dsoc_caps.h65 #define SOC_CPU_CORES_NUM 2 macro

12