1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SENS_REG_H_ 15 #define _SOC_SENS_REG_H_ 16 17 18 #include "soc.h" 19 #define SENS_SAR_READ_CTRL_REG (DR_REG_SENS_BASE + 0x0000) 20 /* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */ 21 /*description: Invert SAR ADC1 data*/ 22 #define SENS_SAR1_DATA_INV (BIT(28)) 23 #define SENS_SAR1_DATA_INV_M (BIT(28)) 24 #define SENS_SAR1_DATA_INV_V 0x1 25 #define SENS_SAR1_DATA_INV_S 28 26 /* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[27] ;default: 1'd0 ; */ 27 /*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL*/ 28 #define SENS_SAR1_DIG_FORCE (BIT(27)) 29 #define SENS_SAR1_DIG_FORCE_M (BIT(27)) 30 #define SENS_SAR1_DIG_FORCE_V 0x1 31 #define SENS_SAR1_DIG_FORCE_S 27 32 /* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ 33 /*description: */ 34 #define SENS_SAR1_SAMPLE_NUM 0x000000FF 35 #define SENS_SAR1_SAMPLE_NUM_M ((SENS_SAR1_SAMPLE_NUM_V)<<(SENS_SAR1_SAMPLE_NUM_S)) 36 #define SENS_SAR1_SAMPLE_NUM_V 0xFF 37 #define SENS_SAR1_SAMPLE_NUM_S 19 38 /* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ 39 /*description: */ 40 #define SENS_SAR1_CLK_GATED (BIT(18)) 41 #define SENS_SAR1_CLK_GATED_M (BIT(18)) 42 #define SENS_SAR1_CLK_GATED_V 0x1 43 #define SENS_SAR1_CLK_GATED_S 18 44 /* SENS_SAR1_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */ 45 /*description: 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 46 11: for 12-bit width*/ 47 #define SENS_SAR1_SAMPLE_BIT 0x00000003 48 #define SENS_SAR1_SAMPLE_BIT_M ((SENS_SAR1_SAMPLE_BIT_V)<<(SENS_SAR1_SAMPLE_BIT_S)) 49 #define SENS_SAR1_SAMPLE_BIT_V 0x3 50 #define SENS_SAR1_SAMPLE_BIT_S 16 51 /* SENS_SAR1_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */ 52 /*description: sample cycles for SAR ADC1*/ 53 #define SENS_SAR1_SAMPLE_CYCLE 0x000000FF 54 #define SENS_SAR1_SAMPLE_CYCLE_M ((SENS_SAR1_SAMPLE_CYCLE_V)<<(SENS_SAR1_SAMPLE_CYCLE_S)) 55 #define SENS_SAR1_SAMPLE_CYCLE_V 0xFF 56 #define SENS_SAR1_SAMPLE_CYCLE_S 8 57 /* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ 58 /*description: clock divider*/ 59 #define SENS_SAR1_CLK_DIV 0x000000FF 60 #define SENS_SAR1_CLK_DIV_M ((SENS_SAR1_CLK_DIV_V)<<(SENS_SAR1_CLK_DIV_S)) 61 #define SENS_SAR1_CLK_DIV_V 0xFF 62 #define SENS_SAR1_CLK_DIV_S 0 63 64 #define SENS_SAR_READ_STATUS1_REG (DR_REG_SENS_BASE + 0x0004) 65 /* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 66 /*description: */ 67 #define SENS_SAR1_READER_STATUS 0xFFFFFFFF 68 #define SENS_SAR1_READER_STATUS_M ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S)) 69 #define SENS_SAR1_READER_STATUS_V 0xFFFFFFFF 70 #define SENS_SAR1_READER_STATUS_S 0 71 72 #define SENS_SAR_MEAS_WAIT1_REG (DR_REG_SENS_BASE + 0x0008) 73 /* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ 74 /*description: */ 75 #define SENS_SAR_AMP_WAIT2 0x0000FFFF 76 #define SENS_SAR_AMP_WAIT2_M ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S)) 77 #define SENS_SAR_AMP_WAIT2_V 0xFFFF 78 #define SENS_SAR_AMP_WAIT2_S 16 79 /* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ 80 /*description: */ 81 #define SENS_SAR_AMP_WAIT1 0x0000FFFF 82 #define SENS_SAR_AMP_WAIT1_M ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S)) 83 #define SENS_SAR_AMP_WAIT1_V 0xFFFF 84 #define SENS_SAR_AMP_WAIT1_S 0 85 86 #define SENS_SAR_MEAS_WAIT2_REG (DR_REG_SENS_BASE + 0x000c) 87 /* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[27:20] ;default: 8'd2 ; */ 88 /*description: */ 89 #define SENS_SAR2_RSTB_WAIT 0x000000FF 90 #define SENS_SAR2_RSTB_WAIT_M ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S)) 91 #define SENS_SAR2_RSTB_WAIT_V 0xFF 92 #define SENS_SAR2_RSTB_WAIT_S 20 93 /* SENS_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ 94 /*description: */ 95 #define SENS_FORCE_XPD_SAR 0x00000003 96 #define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S)) 97 #define SENS_FORCE_XPD_SAR_V 0x3 98 #define SENS_FORCE_XPD_SAR_S 18 99 #define SENS_FORCE_XPD_SAR_SW_M (BIT1) 100 #define SENS_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down 101 #define SENS_FORCE_XPD_SAR_PD 2 // Force power down 102 #define SENS_FORCE_XPD_SAR_PU 3 // Force power up 103 /* SENS_FORCE_XPD_AMP : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ 104 /*description: */ 105 #define SENS_FORCE_XPD_AMP 0x00000003 106 #define SENS_FORCE_XPD_AMP_M ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S)) 107 #define SENS_FORCE_XPD_AMP_V 0x3 108 #define SENS_FORCE_XPD_AMP_S 16 109 #define SENS_FORCE_XPD_AMP_FSM 0 // Use FSM to control power down 110 #define SENS_FORCE_XPD_AMP_PD 2 // Force power down 111 #define SENS_FORCE_XPD_AMP_PU 3 // Force power up 112 /* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ 113 /*description: */ 114 #define SENS_SAR_AMP_WAIT3 0x0000FFFF 115 #define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S)) 116 #define SENS_SAR_AMP_WAIT3_V 0xFFFF 117 #define SENS_SAR_AMP_WAIT3_S 0 118 119 #define SENS_SAR_MEAS_CTRL_REG (DR_REG_SENS_BASE + 0x0010) 120 /* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ 121 /*description: */ 122 #define SENS_SAR2_XPD_WAIT 0x000000FF 123 #define SENS_SAR2_XPD_WAIT_M ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S)) 124 #define SENS_SAR2_XPD_WAIT_V 0xFF 125 #define SENS_SAR2_XPD_WAIT_S 24 126 /* SENS_SAR_RSTB_FSM : R/W ;bitpos:[23:20] ;default: 4'b0000 ; */ 127 /*description: */ 128 #define SENS_SAR_RSTB_FSM 0x0000000F 129 #define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S)) 130 #define SENS_SAR_RSTB_FSM_V 0xF 131 #define SENS_SAR_RSTB_FSM_S 20 132 /* SENS_XPD_SAR_FSM : R/W ;bitpos:[19:16] ;default: 4'b0111 ; */ 133 /*description: */ 134 #define SENS_XPD_SAR_FSM 0x0000000F 135 #define SENS_XPD_SAR_FSM_M ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S)) 136 #define SENS_XPD_SAR_FSM_V 0xF 137 #define SENS_XPD_SAR_FSM_S 16 138 /* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */ 139 /*description: */ 140 #define SENS_AMP_SHORT_REF_GND_FSM 0x0000000F 141 #define SENS_AMP_SHORT_REF_GND_FSM_M ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S)) 142 #define SENS_AMP_SHORT_REF_GND_FSM_V 0xF 143 #define SENS_AMP_SHORT_REF_GND_FSM_S 12 144 /* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[11:8] ;default: 4'b0011 ; */ 145 /*description: */ 146 #define SENS_AMP_SHORT_REF_FSM 0x0000000F 147 #define SENS_AMP_SHORT_REF_FSM_M ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S)) 148 #define SENS_AMP_SHORT_REF_FSM_V 0xF 149 #define SENS_AMP_SHORT_REF_FSM_S 8 150 /* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[7:4] ;default: 4'b1000 ; */ 151 /*description: */ 152 #define SENS_AMP_RST_FB_FSM 0x0000000F 153 #define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S)) 154 #define SENS_AMP_RST_FB_FSM_V 0xF 155 #define SENS_AMP_RST_FB_FSM_S 4 156 /* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[3:0] ;default: 4'b1111 ; */ 157 /*description: */ 158 #define SENS_XPD_SAR_AMP_FSM 0x0000000F 159 #define SENS_XPD_SAR_AMP_FSM_M ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S)) 160 #define SENS_XPD_SAR_AMP_FSM_V 0xF 161 #define SENS_XPD_SAR_AMP_FSM_S 0 162 163 #define SENS_SAR_READ_STATUS2_REG (DR_REG_SENS_BASE + 0x0014) 164 /* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 165 /*description: */ 166 #define SENS_SAR2_READER_STATUS 0xFFFFFFFF 167 #define SENS_SAR2_READER_STATUS_M ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S)) 168 #define SENS_SAR2_READER_STATUS_V 0xFFFFFFFF 169 #define SENS_SAR2_READER_STATUS_S 0 170 171 #define SENS_ULP_CP_SLEEP_CYC0_REG (DR_REG_SENS_BASE + 0x0018) 172 /* SENS_SLEEP_CYCLES_S0 : R/W ;bitpos:[31:0] ;default: 32'd200 ; */ 173 /*description: sleep cycles for ULP-coprocessor timer*/ 174 #define SENS_SLEEP_CYCLES_S0 0xFFFFFFFF 175 #define SENS_SLEEP_CYCLES_S0_M ((SENS_SLEEP_CYCLES_S0_V)<<(SENS_SLEEP_CYCLES_S0_S)) 176 #define SENS_SLEEP_CYCLES_S0_V 0xFFFFFFFF 177 #define SENS_SLEEP_CYCLES_S0_S 0 178 179 #define SENS_ULP_CP_SLEEP_CYC1_REG (DR_REG_SENS_BASE + 0x001c) 180 /* SENS_SLEEP_CYCLES_S1 : R/W ;bitpos:[31:0] ;default: 32'd100 ; */ 181 /*description: */ 182 #define SENS_SLEEP_CYCLES_S1 0xFFFFFFFF 183 #define SENS_SLEEP_CYCLES_S1_M ((SENS_SLEEP_CYCLES_S1_V)<<(SENS_SLEEP_CYCLES_S1_S)) 184 #define SENS_SLEEP_CYCLES_S1_V 0xFFFFFFFF 185 #define SENS_SLEEP_CYCLES_S1_S 0 186 187 #define SENS_ULP_CP_SLEEP_CYC2_REG (DR_REG_SENS_BASE + 0x0020) 188 /* SENS_SLEEP_CYCLES_S2 : R/W ;bitpos:[31:0] ;default: 32'd50 ; */ 189 /*description: */ 190 #define SENS_SLEEP_CYCLES_S2 0xFFFFFFFF 191 #define SENS_SLEEP_CYCLES_S2_M ((SENS_SLEEP_CYCLES_S2_V)<<(SENS_SLEEP_CYCLES_S2_S)) 192 #define SENS_SLEEP_CYCLES_S2_V 0xFFFFFFFF 193 #define SENS_SLEEP_CYCLES_S2_S 0 194 195 #define SENS_ULP_CP_SLEEP_CYC3_REG (DR_REG_SENS_BASE + 0x0024) 196 /* SENS_SLEEP_CYCLES_S3 : R/W ;bitpos:[31:0] ;default: 32'd40 ; */ 197 /*description: */ 198 #define SENS_SLEEP_CYCLES_S3 0xFFFFFFFF 199 #define SENS_SLEEP_CYCLES_S3_M ((SENS_SLEEP_CYCLES_S3_V)<<(SENS_SLEEP_CYCLES_S3_S)) 200 #define SENS_SLEEP_CYCLES_S3_V 0xFFFFFFFF 201 #define SENS_SLEEP_CYCLES_S3_S 0 202 203 #define SENS_ULP_CP_SLEEP_CYC4_REG (DR_REG_SENS_BASE + 0x0028) 204 /* SENS_SLEEP_CYCLES_S4 : R/W ;bitpos:[31:0] ;default: 32'd20 ; */ 205 /*description: */ 206 #define SENS_SLEEP_CYCLES_S4 0xFFFFFFFF 207 #define SENS_SLEEP_CYCLES_S4_M ((SENS_SLEEP_CYCLES_S4_V)<<(SENS_SLEEP_CYCLES_S4_S)) 208 #define SENS_SLEEP_CYCLES_S4_V 0xFFFFFFFF 209 #define SENS_SLEEP_CYCLES_S4_S 0 210 211 #define SENS_SAR_START_FORCE_REG (DR_REG_SENS_BASE + 0x002c) 212 /* SENS_SAR2_PWDET_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ 213 /*description: N/A*/ 214 #define SENS_SAR2_PWDET_EN (BIT(24)) 215 #define SENS_SAR2_PWDET_EN_M (BIT(24)) 216 #define SENS_SAR2_PWDET_EN_V 0x1 217 #define SENS_SAR2_PWDET_EN_S 24 218 /* SENS_SAR1_STOP : R/W ;bitpos:[23] ;default: 1'b0 ; */ 219 /*description: stop SAR ADC1 conversion*/ 220 #define SENS_SAR1_STOP (BIT(23)) 221 #define SENS_SAR1_STOP_M (BIT(23)) 222 #define SENS_SAR1_STOP_V 0x1 223 #define SENS_SAR1_STOP_S 23 224 /* SENS_SAR2_STOP : R/W ;bitpos:[22] ;default: 1'b0 ; */ 225 /*description: stop SAR ADC2 conversion*/ 226 #define SENS_SAR2_STOP (BIT(22)) 227 #define SENS_SAR2_STOP_M (BIT(22)) 228 #define SENS_SAR2_STOP_V 0x1 229 #define SENS_SAR2_STOP_S 22 230 /* SENS_PC_INIT : R/W ;bitpos:[21:11] ;default: 11'b0 ; */ 231 /*description: initialized PC for ULP-coprocessor*/ 232 #define SENS_PC_INIT 0x000007FF 233 #define SENS_PC_INIT_M ((SENS_PC_INIT_V)<<(SENS_PC_INIT_S)) 234 #define SENS_PC_INIT_V 0x7FF 235 #define SENS_PC_INIT_S 11 236 /* SENS_SARCLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 237 /*description: */ 238 #define SENS_SARCLK_EN (BIT(10)) 239 #define SENS_SARCLK_EN_M (BIT(10)) 240 #define SENS_SARCLK_EN_V 0x1 241 #define SENS_SARCLK_EN_S 10 242 /* SENS_ULP_CP_START_TOP : R/W ;bitpos:[9] ;default: 1'b0 ; */ 243 /*description: Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top 244 = 1*/ 245 #define SENS_ULP_CP_START_TOP (BIT(9)) 246 #define SENS_ULP_CP_START_TOP_M (BIT(9)) 247 #define SENS_ULP_CP_START_TOP_V 0x1 248 #define SENS_ULP_CP_START_TOP_S 9 249 /* SENS_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[8] ;default: 1'b0 ; */ 250 /*description: 1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer*/ 251 #define SENS_ULP_CP_FORCE_START_TOP (BIT(8)) 252 #define SENS_ULP_CP_FORCE_START_TOP_M (BIT(8)) 253 #define SENS_ULP_CP_FORCE_START_TOP_V 0x1 254 #define SENS_ULP_CP_FORCE_START_TOP_S 8 255 /* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[7:5] ;default: 3'b0 ; */ 256 /*description: SAR2_PWDET_CCT PA power detector capacitance tuning.*/ 257 #define SENS_SAR2_PWDET_CCT 0x00000007 258 #define SENS_SAR2_PWDET_CCT_M ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S)) 259 #define SENS_SAR2_PWDET_CCT_V 0x7 260 #define SENS_SAR2_PWDET_CCT_S 5 261 /* SENS_SAR2_EN_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 262 /*description: SAR2_EN_TEST only active when reg_sar2_dig_force = 0*/ 263 #define SENS_SAR2_EN_TEST (BIT(4)) 264 #define SENS_SAR2_EN_TEST_M (BIT(4)) 265 #define SENS_SAR2_EN_TEST_V 0x1 266 #define SENS_SAR2_EN_TEST_S 4 267 /* SENS_SAR2_BIT_WIDTH : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ 268 /*description: 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/ 269 #define SENS_SAR2_BIT_WIDTH 0x00000003 270 #define SENS_SAR2_BIT_WIDTH_M ((SENS_SAR2_BIT_WIDTH_V)<<(SENS_SAR2_BIT_WIDTH_S)) 271 #define SENS_SAR2_BIT_WIDTH_V 0x3 272 #define SENS_SAR2_BIT_WIDTH_S 2 273 /* SENS_SAR1_BIT_WIDTH : R/W ;bitpos:[1:0] ;default: 2'b11 ; */ 274 /*description: 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/ 275 #define SENS_SAR1_BIT_WIDTH 0x00000003 276 #define SENS_SAR1_BIT_WIDTH_M ((SENS_SAR1_BIT_WIDTH_V)<<(SENS_SAR1_BIT_WIDTH_S)) 277 #define SENS_SAR1_BIT_WIDTH_V 0x3 278 #define SENS_SAR1_BIT_WIDTH_S 0 279 280 #define SENS_SAR_MEM_WR_CTRL_REG (DR_REG_SENS_BASE + 0x0030) 281 /* SENS_RTC_MEM_WR_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ 282 /*description: */ 283 #define SENS_RTC_MEM_WR_OFFST_CLR (BIT(22)) 284 #define SENS_RTC_MEM_WR_OFFST_CLR_M (BIT(22)) 285 #define SENS_RTC_MEM_WR_OFFST_CLR_V 0x1 286 #define SENS_RTC_MEM_WR_OFFST_CLR_S 22 287 /* SENS_MEM_WR_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ 288 /*description: */ 289 #define SENS_MEM_WR_ADDR_SIZE 0x000007FF 290 #define SENS_MEM_WR_ADDR_SIZE_M ((SENS_MEM_WR_ADDR_SIZE_V)<<(SENS_MEM_WR_ADDR_SIZE_S)) 291 #define SENS_MEM_WR_ADDR_SIZE_V 0x7FF 292 #define SENS_MEM_WR_ADDR_SIZE_S 11 293 /* SENS_MEM_WR_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ 294 /*description: */ 295 #define SENS_MEM_WR_ADDR_INIT 0x000007FF 296 #define SENS_MEM_WR_ADDR_INIT_M ((SENS_MEM_WR_ADDR_INIT_V)<<(SENS_MEM_WR_ADDR_INIT_S)) 297 #define SENS_MEM_WR_ADDR_INIT_V 0x7FF 298 #define SENS_MEM_WR_ADDR_INIT_S 0 299 300 #define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x0034) 301 /* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ 302 /*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ 303 #define SENS_SAR1_ATTEN 0xFFFFFFFF 304 #define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S)) 305 #define SENS_SAR1_ATTEN_V 0xFFFFFFFF 306 #define SENS_SAR1_ATTEN_S 0 307 #define SENS_SAR1_ATTEN_VAL_MASK 0x3 308 #define SENS_SAR2_ATTEN_VAL_MASK 0x3 309 310 #define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x0038) 311 /* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ 312 /*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/ 313 #define SENS_SAR2_ATTEN 0xFFFFFFFF 314 #define SENS_SAR2_ATTEN_M ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S)) 315 #define SENS_SAR2_ATTEN_V 0xFFFFFFFF 316 #define SENS_SAR2_ATTEN_S 0 317 318 #define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x003c) 319 /* SENS_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ 320 /*description: */ 321 #define SENS_MEAS_STATUS 0x000000FF 322 #define SENS_MEAS_STATUS_M ((SENS_MEAS_STATUS_V)<<(SENS_MEAS_STATUS_S)) 323 #define SENS_MEAS_STATUS_V 0xFF 324 #define SENS_MEAS_STATUS_S 22 325 /* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ 326 /*description: */ 327 #define SENS_I2C_SLAVE_ADDR0 0x000007FF 328 #define SENS_I2C_SLAVE_ADDR0_M ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S)) 329 #define SENS_I2C_SLAVE_ADDR0_V 0x7FF 330 #define SENS_I2C_SLAVE_ADDR0_S 11 331 /* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ 332 /*description: */ 333 #define SENS_I2C_SLAVE_ADDR1 0x000007FF 334 #define SENS_I2C_SLAVE_ADDR1_M ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S)) 335 #define SENS_I2C_SLAVE_ADDR1_V 0x7FF 336 #define SENS_I2C_SLAVE_ADDR1_S 0 337 338 #define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x0040) 339 /* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ 340 /*description: */ 341 #define SENS_I2C_SLAVE_ADDR2 0x000007FF 342 #define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S)) 343 #define SENS_I2C_SLAVE_ADDR2_V 0x7FF 344 #define SENS_I2C_SLAVE_ADDR2_S 11 345 /* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ 346 /*description: */ 347 #define SENS_I2C_SLAVE_ADDR3 0x000007FF 348 #define SENS_I2C_SLAVE_ADDR3_M ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S)) 349 #define SENS_I2C_SLAVE_ADDR3_V 0x7FF 350 #define SENS_I2C_SLAVE_ADDR3_S 0 351 352 #define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x0044) 353 /* SENS_TSENS_RDY_OUT : RO ;bitpos:[30] ;default: 1'h0 ; */ 354 /*description: indicate temperature sensor out ready*/ 355 #define SENS_TSENS_RDY_OUT (BIT(30)) 356 #define SENS_TSENS_RDY_OUT_M (BIT(30)) 357 #define SENS_TSENS_RDY_OUT_V 0x1 358 #define SENS_TSENS_RDY_OUT_S 30 359 /* SENS_TSENS_OUT : RO ;bitpos:[29:22] ;default: 8'h0 ; */ 360 /*description: temperature sensor data out*/ 361 #define SENS_TSENS_OUT 0x000000FF 362 #define SENS_TSENS_OUT_M ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S)) 363 #define SENS_TSENS_OUT_V 0xFF 364 #define SENS_TSENS_OUT_S 22 365 /* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ 366 /*description: */ 367 #define SENS_I2C_SLAVE_ADDR4 0x000007FF 368 #define SENS_I2C_SLAVE_ADDR4_M ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S)) 369 #define SENS_I2C_SLAVE_ADDR4_V 0x7FF 370 #define SENS_I2C_SLAVE_ADDR4_S 11 371 /* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ 372 /*description: */ 373 #define SENS_I2C_SLAVE_ADDR5 0x000007FF 374 #define SENS_I2C_SLAVE_ADDR5_M ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S)) 375 #define SENS_I2C_SLAVE_ADDR5_V 0x7FF 376 #define SENS_I2C_SLAVE_ADDR5_S 0 377 378 #define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x0048) 379 /* SENS_I2C_DONE : RO ;bitpos:[30] ;default: 1'h0 ; */ 380 /*description: indicate I2C done*/ 381 #define SENS_I2C_DONE (BIT(30)) 382 #define SENS_I2C_DONE_M (BIT(30)) 383 #define SENS_I2C_DONE_V 0x1 384 #define SENS_I2C_DONE_S 30 385 /* SENS_I2C_RDATA : RO ;bitpos:[29:22] ;default: 8'h0 ; */ 386 /*description: I2C read data*/ 387 #define SENS_I2C_RDATA 0x000000FF 388 #define SENS_I2C_RDATA_M ((SENS_I2C_RDATA_V)<<(SENS_I2C_RDATA_S)) 389 #define SENS_I2C_RDATA_V 0xFF 390 #define SENS_I2C_RDATA_S 22 391 /* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ 392 /*description: */ 393 #define SENS_I2C_SLAVE_ADDR6 0x000007FF 394 #define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S)) 395 #define SENS_I2C_SLAVE_ADDR6_V 0x7FF 396 #define SENS_I2C_SLAVE_ADDR6_S 11 397 /* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ 398 /*description: */ 399 #define SENS_I2C_SLAVE_ADDR7 0x000007FF 400 #define SENS_I2C_SLAVE_ADDR7_M ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S)) 401 #define SENS_I2C_SLAVE_ADDR7_V 0x7FF 402 #define SENS_I2C_SLAVE_ADDR7_S 0 403 404 #define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x004c) 405 /* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[26] ;default: 1'b0 ; */ 406 /*description: temperature sensor dump out only active when reg_tsens_power_up_force = 1*/ 407 #define SENS_TSENS_DUMP_OUT (BIT(26)) 408 #define SENS_TSENS_DUMP_OUT_M (BIT(26)) 409 #define SENS_TSENS_DUMP_OUT_V 0x1 410 #define SENS_TSENS_DUMP_OUT_S 26 411 /* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[25] ;default: 1'b0 ; */ 412 /*description: 1: dump out & power up controlled by SW 0: by FSM*/ 413 #define SENS_TSENS_POWER_UP_FORCE (BIT(25)) 414 #define SENS_TSENS_POWER_UP_FORCE_M (BIT(25)) 415 #define SENS_TSENS_POWER_UP_FORCE_V 0x1 416 #define SENS_TSENS_POWER_UP_FORCE_S 25 417 /* SENS_TSENS_POWER_UP : R/W ;bitpos:[24] ;default: 1'b0 ; */ 418 /*description: temperature sensor power up*/ 419 #define SENS_TSENS_POWER_UP (BIT(24)) 420 #define SENS_TSENS_POWER_UP_M (BIT(24)) 421 #define SENS_TSENS_POWER_UP_V 0x1 422 #define SENS_TSENS_POWER_UP_S 24 423 /* SENS_TSENS_CLK_DIV : R/W ;bitpos:[23:16] ;default: 8'd6 ; */ 424 /*description: temperature sensor clock divider*/ 425 #define SENS_TSENS_CLK_DIV 0x000000FF 426 #define SENS_TSENS_CLK_DIV_M ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S)) 427 #define SENS_TSENS_CLK_DIV_V 0xFF 428 #define SENS_TSENS_CLK_DIV_S 16 429 /* SENS_TSENS_IN_INV : R/W ;bitpos:[15] ;default: 1'b0 ; */ 430 /*description: invert temperature sensor data*/ 431 #define SENS_TSENS_IN_INV (BIT(15)) 432 #define SENS_TSENS_IN_INV_M (BIT(15)) 433 #define SENS_TSENS_IN_INV_V 0x1 434 #define SENS_TSENS_IN_INV_S 15 435 /* SENS_TSENS_CLK_GATED : R/W ;bitpos:[14] ;default: 1'b1 ; */ 436 /*description: */ 437 #define SENS_TSENS_CLK_GATED (BIT(14)) 438 #define SENS_TSENS_CLK_GATED_M (BIT(14)) 439 #define SENS_TSENS_CLK_GATED_V 0x1 440 #define SENS_TSENS_CLK_GATED_S 14 441 /* SENS_TSENS_CLK_INV : R/W ;bitpos:[13] ;default: 1'b1 ; */ 442 /*description: */ 443 #define SENS_TSENS_CLK_INV (BIT(13)) 444 #define SENS_TSENS_CLK_INV_M (BIT(13)) 445 #define SENS_TSENS_CLK_INV_V 0x1 446 #define SENS_TSENS_CLK_INV_S 13 447 /* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ 448 /*description: */ 449 #define SENS_TSENS_XPD_FORCE (BIT(12)) 450 #define SENS_TSENS_XPD_FORCE_M (BIT(12)) 451 #define SENS_TSENS_XPD_FORCE_V 0x1 452 #define SENS_TSENS_XPD_FORCE_S 12 453 /* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ 454 /*description: */ 455 #define SENS_TSENS_XPD_WAIT 0x00000FFF 456 #define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S)) 457 #define SENS_TSENS_XPD_WAIT_V 0xFFF 458 #define SENS_TSENS_XPD_WAIT_S 0 459 460 #define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x0050) 461 /* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */ 462 /*description: 1: I2C started by SW 0: I2C started by FSM*/ 463 #define SENS_SAR_I2C_START_FORCE (BIT(29)) 464 #define SENS_SAR_I2C_START_FORCE_M (BIT(29)) 465 #define SENS_SAR_I2C_START_FORCE_V 0x1 466 #define SENS_SAR_I2C_START_FORCE_S 29 467 /* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */ 468 /*description: start I2C only active when reg_sar_i2c_start_force = 1*/ 469 #define SENS_SAR_I2C_START (BIT(28)) 470 #define SENS_SAR_I2C_START_M (BIT(28)) 471 #define SENS_SAR_I2C_START_V 0x1 472 #define SENS_SAR_I2C_START_S 28 473 /* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ 474 /*description: I2C control data only active when reg_sar_i2c_start_force = 1*/ 475 #define SENS_SAR_I2C_CTRL 0x0FFFFFFF 476 #define SENS_SAR_I2C_CTRL_M ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S)) 477 #define SENS_SAR_I2C_CTRL_V 0xFFFFFFF 478 #define SENS_SAR_I2C_CTRL_S 0 479 480 #define SENS_SAR_MEAS_START1_REG (DR_REG_SENS_BASE + 0x0054) 481 /* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 482 /*description: 1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 483 pad enable bitmap is controlled by ULP-coprocessor*/ 484 #define SENS_SAR1_EN_PAD_FORCE (BIT(31)) 485 #define SENS_SAR1_EN_PAD_FORCE_M (BIT(31)) 486 #define SENS_SAR1_EN_PAD_FORCE_V 0x1 487 #define SENS_SAR1_EN_PAD_FORCE_S 31 488 /* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ 489 /*description: SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1*/ 490 #define SENS_SAR1_EN_PAD 0x00000FFF 491 #define SENS_SAR1_EN_PAD_M ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S)) 492 #define SENS_SAR1_EN_PAD_V 0xFFF 493 #define SENS_SAR1_EN_PAD_S 19 494 /* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ 495 /*description: 1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 496 controller is started by ULP-coprocessor*/ 497 #define SENS_MEAS1_START_FORCE (BIT(18)) 498 #define SENS_MEAS1_START_FORCE_M (BIT(18)) 499 #define SENS_MEAS1_START_FORCE_V 0x1 500 #define SENS_MEAS1_START_FORCE_S 18 501 /* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ 502 /*description: SAR ADC1 controller (in RTC) starts conversion only active when 503 reg_meas1_start_force = 1*/ 504 #define SENS_MEAS1_START_SAR (BIT(17)) 505 #define SENS_MEAS1_START_SAR_M (BIT(17)) 506 #define SENS_MEAS1_START_SAR_V 0x1 507 #define SENS_MEAS1_START_SAR_S 17 508 /* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ 509 /*description: SAR ADC1 conversion done indication*/ 510 #define SENS_MEAS1_DONE_SAR (BIT(16)) 511 #define SENS_MEAS1_DONE_SAR_M (BIT(16)) 512 #define SENS_MEAS1_DONE_SAR_V 0x1 513 #define SENS_MEAS1_DONE_SAR_S 16 514 /* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ 515 /*description: SAR ADC1 data*/ 516 #define SENS_MEAS1_DATA_SAR 0x0000FFFF 517 #define SENS_MEAS1_DATA_SAR_M ((SENS_MEAS1_DATA_SAR_V)<<(SENS_MEAS1_DATA_SAR_S)) 518 #define SENS_MEAS1_DATA_SAR_V 0xFFFF 519 #define SENS_MEAS1_DATA_SAR_S 0 520 521 #define SENS_SAR_TOUCH_CTRL1_REG (DR_REG_SENS_BASE + 0x0058) 522 /* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */ 523 /*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled 524 by FSM in ULP-coprocessor*/ 525 #define SENS_HALL_PHASE_FORCE (BIT(27)) 526 #define SENS_HALL_PHASE_FORCE_M (BIT(27)) 527 #define SENS_HALL_PHASE_FORCE_V 0x1 528 #define SENS_HALL_PHASE_FORCE_S 27 529 /* SENS_XPD_HALL_FORCE : R/W ;bitpos:[26] ;default: 1'b0 ; */ 530 /*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by 531 FSM in ULP-coprocessor*/ 532 #define SENS_XPD_HALL_FORCE (BIT(26)) 533 #define SENS_XPD_HALL_FORCE_M (BIT(26)) 534 #define SENS_XPD_HALL_FORCE_V 0x1 535 #define SENS_XPD_HALL_FORCE_S 26 536 /* SENS_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ 537 /*description: 1: wakeup interrupt is generated if SET1 is "touched" 0: 538 wakeup interrupt is generated only if SET1 & SET2 is both "touched"*/ 539 #define SENS_TOUCH_OUT_1EN (BIT(25)) 540 #define SENS_TOUCH_OUT_1EN_M (BIT(25)) 541 #define SENS_TOUCH_OUT_1EN_V 0x1 542 #define SENS_TOUCH_OUT_1EN_S 25 543 /* SENS_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */ 544 /*description: 1: when the counter is greater then the threshold the touch 545 pad is considered as "touched" 0: when the counter is less than the threshold the touch pad is considered as "touched"*/ 546 #define SENS_TOUCH_OUT_SEL (BIT(24)) 547 #define SENS_TOUCH_OUT_SEL_M (BIT(24)) 548 #define SENS_TOUCH_OUT_SEL_V 0x1 549 #define SENS_TOUCH_OUT_SEL_S 24 550 /* SENS_TOUCH_XPD_WAIT : R/W ;bitpos:[23:16] ;default: 8'h4 ; */ 551 /*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ 552 #define SENS_TOUCH_XPD_WAIT 0x000000FF 553 #define SENS_TOUCH_XPD_WAIT_M ((SENS_TOUCH_XPD_WAIT_V)<<(SENS_TOUCH_XPD_WAIT_S)) 554 #define SENS_TOUCH_XPD_WAIT_V 0xFF 555 #define SENS_TOUCH_XPD_WAIT_S 16 556 /* SENS_TOUCH_MEAS_DELAY : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ 557 /*description: the meas length (in 8MHz)*/ 558 #define SENS_TOUCH_MEAS_DELAY 0x0000FFFF 559 #define SENS_TOUCH_MEAS_DELAY_M ((SENS_TOUCH_MEAS_DELAY_V)<<(SENS_TOUCH_MEAS_DELAY_S)) 560 #define SENS_TOUCH_MEAS_DELAY_V 0xFFFF 561 #define SENS_TOUCH_MEAS_DELAY_S 0 562 563 #define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x005c) 564 /* SENS_TOUCH_OUT_TH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ 565 /*description: the threshold for touch pad 0*/ 566 #define SENS_TOUCH_OUT_TH0 0x0000FFFF 567 #define SENS_TOUCH_OUT_TH0_M ((SENS_TOUCH_OUT_TH0_V)<<(SENS_TOUCH_OUT_TH0_S)) 568 #define SENS_TOUCH_OUT_TH0_V 0xFFFF 569 #define SENS_TOUCH_OUT_TH0_S 16 570 /* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 571 /*description: the threshold for touch pad 1*/ 572 #define SENS_TOUCH_OUT_TH1 0x0000FFFF 573 #define SENS_TOUCH_OUT_TH1_M ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S)) 574 #define SENS_TOUCH_OUT_TH1_V 0xFFFF 575 #define SENS_TOUCH_OUT_TH1_S 0 576 577 #define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x0060) 578 /* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ 579 /*description: the threshold for touch pad 2*/ 580 #define SENS_TOUCH_OUT_TH2 0x0000FFFF 581 #define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S)) 582 #define SENS_TOUCH_OUT_TH2_V 0xFFFF 583 #define SENS_TOUCH_OUT_TH2_S 16 584 /* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 585 /*description: the threshold for touch pad 3*/ 586 #define SENS_TOUCH_OUT_TH3 0x0000FFFF 587 #define SENS_TOUCH_OUT_TH3_M ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S)) 588 #define SENS_TOUCH_OUT_TH3_V 0xFFFF 589 #define SENS_TOUCH_OUT_TH3_S 0 590 591 #define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x0064) 592 /* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ 593 /*description: the threshold for touch pad 4*/ 594 #define SENS_TOUCH_OUT_TH4 0x0000FFFF 595 #define SENS_TOUCH_OUT_TH4_M ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S)) 596 #define SENS_TOUCH_OUT_TH4_V 0xFFFF 597 #define SENS_TOUCH_OUT_TH4_S 16 598 /* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 599 /*description: the threshold for touch pad 5*/ 600 #define SENS_TOUCH_OUT_TH5 0x0000FFFF 601 #define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S)) 602 #define SENS_TOUCH_OUT_TH5_V 0xFFFF 603 #define SENS_TOUCH_OUT_TH5_S 0 604 605 #define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x0068) 606 /* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ 607 /*description: the threshold for touch pad 6*/ 608 #define SENS_TOUCH_OUT_TH6 0x0000FFFF 609 #define SENS_TOUCH_OUT_TH6_M ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S)) 610 #define SENS_TOUCH_OUT_TH6_V 0xFFFF 611 #define SENS_TOUCH_OUT_TH6_S 16 612 /* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 613 /*description: the threshold for touch pad 7*/ 614 #define SENS_TOUCH_OUT_TH7 0x0000FFFF 615 #define SENS_TOUCH_OUT_TH7_M ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S)) 616 #define SENS_TOUCH_OUT_TH7_V 0xFFFF 617 #define SENS_TOUCH_OUT_TH7_S 0 618 619 #define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x006c) 620 /* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ 621 /*description: the threshold for touch pad 8*/ 622 #define SENS_TOUCH_OUT_TH8 0x0000FFFF 623 #define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S)) 624 #define SENS_TOUCH_OUT_TH8_V 0xFFFF 625 #define SENS_TOUCH_OUT_TH8_S 16 626 /* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 627 /*description: the threshold for touch pad 9*/ 628 #define SENS_TOUCH_OUT_TH9 0x0000FFFF 629 #define SENS_TOUCH_OUT_TH9_M ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S)) 630 #define SENS_TOUCH_OUT_TH9_V 0xFFFF 631 #define SENS_TOUCH_OUT_TH9_S 0 632 633 #define SENS_SAR_TOUCH_OUT1_REG (DR_REG_SENS_BASE + 0x0070) 634 /* SENS_TOUCH_MEAS_OUT0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ 635 /*description: the counter for touch pad 0*/ 636 #define SENS_TOUCH_MEAS_OUT0 0x0000FFFF 637 #define SENS_TOUCH_MEAS_OUT0_M ((SENS_TOUCH_MEAS_OUT0_V)<<(SENS_TOUCH_MEAS_OUT0_S)) 638 #define SENS_TOUCH_MEAS_OUT0_V 0xFFFF 639 #define SENS_TOUCH_MEAS_OUT0_S 16 640 /* SENS_TOUCH_MEAS_OUT1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 641 /*description: the counter for touch pad 1*/ 642 #define SENS_TOUCH_MEAS_OUT1 0x0000FFFF 643 #define SENS_TOUCH_MEAS_OUT1_M ((SENS_TOUCH_MEAS_OUT1_V)<<(SENS_TOUCH_MEAS_OUT1_S)) 644 #define SENS_TOUCH_MEAS_OUT1_V 0xFFFF 645 #define SENS_TOUCH_MEAS_OUT1_S 0 646 647 #define SENS_SAR_TOUCH_OUT2_REG (DR_REG_SENS_BASE + 0x0074) 648 /* SENS_TOUCH_MEAS_OUT2 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ 649 /*description: the counter for touch pad 2*/ 650 #define SENS_TOUCH_MEAS_OUT2 0x0000FFFF 651 #define SENS_TOUCH_MEAS_OUT2_M ((SENS_TOUCH_MEAS_OUT2_V)<<(SENS_TOUCH_MEAS_OUT2_S)) 652 #define SENS_TOUCH_MEAS_OUT2_V 0xFFFF 653 #define SENS_TOUCH_MEAS_OUT2_S 16 654 /* SENS_TOUCH_MEAS_OUT3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 655 /*description: the counter for touch pad 3*/ 656 #define SENS_TOUCH_MEAS_OUT3 0x0000FFFF 657 #define SENS_TOUCH_MEAS_OUT3_M ((SENS_TOUCH_MEAS_OUT3_V)<<(SENS_TOUCH_MEAS_OUT3_S)) 658 #define SENS_TOUCH_MEAS_OUT3_V 0xFFFF 659 #define SENS_TOUCH_MEAS_OUT3_S 0 660 661 #define SENS_SAR_TOUCH_OUT3_REG (DR_REG_SENS_BASE + 0x0078) 662 /* SENS_TOUCH_MEAS_OUT4 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ 663 /*description: the counter for touch pad 4*/ 664 #define SENS_TOUCH_MEAS_OUT4 0x0000FFFF 665 #define SENS_TOUCH_MEAS_OUT4_M ((SENS_TOUCH_MEAS_OUT4_V)<<(SENS_TOUCH_MEAS_OUT4_S)) 666 #define SENS_TOUCH_MEAS_OUT4_V 0xFFFF 667 #define SENS_TOUCH_MEAS_OUT4_S 16 668 /* SENS_TOUCH_MEAS_OUT5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 669 /*description: the counter for touch pad 5*/ 670 #define SENS_TOUCH_MEAS_OUT5 0x0000FFFF 671 #define SENS_TOUCH_MEAS_OUT5_M ((SENS_TOUCH_MEAS_OUT5_V)<<(SENS_TOUCH_MEAS_OUT5_S)) 672 #define SENS_TOUCH_MEAS_OUT5_V 0xFFFF 673 #define SENS_TOUCH_MEAS_OUT5_S 0 674 675 #define SENS_SAR_TOUCH_OUT4_REG (DR_REG_SENS_BASE + 0x007c) 676 /* SENS_TOUCH_MEAS_OUT6 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ 677 /*description: the counter for touch pad 6*/ 678 #define SENS_TOUCH_MEAS_OUT6 0x0000FFFF 679 #define SENS_TOUCH_MEAS_OUT6_M ((SENS_TOUCH_MEAS_OUT6_V)<<(SENS_TOUCH_MEAS_OUT6_S)) 680 #define SENS_TOUCH_MEAS_OUT6_V 0xFFFF 681 #define SENS_TOUCH_MEAS_OUT6_S 16 682 /* SENS_TOUCH_MEAS_OUT7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 683 /*description: the counter for touch pad 7*/ 684 #define SENS_TOUCH_MEAS_OUT7 0x0000FFFF 685 #define SENS_TOUCH_MEAS_OUT7_M ((SENS_TOUCH_MEAS_OUT7_V)<<(SENS_TOUCH_MEAS_OUT7_S)) 686 #define SENS_TOUCH_MEAS_OUT7_V 0xFFFF 687 #define SENS_TOUCH_MEAS_OUT7_S 0 688 689 #define SENS_SAR_TOUCH_OUT5_REG (DR_REG_SENS_BASE + 0x0080) 690 /* SENS_TOUCH_MEAS_OUT8 : RO ;bitpos:[31:16] ;default: 16'h0 ; */ 691 /*description: the counter for touch pad 8*/ 692 #define SENS_TOUCH_MEAS_OUT8 0x0000FFFF 693 #define SENS_TOUCH_MEAS_OUT8_M ((SENS_TOUCH_MEAS_OUT8_V)<<(SENS_TOUCH_MEAS_OUT8_S)) 694 #define SENS_TOUCH_MEAS_OUT8_V 0xFFFF 695 #define SENS_TOUCH_MEAS_OUT8_S 16 696 /* SENS_TOUCH_MEAS_OUT9 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 697 /*description: the counter for touch pad 9*/ 698 #define SENS_TOUCH_MEAS_OUT9 0x0000FFFF 699 #define SENS_TOUCH_MEAS_OUT9_M ((SENS_TOUCH_MEAS_OUT9_V)<<(SENS_TOUCH_MEAS_OUT9_S)) 700 #define SENS_TOUCH_MEAS_OUT9_V 0xFFFF 701 #define SENS_TOUCH_MEAS_OUT9_S 0 702 703 #define SENS_SAR_TOUCH_CTRL2_REG (DR_REG_SENS_BASE + 0x0084) 704 /* SENS_TOUCH_MEAS_EN_CLR : WO ;bitpos:[30] ;default: 1'h0 ; */ 705 /*description: to clear reg_touch_meas_en*/ 706 #define SENS_TOUCH_MEAS_EN_CLR (BIT(30)) 707 #define SENS_TOUCH_MEAS_EN_CLR_M (BIT(30)) 708 #define SENS_TOUCH_MEAS_EN_CLR_V 0x1 709 #define SENS_TOUCH_MEAS_EN_CLR_S 30 710 /* SENS_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[29:14] ;default: 16'h100 ; */ 711 /*description: sleep cycles for timer*/ 712 #define SENS_TOUCH_SLEEP_CYCLES 0x0000FFFF 713 #define SENS_TOUCH_SLEEP_CYCLES_M ((SENS_TOUCH_SLEEP_CYCLES_V)<<(SENS_TOUCH_SLEEP_CYCLES_S)) 714 #define SENS_TOUCH_SLEEP_CYCLES_V 0xFFFF 715 #define SENS_TOUCH_SLEEP_CYCLES_S 14 716 /* SENS_TOUCH_START_FORCE : R/W ;bitpos:[13] ;default: 1'h0 ; */ 717 /*description: 1: to start touch fsm by SW 0: to start touch fsm by timer*/ 718 #define SENS_TOUCH_START_FORCE (BIT(13)) 719 #define SENS_TOUCH_START_FORCE_M (BIT(13)) 720 #define SENS_TOUCH_START_FORCE_V 0x1 721 #define SENS_TOUCH_START_FORCE_S 13 722 /* SENS_TOUCH_START_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ 723 /*description: 1: start touch fsm valid when reg_touch_start_force is set*/ 724 #define SENS_TOUCH_START_EN (BIT(12)) 725 #define SENS_TOUCH_START_EN_M (BIT(12)) 726 #define SENS_TOUCH_START_EN_V 0x1 727 #define SENS_TOUCH_START_EN_S 12 728 /* SENS_TOUCH_START_FSM_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ 729 /*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START 730 & TOUCH_XPD is controlled by registers*/ 731 #define SENS_TOUCH_START_FSM_EN (BIT(11)) 732 #define SENS_TOUCH_START_FSM_EN_M (BIT(11)) 733 #define SENS_TOUCH_START_FSM_EN_V 0x1 734 #define SENS_TOUCH_START_FSM_EN_S 11 735 /* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[10] ;default: 1'h0 ; */ 736 /*description: fsm set 1 to indicate touch touch meas is done*/ 737 #define SENS_TOUCH_MEAS_DONE (BIT(10)) 738 #define SENS_TOUCH_MEAS_DONE_M (BIT(10)) 739 #define SENS_TOUCH_MEAS_DONE_V 0x1 740 #define SENS_TOUCH_MEAS_DONE_S 10 741 /* SENS_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 742 /*description: 10-bit register to indicate which pads are "touched"*/ 743 #define SENS_TOUCH_MEAS_EN 0x000003FF 744 #define SENS_TOUCH_MEAS_EN_M ((SENS_TOUCH_MEAS_EN_V)<<(SENS_TOUCH_MEAS_EN_S)) 745 #define SENS_TOUCH_MEAS_EN_V 0x3FF 746 #define SENS_TOUCH_MEAS_EN_S 0 747 748 #define SENS_SAR_TOUCH_ENABLE_REG (DR_REG_SENS_BASE + 0x008c) 749 /* SENS_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */ 750 /*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is 751 "touched" only if at least one of touch pad in SET1 is "touched".*/ 752 #define SENS_TOUCH_PAD_OUTEN1 0x000003FF 753 #define SENS_TOUCH_PAD_OUTEN1_M ((SENS_TOUCH_PAD_OUTEN1_V)<<(SENS_TOUCH_PAD_OUTEN1_S)) 754 #define SENS_TOUCH_PAD_OUTEN1_V 0x3FF 755 #define SENS_TOUCH_PAD_OUTEN1_S 20 756 /* SENS_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */ 757 /*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is 758 "touched" only if at least one of touch pad in SET2 is "touched".*/ 759 #define SENS_TOUCH_PAD_OUTEN2 0x000003FF 760 #define SENS_TOUCH_PAD_OUTEN2_M ((SENS_TOUCH_PAD_OUTEN2_V)<<(SENS_TOUCH_PAD_OUTEN2_S)) 761 #define SENS_TOUCH_PAD_OUTEN2_V 0x3FF 762 #define SENS_TOUCH_PAD_OUTEN2_S 10 763 /* SENS_TOUCH_PAD_WORKEN : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */ 764 /*description: Bitmap defining the working set during the measurement.*/ 765 #define SENS_TOUCH_PAD_WORKEN 0x000003FF 766 #define SENS_TOUCH_PAD_WORKEN_M ((SENS_TOUCH_PAD_WORKEN_V)<<(SENS_TOUCH_PAD_WORKEN_S)) 767 #define SENS_TOUCH_PAD_WORKEN_V 0x3FF 768 #define SENS_TOUCH_PAD_WORKEN_S 0 769 770 #define SENS_SAR_READ_CTRL2_REG (DR_REG_SENS_BASE + 0x0090) 771 /* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */ 772 /*description: Invert SAR ADC2 data*/ 773 #define SENS_SAR2_DATA_INV (BIT(29)) 774 #define SENS_SAR2_DATA_INV_M (BIT(29)) 775 #define SENS_SAR2_DATA_INV_V 0x1 776 #define SENS_SAR2_DATA_INV_S 29 777 /* SENS_SAR2_DIG_FORCE : R/W ;bitpos:[28] ;default: 1'b0 ; */ 778 /*description: 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR 779 ADC2 controlled by RTC ADC2 CTRL*/ 780 #define SENS_SAR2_DIG_FORCE (BIT(28)) 781 #define SENS_SAR2_DIG_FORCE_M (BIT(28)) 782 #define SENS_SAR2_DIG_FORCE_V 0x1 783 #define SENS_SAR2_DIG_FORCE_S 28 784 /* SENS_SAR2_PWDET_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */ 785 /*description: */ 786 #define SENS_SAR2_PWDET_FORCE (BIT(27)) 787 #define SENS_SAR2_PWDET_FORCE_M (BIT(27)) 788 #define SENS_SAR2_PWDET_FORCE_V 0x1 789 #define SENS_SAR2_PWDET_FORCE_S 27 790 /* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ 791 /*description: */ 792 #define SENS_SAR2_SAMPLE_NUM 0x000000FF 793 #define SENS_SAR2_SAMPLE_NUM_M ((SENS_SAR2_SAMPLE_NUM_V)<<(SENS_SAR2_SAMPLE_NUM_S)) 794 #define SENS_SAR2_SAMPLE_NUM_V 0xFF 795 #define SENS_SAR2_SAMPLE_NUM_S 19 796 /* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ 797 /*description: */ 798 #define SENS_SAR2_CLK_GATED (BIT(18)) 799 #define SENS_SAR2_CLK_GATED_M (BIT(18)) 800 #define SENS_SAR2_CLK_GATED_V 0x1 801 #define SENS_SAR2_CLK_GATED_S 18 802 /* SENS_SAR2_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */ 803 /*description: 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 804 11: for 12-bit width*/ 805 #define SENS_SAR2_SAMPLE_BIT 0x00000003 806 #define SENS_SAR2_SAMPLE_BIT_M ((SENS_SAR2_SAMPLE_BIT_V)<<(SENS_SAR2_SAMPLE_BIT_S)) 807 #define SENS_SAR2_SAMPLE_BIT_V 0x3 808 #define SENS_SAR2_SAMPLE_BIT_S 16 809 /* SENS_SAR2_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */ 810 /*description: sample cycles for SAR ADC2*/ 811 #define SENS_SAR2_SAMPLE_CYCLE 0x000000FF 812 #define SENS_SAR2_SAMPLE_CYCLE_M ((SENS_SAR2_SAMPLE_CYCLE_V)<<(SENS_SAR2_SAMPLE_CYCLE_S)) 813 #define SENS_SAR2_SAMPLE_CYCLE_V 0xFF 814 #define SENS_SAR2_SAMPLE_CYCLE_S 8 815 /* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ 816 /*description: clock divider*/ 817 #define SENS_SAR2_CLK_DIV 0x000000FF 818 #define SENS_SAR2_CLK_DIV_M ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S)) 819 #define SENS_SAR2_CLK_DIV_V 0xFF 820 #define SENS_SAR2_CLK_DIV_S 0 821 822 #define SENS_SAR_MEAS_START2_REG (DR_REG_SENS_BASE + 0x0094) 823 /* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 824 /*description: 1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 825 pad enable bitmap is controlled by ULP-coprocessor*/ 826 #define SENS_SAR2_EN_PAD_FORCE (BIT(31)) 827 #define SENS_SAR2_EN_PAD_FORCE_M (BIT(31)) 828 #define SENS_SAR2_EN_PAD_FORCE_V 0x1 829 #define SENS_SAR2_EN_PAD_FORCE_S 31 830 /* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ 831 /*description: SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1*/ 832 #define SENS_SAR2_EN_PAD 0x00000FFF 833 #define SENS_SAR2_EN_PAD_M ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S)) 834 #define SENS_SAR2_EN_PAD_V 0xFFF 835 #define SENS_SAR2_EN_PAD_S 19 836 /* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ 837 /*description: 1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 838 controller is started by ULP-coprocessor*/ 839 #define SENS_MEAS2_START_FORCE (BIT(18)) 840 #define SENS_MEAS2_START_FORCE_M (BIT(18)) 841 #define SENS_MEAS2_START_FORCE_V 0x1 842 #define SENS_MEAS2_START_FORCE_S 18 843 /* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ 844 /*description: SAR ADC2 controller (in RTC) starts conversion only active when 845 reg_meas2_start_force = 1*/ 846 #define SENS_MEAS2_START_SAR (BIT(17)) 847 #define SENS_MEAS2_START_SAR_M (BIT(17)) 848 #define SENS_MEAS2_START_SAR_V 0x1 849 #define SENS_MEAS2_START_SAR_S 17 850 /* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ 851 /*description: SAR ADC2 conversion done indication*/ 852 #define SENS_MEAS2_DONE_SAR (BIT(16)) 853 #define SENS_MEAS2_DONE_SAR_M (BIT(16)) 854 #define SENS_MEAS2_DONE_SAR_V 0x1 855 #define SENS_MEAS2_DONE_SAR_S 16 856 /* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ 857 /*description: SAR ADC2 data*/ 858 #define SENS_MEAS2_DATA_SAR 0x0000FFFF 859 #define SENS_MEAS2_DATA_SAR_M ((SENS_MEAS2_DATA_SAR_V)<<(SENS_MEAS2_DATA_SAR_S)) 860 #define SENS_MEAS2_DATA_SAR_V 0xFFFF 861 #define SENS_MEAS2_DATA_SAR_S 0 862 863 #define SENS_SAR_DAC_CTRL1_REG (DR_REG_SENS_BASE + 0x0098) 864 /* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */ 865 /*description: 1: invert PDAC_CLK*/ 866 #define SENS_DAC_CLK_INV (BIT(25)) 867 #define SENS_DAC_CLK_INV_M (BIT(25)) 868 #define SENS_DAC_CLK_INV_V 0x1 869 #define SENS_DAC_CLK_INV_S 25 870 /* SENS_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */ 871 /*description: 1: force PDAC_CLK to high*/ 872 #define SENS_DAC_CLK_FORCE_HIGH (BIT(24)) 873 #define SENS_DAC_CLK_FORCE_HIGH_M (BIT(24)) 874 #define SENS_DAC_CLK_FORCE_HIGH_V 0x1 875 #define SENS_DAC_CLK_FORCE_HIGH_S 24 876 /* SENS_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */ 877 /*description: 1: force PDAC_CLK to low*/ 878 #define SENS_DAC_CLK_FORCE_LOW (BIT(23)) 879 #define SENS_DAC_CLK_FORCE_LOW_M (BIT(23)) 880 #define SENS_DAC_CLK_FORCE_LOW_V 0x1 881 #define SENS_DAC_CLK_FORCE_LOW_S 23 882 /* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */ 883 /*description: 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA*/ 884 #define SENS_DAC_DIG_FORCE (BIT(22)) 885 #define SENS_DAC_DIG_FORCE_M (BIT(22)) 886 #define SENS_DAC_DIG_FORCE_V 0x1 887 #define SENS_DAC_DIG_FORCE_S 22 888 /* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */ 889 /*description: */ 890 #define SENS_DEBUG_BIT_SEL 0x0000001F 891 #define SENS_DEBUG_BIT_SEL_M ((SENS_DEBUG_BIT_SEL_V)<<(SENS_DEBUG_BIT_SEL_S)) 892 #define SENS_DEBUG_BIT_SEL_V 0x1F 893 #define SENS_DEBUG_BIT_SEL_S 17 894 /* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ 895 /*description: 1: enable CW generator 0: disable CW generator*/ 896 #define SENS_SW_TONE_EN (BIT(16)) 897 #define SENS_SW_TONE_EN_M (BIT(16)) 898 #define SENS_SW_TONE_EN_V 0x1 899 #define SENS_SW_TONE_EN_S 16 900 /* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ 901 /*description: frequency step for CW generator can be used to adjust the frequency*/ 902 #define SENS_SW_FSTEP 0x0000FFFF 903 #define SENS_SW_FSTEP_M ((SENS_SW_FSTEP_V)<<(SENS_SW_FSTEP_S)) 904 #define SENS_SW_FSTEP_V 0xFFFF 905 #define SENS_SW_FSTEP_S 0 906 907 #define SENS_SAR_DAC_CTRL2_REG (DR_REG_SENS_BASE + 0x009c) 908 /* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */ 909 /*description: 1: to select CW generator as source to PDAC2_DAC[7:0] 0: to 910 select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/ 911 #define SENS_DAC_CW_EN2 (BIT(25)) 912 #define SENS_DAC_CW_EN2_M (BIT(25)) 913 #define SENS_DAC_CW_EN2_V 0x1 914 #define SENS_DAC_CW_EN2_S 25 915 /* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */ 916 /*description: 1: to select CW generator as source to PDAC1_DAC[7:0] 0: to 917 select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/ 918 #define SENS_DAC_CW_EN1 (BIT(24)) 919 #define SENS_DAC_CW_EN1_M (BIT(24)) 920 #define SENS_DAC_CW_EN1_V 0x1 921 #define SENS_DAC_CW_EN1_S 24 922 /* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ 923 /*description: 00: do not invert any bits 01: invert all bits 10: invert MSB 924 11: invert all bits except MSB*/ 925 #define SENS_DAC_INV2 0x00000003 926 #define SENS_DAC_INV2_M ((SENS_DAC_INV2_V)<<(SENS_DAC_INV2_S)) 927 #define SENS_DAC_INV2_V 0x3 928 #define SENS_DAC_INV2_S 22 929 /* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */ 930 /*description: 00: do not invert any bits 01: invert all bits 10: invert MSB 931 11: invert all bits except MSB*/ 932 #define SENS_DAC_INV1 0x00000003 933 #define SENS_DAC_INV1_M ((SENS_DAC_INV1_V)<<(SENS_DAC_INV1_S)) 934 #define SENS_DAC_INV1_V 0x3 935 #define SENS_DAC_INV1_S 20 936 /* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ 937 /*description: 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/ 938 #define SENS_DAC_SCALE2 0x00000003 939 #define SENS_DAC_SCALE2_M ((SENS_DAC_SCALE2_V)<<(SENS_DAC_SCALE2_S)) 940 #define SENS_DAC_SCALE2_V 0x3 941 #define SENS_DAC_SCALE2_S 18 942 /* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ 943 /*description: 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/ 944 #define SENS_DAC_SCALE1 0x00000003 945 #define SENS_DAC_SCALE1_M ((SENS_DAC_SCALE1_V)<<(SENS_DAC_SCALE1_S)) 946 #define SENS_DAC_SCALE1_V 0x3 947 #define SENS_DAC_SCALE1_S 16 948 /* SENS_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ 949 /*description: DC offset for DAC2 CW generator*/ 950 #define SENS_DAC_DC2 0x000000FF 951 #define SENS_DAC_DC2_M ((SENS_DAC_DC2_V)<<(SENS_DAC_DC2_S)) 952 #define SENS_DAC_DC2_V 0xFF 953 #define SENS_DAC_DC2_S 8 954 /* SENS_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ 955 /*description: DC offset for DAC1 CW generator*/ 956 #define SENS_DAC_DC1 0x000000FF 957 #define SENS_DAC_DC1_M ((SENS_DAC_DC1_V)<<(SENS_DAC_DC1_S)) 958 #define SENS_DAC_DC1_V 0xFF 959 #define SENS_DAC_DC1_S 0 960 961 #define SENS_SAR_MEAS_CTRL2_REG (DR_REG_SENS_BASE + 0x0a0) 962 /* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[18:17] ;default: 2'b0 ; */ 963 /*description: */ 964 #define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 965 #define SENS_AMP_SHORT_REF_GND_FORCE_M ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S)) 966 #define SENS_AMP_SHORT_REF_GND_FORCE_V 0x3 967 #define SENS_AMP_SHORT_REF_GND_FORCE_S 17 968 #define SENS_AMP_SHORT_REF_GND_FORCE_FSM 0 // Use FSM to control power down 969 #define SENS_AMP_SHORT_REF_GND_FORCE_PD 2 // Force power down 970 #define SENS_AMP_SHORT_REF_GND_FORCE_PU 3 // Force power up 971 /* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ 972 /*description: */ 973 #define SENS_AMP_SHORT_REF_FORCE 0x00000003 974 #define SENS_AMP_SHORT_REF_FORCE_M ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S)) 975 #define SENS_AMP_SHORT_REF_FORCE_V 0x3 976 #define SENS_AMP_SHORT_REF_FORCE_S 15 977 #define SENS_AMP_SHORT_REF_FORCE_FSM 0 // Use FSM to control power down 978 #define SENS_AMP_SHORT_REF_FORCE_PD 2 // Force power down 979 #define SENS_AMP_SHORT_REF_FORCE_PU 3 // Force power up 980 /* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ 981 /*description: */ 982 #define SENS_AMP_RST_FB_FORCE 0x00000003 983 #define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S)) 984 #define SENS_AMP_RST_FB_FORCE_V 0x3 985 #define SENS_AMP_RST_FB_FORCE_S 13 986 #define SENS_AMP_RST_FB_FORCE_FSM 0 // Use FSM to control power down 987 #define SENS_AMP_RST_FB_FORCE_PD 2 // Force power down 988 #define SENS_AMP_RST_FB_FORCE_PU 3 // Force power up 989 /* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[12:11] ;default: 2'b0 ; */ 990 /*description: */ 991 #define SENS_SAR2_RSTB_FORCE 0x00000003 992 #define SENS_SAR2_RSTB_FORCE_M ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S)) 993 #define SENS_SAR2_RSTB_FORCE_V 0x3 994 #define SENS_SAR2_RSTB_FORCE_S 11 995 #define SENS_SAR2_RSTB_FORCE_FSM 0 // Use FSM to control power down 996 #define SENS_SAR2_RSTB_FORCE_PD 2 // Force power down 997 #define SENS_SAR2_RSTB_FORCE_PU 3 // Force power up 998 /* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ 999 /*description: */ 1000 #define SENS_SAR_RSTB_FSM_IDLE (BIT(10)) 1001 #define SENS_SAR_RSTB_FSM_IDLE_M (BIT(10)) 1002 #define SENS_SAR_RSTB_FSM_IDLE_V 0x1 1003 #define SENS_SAR_RSTB_FSM_IDLE_S 10 1004 /* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1005 /*description: */ 1006 #define SENS_XPD_SAR_FSM_IDLE (BIT(9)) 1007 #define SENS_XPD_SAR_FSM_IDLE_M (BIT(9)) 1008 #define SENS_XPD_SAR_FSM_IDLE_V 0x1 1009 #define SENS_XPD_SAR_FSM_IDLE_S 9 1010 /* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1011 /*description: */ 1012 #define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(8)) 1013 #define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(8)) 1014 #define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 1015 #define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 8 1016 /* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1017 /*description: */ 1018 #define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(7)) 1019 #define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(7)) 1020 #define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1 1021 #define SENS_AMP_SHORT_REF_FSM_IDLE_S 7 1022 /* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1023 /*description: */ 1024 #define SENS_AMP_RST_FB_FSM_IDLE (BIT(6)) 1025 #define SENS_AMP_RST_FB_FSM_IDLE_M (BIT(6)) 1026 #define SENS_AMP_RST_FB_FSM_IDLE_V 0x1 1027 #define SENS_AMP_RST_FB_FSM_IDLE_S 6 1028 /* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1029 /*description: */ 1030 #define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(5)) 1031 #define SENS_XPD_SAR_AMP_FSM_IDLE_M (BIT(5)) 1032 #define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x1 1033 #define SENS_XPD_SAR_AMP_FSM_IDLE_S 5 1034 /* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1035 /*description: */ 1036 #define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(4)) 1037 #define SENS_SAR1_DAC_XPD_FSM_IDLE_M (BIT(4)) 1038 #define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x1 1039 #define SENS_SAR1_DAC_XPD_FSM_IDLE_S 4 1040 /* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */ 1041 /*description: */ 1042 #define SENS_SAR1_DAC_XPD_FSM 0x0000000F 1043 #define SENS_SAR1_DAC_XPD_FSM_M ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S)) 1044 #define SENS_SAR1_DAC_XPD_FSM_V 0xF 1045 #define SENS_SAR1_DAC_XPD_FSM_S 0 1046 1047 #define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0x00F8) 1048 /* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1049 /*description: */ 1050 #define SENS_SAR_NOUSE 0xFFFFFFFF 1051 #define SENS_SAR_NOUSE_M ((SENS_SAR_NOUSE_V)<<(SENS_SAR_NOUSE_S)) 1052 #define SENS_SAR_NOUSE_V 0xFFFFFFFF 1053 #define SENS_SAR_NOUSE_S 0 1054 1055 #define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0x00FC) 1056 /* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605180 ; */ 1057 /*description: */ 1058 #define SENS_SAR_DATE 0x0FFFFFFF 1059 #define SENS_SAR_DATE_M ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S)) 1060 #define SENS_SAR_DATE_V 0xFFFFFFF 1061 #define SENS_SAR_DATE_S 0 1062 1063 1064 1065 1066 #endif /*_SOC_SENS_REG_H_ */ 1067
