SENS_MEM_WR_ADDR_INIT_V (reference) in projects: hal_espressif-3.6.0

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/hal_espressif-3.6.0/components/soc/esp32/include/soc/
D	sens_reg.h	`296 #define SENS_MEM_WR_ADDR_INIT_M ((SENS_MEM_WR_ADDR_INIT_V)<<(SENS_MEM_WR_ADDR_INIT_S)) 297 #define SENS_MEM_WR_ADDR_INIT_V 0x7FF macro`

TraceRecorderSource-2.7.6
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Zephyr-Core-2.7.6
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