1 // Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #ifndef _ROM_RTC_H_
16 #define _ROM_RTC_H_
17
18 #include "ets_sys.h"
19
20 #include <stdbool.h>
21 #include <stdint.h>
22
23 #include "soc/soc.h"
24 #include "soc/rtc_cntl_reg.h"
25 #include "soc/reset_reasons.h"
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 /** \defgroup rtc_apis, rtc registers and memory related apis
32 * @brief rtc apis
33 */
34
35 /** @addtogroup rtc_apis
36 * @{
37 */
38
39 /**************************************************************************************
40 * Note: *
41 * Some Rtc memory and registers are used, in ROM or in internal library. *
42 * Please do not use reserved or used rtc memory or registers. *
43 * *
44 *************************************************************************************
45 * RTC Memory & Store Register usage
46 *************************************************************************************
47 * rtc memory addr type size usage
48 * 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
49 * 0x3ff61000+SIZE_CP Slow 8192-SIZE_CP
50 *
51 * 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code
52 *
53 *************************************************************************************
54 * RTC store registers usage
55 * RTC_CNTL_STORE0_REG Reserved
56 * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
57 * RTC_CNTL_STORE2_REG Boot time, low word
58 * RTC_CNTL_STORE3_REG Boot time, high word
59 * RTC_CNTL_STORE4_REG External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code.
60 * RTC_CNTL_STORE5_REG APB bus frequency
61 * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
62 * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
63 *************************************************************************************
64 */
65
66 #define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
67 #define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
68 #define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
69 #define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
70 #define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
71 #define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
72 #define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
73 #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
74
75 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
76
77 typedef enum {
78 AWAKE = 0, //<CPU ON
79 LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
80 DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
81 } SLEEP_MODE;
82
83 typedef enum {
84 NO_MEAN = 0,
85 POWERON_RESET = 1, /**<1, Vbat power on reset*/
86 SW_RESET = 3, /**<3, Software reset digital core*/
87 OWDT_RESET = 4, /**<4, Legacy watch dog reset digital core*/
88 DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
89 SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/
90 TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
91 TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
92 RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
93 INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
94 TGWDT_CPU_RESET = 11, /**<11, Time Group reset CPU*/
95 SW_CPU_RESET = 12, /**<12, Software reset CPU*/
96 RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
97 EXT_CPU_RESET = 14, /**<14, for APP CPU, reseted by PRO CPU*/
98 RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
99 RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/
100 } RESET_REASON;
101
102 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
103 _Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
104 _Static_assert((soc_reset_reason_t)SW_RESET == RESET_REASON_CORE_SW, "SW_RESET != RESET_REASON_CORE_SW");
105 _Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
106 _Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
107 _Static_assert((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
108 _Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
109 _Static_assert((soc_reset_reason_t)TGWDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TGWDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
110 _Static_assert((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU0_SW, "SW_CPU_RESET != RESET_REASON_CPU0_SW");
111 _Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
112 _Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
113 _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
114
115 typedef enum {
116 NO_SLEEP = 0,
117 EXT_EVENT0_TRIG = BIT0,
118 EXT_EVENT1_TRIG = BIT1,
119 GPIO_TRIG = BIT2,
120 TIMER_EXPIRE = BIT3,
121 SDIO_TRIG = BIT4,
122 MAC_TRIG = BIT5,
123 UART0_TRIG = BIT6,
124 UART1_TRIG = BIT7,
125 TOUCH_TRIG = BIT8,
126 SAR_TRIG = BIT9,
127 BT_TRIG = BIT10
128 } WAKEUP_REASON;
129
130 typedef enum {
131 DISEN_WAKEUP = NO_SLEEP,
132 EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
133 EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
134 GPIO_TRIG_EN = GPIO_TRIG,
135 TIMER_EXPIRE_EN = TIMER_EXPIRE,
136 SDIO_TRIG_EN = SDIO_TRIG,
137 MAC_TRIG_EN = MAC_TRIG,
138 UART0_TRIG_EN = UART0_TRIG,
139 UART1_TRIG_EN = UART1_TRIG,
140 TOUCH_TRIG_EN = TOUCH_TRIG,
141 SAR_TRIG_EN = SAR_TRIG,
142 BT_TRIG_EN = BT_TRIG
143 } WAKEUP_ENABLE;
144
145 typedef enum {
146 NO_INT = 0,
147 WAKEUP_INT = BIT0,
148 REJECT_INT = BIT1,
149 SDIO_IDLE_INT = BIT2,
150 RTC_WDT_INT = BIT3,
151 RTC_TIME_VALID_INT = BIT4
152 } RTC_INT_REASON;
153
154 typedef enum {
155 DISEN_INT = 0,
156 WAKEUP_INT_EN = WAKEUP_INT,
157 REJECT_INT_EN = REJECT_INT,
158 SDIO_IDLE_INT_EN = SDIO_IDLE_INT,
159 RTC_WDT_INT_EN = RTC_WDT_INT,
160 RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
161 } RTC_INT_EN;
162
163 /**
164 * @brief Get the reset reason for CPU.
165 *
166 * @param int cpu_no : CPU no.
167 *
168 * @return RESET_REASON
169 */
170 RESET_REASON rtc_get_reset_reason(int cpu_no);
171
172 /**
173 * @brief Get the wakeup cause for CPU.
174 *
175 * @param int cpu_no : CPU no.
176 *
177 * @return WAKEUP_REASON
178 */
179 WAKEUP_REASON rtc_get_wakeup_cause(void);
180
181 /**
182 * @brief Get CRC for Fast RTC Memory.
183 *
184 * @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
185 *
186 * @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
187 *
188 * @return uint32_t : CRC32 result
189 */
190 uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
191
192 /**
193 * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
194 *
195 * @param None
196 *
197 * @return None
198 */
199 void set_rtc_memory_crc(void);
200
201 /**
202 * @brief Suppress ROM log by setting specific RTC control register.
203 * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
204 *
205 * @param None
206 *
207 * @return None
208 */
rtc_suppress_rom_log(void)209 static inline void rtc_suppress_rom_log(void)
210 {
211 /* To disable logging in the ROM, only the least significant bit of the register is used,
212 * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
213 * you need to write to this register in the same format.
214 * Namely, the upper 16 bits and lower should be the same.
215 */
216 REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
217 }
218
219 /**
220 * @brief Software Reset digital core.
221 *
222 * It is not recommended to use this function in esp-idf, use
223 * esp_restart() instead.
224 *
225 * @param None
226 *
227 * @return None
228 */
229 void __attribute__((noreturn)) software_reset(void);
230
231 /**
232 * @brief Software Reset digital core.
233 *
234 * It is not recommended to use this function in esp-idf, use
235 * esp_restart() instead.
236 *
237 * @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
238 *
239 * @return None
240 */
241 void software_reset_cpu(int cpu_no);
242
243 /**
244 * @}
245 */
246
247 #ifdef __cplusplus
248 }
249 #endif
250
251 #endif /* _ROM_RTC_H_ */
252
