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Searched refs:RTC_CNTL_SOC_CLK_SEL (Results 1 – 4 of 4) sorted by relevance

/hal_espressif-3.6.0/components/soc/src/esp32/
Drtc_clk.c242 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) { in rtc_clk_apll_enable()
427 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL); in rtc_clk_cpu_freq_to_xtal()
442 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M); in rtc_clk_cpu_freq_to_8m()
497 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL); in rtc_clk_cpu_freq_to_pll_mhz()
612 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); in rtc_clk_cpu_freq_set_config()
640 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32/
Drtc_clk.c277 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) { in rtc_clk_apll_enable()
462 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL); in rtc_clk_cpu_freq_to_xtal()
477 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M); in rtc_clk_cpu_freq_to_8m()
532 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL); in rtc_clk_cpu_freq_to_pll_mhz()
647 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); in rtc_clk_cpu_freq_set_config()
675 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config()
Drtc_clk_init.c49 if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) == RTC_CNTL_SOC_CLK_SEL_PLL) { in rtc_clk_init()
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
Drtc_cntl_reg.h901 #define RTC_CNTL_SOC_CLK_SEL 0x00000003 macro